Mostly cosmetic clean-up of comments
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32/kl_idle.c
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* arch/arm/src/kl/kl_idle.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32/kl_irq.c
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* arch/arm/src/kl/kl_irq.c
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*
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -1,6 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32/kl_irqprio.c
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* arch/arm/src/chip/kl_irqprio.c
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* arch/arm/src/kl/kl_irqprio.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -693,12 +693,10 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
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* Initialize one timer for use with the upper_level PWM driver.
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*
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* Input Parameters:
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* timer - A number identifying the timer use. The number of valid timer
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* IDs varies with the STM32 MCU and MCU family but is somewhere in
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* the range of {1,..,14}.
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* timer - A number identifying the timer use.
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*
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* Returned Value:
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* On success, a pointer to the STM32 lower half PWM driver is returned.
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* On success, a pointer to the KL lower half PWM driver is returned.
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* NULL is returned on any failure.
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*
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****************************************************************************/
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@ -77,13 +77,9 @@
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* configuration settings:
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*
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* CONFIG_KL_TPMx_CHANNEL - Specifies the timer output channel {1,..,4}
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* PWM_TPMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case
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* PWM_TPMx_CHn - One of the values defined in chip/kl*_pinmap.h. In the case
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* where there are multiple pin selections, the correct setting must be provided
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* in the arch/board/board.h file.
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*
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* NOTE: The STM32 timers are each capable of generating different signals on
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* each of the four channels with different duty cycles. That capability is
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* not supported by this driver: Only one output channel per timer.
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*/
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#ifdef CONFIG_KL_TPM0_PWM
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@ -175,12 +171,10 @@ extern "C" {
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* Initialize one timer for use with the upper_level PWM driver.
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*
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* Input Parameters:
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* timer - A number identifying the timer use. The number of valid timer
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* IDs varies with the STM32 MCU and MCU family but is somewhere in
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* the range of {1,..,14}.
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* timer - A number identifying the timer use.
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*
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* Returned Value:
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* On success, a pointer to the STM32 lower half PWM driver is returned.
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* On success, a pointer to the KL lower half PWM driver is returned.
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* NULL is returned on any failure.
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*
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************************************************************************************/
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@ -75,6 +75,6 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
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CHIP_CSRCS += sam_userspace.c
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endif
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ifeq ($(CONFIG_NUTTX_KERNEL),y)
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ifeq ($(CONFIG_ARCH_IRQPRIO),y)
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CHIP_CSRCS += sam_irqprio.c
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endif
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@ -1,6 +1,5 @@
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/****************************************************************************
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* arch/arm/src/stm32/kl_irqprio.c
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* arch/arm/src/chip/kl_irqprio.c
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* arch/arm/src/samd/sam_irqprio.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -351,17 +351,19 @@
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#define BOARD_FLASH_WAITSTATES 1
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/* SERCOM definitions ***************************************************************/
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/* SERCOM4 is available on connectors EXT1 and EXT3
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/* SERCOM4 is available on connectors EXT1, EXT2, and EXT3
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*
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* PIN EXT1 EXT3 GPIO Function
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* ---- ---- ------ -----------
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* 13 PB09 PB13 SERCOM4 / USART RX
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* 14 PB08 PB12 SERCOM4 / USART TX
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* 19 19 GND
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* 20 20 VCC
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* PIN EXT1 EXT2 EXT3 GPIO Function
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* ---- ---- ---- ---- ------------------
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* 13 PB09 PB13 PB11 SERCOM4 / USART RX
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* 14 PB08 PB12 PB12 SERCOM4 / USART TX
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* 19 GND GND GND N/A
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* 20 VCC VCC VCC N/A
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*
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* If you have a TTL to RS-232 converter then this is the most convenient
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* serial console to use. It is the default in all of these configurations.
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* serial console to use (because you don't lose the console device each time
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* you lose the USB connection). It is the default in all of the SAMD20
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* configurations.
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*/
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#define BOARD_SERCOM4_GCLKGEN GCLK_CLKCTRL_GEN0
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