First AVR compile
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3681 42af7a65-404d-4744-a932-0658087f49c3
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@ -46,7 +46,20 @@
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* Pre-processor definitions
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* Pre-processor definitions
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****************************************************************************/
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****************************************************************************/
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#define STACKBASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
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/* Stack is allocated just after .bss and before the heap */
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#define STACKBASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-1)
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/* The RAMPZ register is only available for CPUs with more than 64Kb of FLASH.
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* Only the AT90USB646, 647, 1286, and 1287 are supported by this file.
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*
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* - Support for the EPLMX instructions is assumed if RAMPZ is present
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* - If RAMPZ is not present, support for LPMX is assumed
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*/
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#if defined(CONFIG_ARCH_CHIP_AT90USB1286) || defined(CONFIG_ARCH_CHIP_AT90USB1286)
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# define HAVE_RAMPZ 1
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#endif
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/****************************************************************************
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/****************************************************************************
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* External Symbols
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* External Symbols
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@ -180,6 +193,7 @@ __start:
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/* Copy initial global data values from FLASH into RAM */
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/* Copy initial global data values from FLASH into RAM */
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#ifdef HAVE_RAMPZ
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ldi r17, hi8(_edata)
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ldi r17, hi8(_edata)
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ldi r26, lo8(_sdata)
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ldi r26, lo8(_sdata)
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ldi r27, hi8(_sdata)
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ldi r27, hi8(_sdata)
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@ -197,6 +211,22 @@ __start:
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cpi r26, lo8(_edata)
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cpi r26, lo8(_edata)
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cpc r27, r17
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cpc r27, r17
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brne .Lcopyloop
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brne .Lcopyloop
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#else
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ldi r17, hi8(_edata)
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ldi r26, lo8(_sdata)
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ldi r27, hi8(_sdata)
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ldi r30, lo8(_eronly)
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ldi r31, hi8(_eronly)
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rjmp .Lcopystart
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.Lcopyloop:
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lpm r0, Z+
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st X+, r0
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.Lcopystart:
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cpi r26, lo8(_edata)
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cpc r27, r17
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brne .Lcopyloop
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#endif
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/* Clear uninitialized data */
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/* Clear uninitialized data */
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@ -46,8 +46,20 @@
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* Pre-processor definitions
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* Pre-processor definitions
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****************************************************************************/
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****************************************************************************/
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/* Stack is allocated just after .bss and before the heap */
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#define STACKBASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
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#define STACKBASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
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/* The RAMPZ register is only available for CPUs with more than 64Kb of FLASH.
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* At present, only the ATMega128 is supported so RAMPZ should always be
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* available.
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*
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* - Support for the EPLMX instructions is assumed if RAMPZ is present
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* - If RAMPZ is not present, support for LPMX is assumed
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*/
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#define HAVE_RAMPZ 1
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/****************************************************************************
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/****************************************************************************
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* External Symbols
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* External Symbols
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****************************************************************************/
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****************************************************************************/
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@ -174,6 +186,7 @@ __start:
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/* Copy initial global data values from FLASH into RAM */
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/* Copy initial global data values from FLASH into RAM */
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#ifdef HAVE_RAMPZ
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ldi r17, hi8(_edata)
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ldi r17, hi8(_edata)
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ldi r26, lo8(_sdata)
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ldi r26, lo8(_sdata)
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ldi r27, hi8(_sdata)
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ldi r27, hi8(_sdata)
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@ -191,6 +204,22 @@ __start:
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cpi r26, lo8(_edata)
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cpi r26, lo8(_edata)
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cpc r27, r17
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cpc r27, r17
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brne .Lcopyloop
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brne .Lcopyloop
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#else
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ldi r17, hi8(_edata)
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ldi r26, lo8(_sdata)
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ldi r27, hi8(_sdata)
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ldi r30, lo8(_eronly)
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ldi r31, hi8(_eronly)
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rjmp .Lcopystart
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.Lcopyloop:
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lpm r0, Z+
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st X+, r0
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.Lcopystart:
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cpi r26, lo8(_edata)
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cpc r27, r17
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brne .Lcopyloop
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#endif
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/* Clear uninitialized data */
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/* Clear uninitialized data */
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@ -144,8 +144,6 @@ SECTIONS
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_ebss = ABSOLUTE(.);
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_ebss = ABSOLUTE(.);
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} > sram
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} > sram
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.bss SIZEOF(.data) + ADDR(.data) :
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/* Global data not cleared after reset. */
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/* Global data not cleared after reset. */
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.noinit :
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.noinit :
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