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Add missing NSH configuration settings. Correct some conditional logic for STM32 FALSH pre-fetch settings. From Lorenz Meier

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This commit is contained in:
Gregory Nutt 2013-06-02 13:16:35 -06:00
parent b20b0a1839
commit 7bfa4e299c
4 changed files with 8 additions and 3 deletions
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5
ChangeLog
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@ -4858,3 +4858,8 @@
* arch/arm/src/sam3u: Renamed files to sam_* vs. sam3u_*.
Eliminated sam3u_internal.h; instead uses individual header
files for each SAM interface block (2013-6-2).
* arch/arm/src/stm32/stm32f20xxx_rcc.c and stm32f40xxx_rcc.c, and
configs/mikroe-stm32f4/src/up_clockconfig.c. Correct some bad
conditional compilation (CONFIG_ missing from setting name). This
affects some STM32 FLASH pre-fetch settings. From Lorenz Meier
(2013-6-2).

2
arch/arm/src/stm32/stm32f20xxx_rcc.c
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@ -631,7 +631,7 @@ static void stm32_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef STM32_FLASH_PREFETCH
#ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);

2
arch/arm/src/stm32/stm32f40xxx_rcc.c
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@ -669,7 +669,7 @@ static void stm32_stdclockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef STM32_FLASH_PREFETCH
#ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);

2
configs/mikroe-stm32f4/src/up_clockconfig.c
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@ -128,7 +128,7 @@ void stm32_board_clockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef STM32_FLASH_PREFETCH
#ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);