icjx: add support for multiple pin read/write
This commit implements functions icjx_multireadpin and icjx_multiwritepin. These functions can be used for multiple pin access (read/write) if CONFIG_IOEXPANDER_MULTIPIN is selected. This access is generally faster than one by one pin and may simplify user application. Changes to general functions icjx_read and icjx_write were also required to provide support for multiple data send/receive. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc
Xiang Xiao
parent
e622e95d5b
commit
7c7e163e23
@ -45,7 +45,8 @@
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#define ICJX_NOP 0x00
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#define ICJX_RNW 0x01
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#define ICJX_NOB 0x0f
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#define ICJX_NOB1 0x0f
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#define ICJX_NOB2 0x1e
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#define ICJX_CONTROL 0x59
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/****************************************************************************
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@ -77,9 +78,9 @@ static void icjx_deselect(FAR struct spi_dev_s *spi,
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/* Read/Write helpers */
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static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg,
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uint8_t *data);
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uint16_t *data, int nob);
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static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg,
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uint8_t data);
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uint16_t data, int nob);
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/* I/O Expander Methods */
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@ -93,8 +94,8 @@ static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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FAR bool *value);
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#ifdef CONFIG_IOEXPANDER_MULTIPIN
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static int icjx_multiwritepin(FAR struct ioexpander_dev_s *dev,
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FAR const uint8_t *pins, FAR bool *values,
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int count);
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FAR const uint8_t *pins,
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FAR const bool *values, int count);
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static int icjx_multireadpin(FAR struct ioexpander_dev_s *dev,
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FAR const uint8_t *pins, FAR bool *values,
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int count);
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@ -207,16 +208,17 @@ static void icjx_deselect(FAR struct spi_dev_s *spi,
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*
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****************************************************************************/
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static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg, uint8_t *data)
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static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg,
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uint16_t *data, int nob)
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{
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uint8_t startaddr;
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uint8_t tx_buffer[5];
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uint8_t rx_buffer[5];
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uint8_t tx_buffer[6];
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uint8_t rx_buffer[6];
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startaddr = (priv->config->addr << 6) | (reg << 1) | ICJX_RNW;
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tx_buffer[0] = startaddr;
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tx_buffer[1] = ICJX_NOP;
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tx_buffer[2] = ICJX_NOB;
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tx_buffer[2] = nob;
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icjx_select(priv->spi, priv->config, 8);
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SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 3);
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@ -225,7 +227,20 @@ static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg, uint8_t *data)
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if (priv->config->verification)
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{
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tx_buffer[0] = rx_buffer[2];
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if (nob == ICJX_NOB2)
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{
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tx_buffer[0] = rx_buffer[2];
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SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 1);
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*data |= rx_buffer[0] << 8;
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tx_buffer[0] = rx_buffer[0];
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startaddr = (priv->config->addr << 6) |
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((reg + 1) << 1) | ICJX_RNW;
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}
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else
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{
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tx_buffer[0] = rx_buffer[2];
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}
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tx_buffer[1] = ICJX_CONTROL;
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SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 2);
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}
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@ -268,24 +283,34 @@ static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg, uint8_t *data)
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*
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****************************************************************************/
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static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg, uint8_t data)
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static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg,
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uint16_t data, int nob)
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{
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uint8_t startaddr;
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uint8_t bytes_to_exchange;
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uint8_t tx_buffer[5];
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uint8_t rx_buffer[5];
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uint8_t tx_buffer[6];
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uint8_t rx_buffer[6];
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int ver_idx;
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int data_len;
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bytes_to_exchange = 3;
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data_len = 1;
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ver_idx = 2;
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bytes_to_exchange = 0;
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startaddr = (priv->config->addr << 6) | (reg << 1);
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tx_buffer[0] = startaddr;
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tx_buffer[1] = ICJX_NOB;
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tx_buffer[2] = data;
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tx_buffer[bytes_to_exchange++] = startaddr;
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tx_buffer[bytes_to_exchange++] = nob;
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tx_buffer[bytes_to_exchange++] = data & 0xff;
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if (nob == ICJX_NOB2)
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{
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data_len = 2;
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tx_buffer[bytes_to_exchange++] = (data >> 8) & 0xff;
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}
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if (priv->config->verification)
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{
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tx_buffer[3] = startaddr;
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tx_buffer[4] = ICJX_CONTROL;
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bytes_to_exchange = 5;
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tx_buffer[bytes_to_exchange++] = (priv->config->addr << 6) |
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((reg + (data_len - 1)) << 1);
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tx_buffer[bytes_to_exchange++] = ICJX_CONTROL;
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}
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icjx_select(priv->spi, priv->config, 8);
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@ -294,23 +319,26 @@ static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg, uint8_t data)
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if (priv->config->verification)
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{
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if (rx_buffer[2] != ICJX_NOB)
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if (rx_buffer[ver_idx++] != nob)
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{
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gpioerr("ERROR: Start address verification error for register"
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"0x%x!\n", reg);
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return -EIO;
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}
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if (rx_buffer[3] != data)
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for (int i = 0; i < data_len; i++)
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{
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gpioerr("ERROR: Data verification error for register 0x%x!\n",
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reg);
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return -EIO;
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if (rx_buffer[ver_idx++] != ((data >> (i * 8)) & 0xff))
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{
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gpioerr("ERROR: Data verification error for register 0x%x!\n",
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reg);
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return -EIO;
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}
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}
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if (rx_buffer[4] != ICJX_CONTROL)
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if (rx_buffer[ver_idx++] != ICJX_CONTROL)
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{
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gpioerr("ERROR: Data verification error for register 0x%x!\n",
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gpioerr("ERROR: Control verification error for register 0x%x!\n",
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reg);
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return -EIO;
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}
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@ -341,7 +369,7 @@ static int icjx_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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{
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FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev;
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uint8_t outpins;
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uint8_t out_set;
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uint16_t out_set;
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uint8_t regaddr;
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int ret;
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@ -379,7 +407,7 @@ static int icjx_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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outpins = (priv->outpins >> 8) & 0xff;
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}
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ret = icjx_read(priv, regaddr, &out_set);
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ret = icjx_read(priv, regaddr, &out_set, ICJX_NOB1);
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if (ret < 0)
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{
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nxmutex_unlock(&priv->lock);
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@ -406,7 +434,7 @@ static int icjx_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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out_set &= ~ICJX_CTRL_WORD_2_NIOH;
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}
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ret = icjx_write(priv, regaddr, out_set);
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ret = icjx_write(priv, regaddr, out_set, ICJX_NOB1);
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nxmutex_unlock(&priv->lock);
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return ret;
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@ -517,7 +545,7 @@ static int icjx_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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outstate = (priv->outstate >> 8) & 0xff;
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}
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ret = icjx_write(priv, regaddr, outstate);
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ret = icjx_write(priv, regaddr, outstate, ICJX_NOB1);
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nxmutex_unlock(&priv->lock);
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return ret;
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@ -547,7 +575,7 @@ static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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{
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FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev;
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uint8_t regaddr;
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uint8_t data;
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uint16_t data;
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int ret;
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if (pin > 16)
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@ -578,7 +606,7 @@ static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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regaddr = pin < 8 ? ICJX_INPUT_A : ICJX_INPUT_B;
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ret = icjx_read(priv, regaddr, &data);
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ret = icjx_read(priv, regaddr, &data, ICJX_NOB1);
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nxmutex_unlock(&priv->lock);
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if (ret != OK)
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{
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@ -610,12 +638,58 @@ static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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#ifdef CONFIG_IOEXPANDER_MULTIPIN
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static int icjx_multiwritepin(FAR struct ioexpander_dev_s *dev,
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FAR const uint8_t *pins,
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FAR bool *values, int count)
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FAR const bool *values, int count)
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{
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gpiowarn("WARNING: iC-JX does not have implemented support for"
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"multiple pin write operation!\n");
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FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev;
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int ret;
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int pin;
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int value;
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return -ENOTSUP;
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if (count >= 16)
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{
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return -ENXIO;
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}
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DEBUGASSERT(priv != NULL && priv->config != NULL);
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/* Get exclusive access to the I/O Expander */
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ret = nxmutex_lock(&priv->lock);
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if (ret < 0)
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{
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return ret;
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}
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for (int i = 0; i < count; i++)
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{
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pin = pins[i];
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value = values[i];
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gpioinfo("Expander id=%02x, pin=%u\n", priv->config->id, pin);
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if ((priv->outpins & (1 << pin)) == 0)
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{
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gpioerr("ERROR: pin%u is an input\n", pin);
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nxmutex_unlock(&priv->lock);
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return -EINVAL;
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}
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/* Set/clear a bit in outstate. */
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if (value)
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{
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priv->outstate |= (1 << pin);
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}
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else
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{
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priv->outstate &= ~(1 << pin);
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}
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}
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ret = icjx_write(priv, ICJX_OUTPUT_A, priv->outstate, ICJX_NOB2);
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nxmutex_unlock(&priv->lock);
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return ret;
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}
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/****************************************************************************
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@ -640,10 +714,51 @@ static int icjx_multireadpin(FAR struct ioexpander_dev_s *dev,
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FAR const uint8_t *pins, FAR bool *values,
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int count)
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{
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gpiowarn("WARNING: iC-JX does not have implemented support for"
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"multiple pin read operation!\n");
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FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev;
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uint16_t data;
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int pin;
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int ret;
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return -ENOTSUP;
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if (count > 16)
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{
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return -ENXIO;
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}
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DEBUGASSERT(priv != NULL && priv->config != NULL && values != NULL);
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/* Get exclusive access to the I/O Expander */
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ret = nxmutex_lock(&priv->lock);
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if (ret < 0)
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{
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return ret;
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}
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for (int i = 0; i < count; i++)
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{
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pin = pins[i];
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gpioinfo("Expander id=%02x, pin=%u\n", priv->config->id, pin);
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if ((priv->outpins & (1 << pin)) != 0)
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{
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values[i] = (priv->outstate & (1 << pin)) != 0;
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}
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}
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ret = icjx_read(priv, ICJX_INPUT_A, &data, ICJX_NOB2);
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nxmutex_unlock(&priv->lock);
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if (ret != OK)
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{
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return ret;
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}
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for (int i = 0; i < count; i++)
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{
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values[i] = (data >> (pins[i] & 0xf)) & 1;
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}
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return OK;
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}
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#endif /* CONFIG_IOEXPANDER_MULTIPIN */
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@ -706,14 +821,14 @@ FAR struct ioexpander_dev_s *icjx_initialize(FAR struct spi_dev_s *spi,
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regval = (config->current_src << 4) | config->current_src;
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ret = icjx_write(priv, ICJX_CTRL_WORD_2_A, regval);
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ret = icjx_write(priv, ICJX_CTRL_WORD_2_A, regval, ICJX_NOB1);
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if (ret < 0)
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{
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gpioerr("ERROR: Could write to ICJX_CTRL_WORD_2_A: %d!\n", ret);
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goto err;
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}
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ret = icjx_write(priv, ICJX_CTRL_WORD_2_B, regval);
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ret = icjx_write(priv, ICJX_CTRL_WORD_2_B, regval, ICJX_NOB1);
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if (ret < 0)
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{
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gpioerr("ERROR: Could write to ICJX_CTRL_WORD_2_B: %d!\n", ret);
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@ -723,14 +838,14 @@ FAR struct ioexpander_dev_s *icjx_initialize(FAR struct spi_dev_s *spi,
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/* Bypass filters as those are not yet supported. */
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regval = ICJX_CTRL_WORD_1_BYP0 | ICJX_CTRL_WORD_1_BYP1;
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ret = icjx_write(priv, ICJX_CTRL_WORD_1_A, regval);
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ret = icjx_write(priv, ICJX_CTRL_WORD_1_A, regval, ICJX_NOB1);
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if (ret < 0)
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{
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gpioerr("ERROR: Could write to ICJX_CTRL_WORD_1_A: %d!\n", ret);
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goto err;
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}
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ret = icjx_write(priv, ICJX_CTRL_WORD_1_B, regval);
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ret = icjx_write(priv, ICJX_CTRL_WORD_1_B, regval, ICJX_NOB1);
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if (ret < 0)
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{
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gpioerr("ERROR: Could write to ICJX_CTRL_WORD_1_B: %d!\n", ret);
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