LaunchXL-TMS57004: Add VCLK and RTICLK dividers to board.h
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@ -108,6 +108,17 @@
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#define BOARD_PLL_R 2 /* PLLDIV = 1 */
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#define BOARD_PLL_FREQUENCY 80000000
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/* Clock Sources / Dividers
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*
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* GCLK and HCLK are both driven by PLL1.
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* VCLK is driven by HCLK (optionally by HCLK/2)
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* RTICLK source is VCLK/2 (optionally from VCLK)
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*/
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#define BOARD_VCLK_DIVIDER 1
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#define BOARD_VCLK2_DIVIDER 1
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#define BOARD_RTICLK_DIVIDER 2
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/* Resulting frequencies:
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*
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* GCLK and HCLK are both driven by PLL1.
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@ -117,8 +128,8 @@
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#define BOARD_GCLK_FREQUENCY BOARD_PLL_FREQUENCY
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#define BOARD_HCLK_FREQUENCY BOARD_PLL_FREQUENCY
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#define BOARD_VCLK_FREQUENCY BOARD_HCLK_FREQUENCY
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#define BOARD_RTICLK_FREQUENCY (BOARD_VCLK_FREQUENCY / 2)
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#define BOARD_VCLK_FREQUENCY (BOARD_HCLK_FREQUENCY / BOARD_VCLK_DIVIDER)
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#define BOARD_RTICLK_FREQUENCY (BOARD_VCLK_FREQUENCY / BOARD_RTICLK_DIVIDER)
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/* FLASH wait states */
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