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Add low UART init logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@745 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2008-03-23 14:50:18 +00:00
parent 0125c5989f
commit 7caf0ae3b6
3 changed files with 198 additions and 8 deletions
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2
arch/z80/src/ez80/chip.h
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@ -217,6 +217,8 @@
# define EZ80_UARTCHAR_7BITS 0x02 /* 10: 7 data bits */
# define EZ80_UARTCHAR_8BITS 0x03 /* 11: 8 data bits */
#define EZ80_UARTLCTL_MASK 0x3f
/* UART0/1 MCTL register bits *******************************************************/
/* Bit 7: Reserved */
#define EZ80_UARTMCTL_POLARITY 0x40 /* Bit 6: Invert polarity of RxD and TxD */

190
arch/z80/src/ez80/ez80_lowuart.c Normal file
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@ -0,0 +1,190 @@
/****************************************************************************
* arch/z80/src/ez80/ez80_loweruart.c
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <string.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include "chip/chip.h"
#include "common/up_internal.h"
#ifdef CONFIG_USE_LOWUARTINIT
/****************************************************************************
* Private Definitions
****************************************************************************/
/* The system clock frequency is defined in the linkcmd file */
extern unsigned long SYS_CLK_FREQ;
#define _DEFCLK ((unsigned long)&SYS_CLK_FREQ)
#ifdef CONFIG_UART1_SERIAL_CONSOLE
# define ez80_getreg(offs) getreg8((EZ80_UART1_BASE+(offs)))
# define ez80_putreg(val,offs) putreg8((val), (EZ80_UART1_BASE+(offs)))
# define CONFIG_UART_BAUD CONFIG_UART0_BAUD
# if CONFIG_UART0_BITS == 7
# define CONFIG_UART_BITS EZ80_UARTCHAR_7BITS
# else
# define CONFIG_UART_BITS EZ80_UARTCHAR_8BITS
# endif
# if CONFIG_UART0_2STOP != 0
# define CONFIG_UART_2STOP EZ80_UARTLCTl_2STOP
# else
# define CONFIG_UART_2STOP 0
# endif
# if CONFIG_UART0_PARITY == 1 /* Odd parity */
# define CONFIG_UART_PARITY EZ80_UARTLCTL_PEN
# elif CONFIG_UART0_PARITY == 2 /* Even parity */
# define CONFIG_UART_PARITY (EZ80_UARTLCTL_PEN|EZ80_UARTLCTL_EPS)
# else
# define CONFIG_UART_PARITY 0
# endif
#else
# define ez80_getreg(offs) getreg8((EZ80_UART0_BASE+(offs)))
# define ez80_putreg(val,offs) putreg8((val), (EZ80_UART0_BASE+(offs)))
# define CONFIG_UART_BAUD CONFIG_UART1_BAUD
# if CONFIG_UART1_BITS == 7
# define CONFIG_UART_BITS EZ80_UARTCHAR_7BITS
# else
# define CONFIG_UART_BITS EZ80_UARTCHAR_8BITS
# endif
# if CONFIG_UART1_2STOP != 0
# define CONFIG_UART_2STOP EZ80_UARTLCTl_2STOP
# else
# define CONFIG_UART_2STOP 0
# endif
# if CONFIG_UART1_PARITY == 1 /* Odd parity */
# define CONFIG_UART_PARITY EZ80_UARTLCTL_PEN
# elif CONFIG_UART1_PARITY == 2 /* Even parity */
# define CONFIG_UART_PARITY (EZ80_UARTLCTL_PEN|EZ80_UARTLCTL_EPS)
# else
# define CONFIG_UART_PARITY 0
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#ifndef CONFIG_SUPPRESS_UART_CONFIG
static void ez80_setbaud(void)
{
uint24 brg_divisor;
ubyte lctl;
/* The resulting BAUD and depends on the system clock frequency and the
* BRG divisor as follows:
*
* BAUD = SYSTEM_CLOCK_FREQUENCY / (16 * BRG_Divisor)
*
* Or
*
* BRG_Divisor = SYSTEM_CLOCK_FREQUENCY / 16 / BAUD
*/
brg_divisor = ( _DEFCLK + (CONFIG_UART_BAUD << 3)) / (CONFIG_UART_BAUD << 4);
/* Set the DLAB bit to enable access to the BRG registers */
lctl = ez80_getreg(EZ80_UART_LCTL);
lctl |= EZ80_UARTLCTL_DLAB;
ez80_putreg(lctl, EZ80_UART_LCTL);
ez80_putreg((ubyte)(brg_divisor & 0xff), EZ80_UART_BRGL);
ez80_putreg((ubyte)(brg_divisor >> 8), EZ80_UART_BRGH);
lctl &= ~EZ80_UARTLCTL_DLAB;
ez80_putreg(lctl, EZ80_UART_LCTL);
}
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_lowuartinit
****************************************************************************/
void up_lowuartinit(void)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
ubyte reg;
/* Disable interrupts from the UART */
reg = ez80_getreg(EZ80_UART_IER);
reg &= ~EZ80_UARTEIR_INTMASK;
ez80_putreg(reg, EZ80_UART_IER);
/* Set the baud rate */
ez80_setbaud();
ez80_putreg(0, EZ80_UART_MCTL);
/* Set the character properties */
reg = ez80_getreg(EZ80_UART_LCTL);
reg &= ~EZ80_UARTLCTL_MASK;
reg |= (CONFIG_UART_BITS | CONFIG_UART_2STOP | CONFIG_UART_PARITY);
ez80_putreg(reg, EZ80_UART_LCTL);
/* Enable and flush the receive FIFO */
reg = EZ80_UARTFCTL_FIFOEN;
ez80_putreg(reg, EZ80_UART_FCTL);
reg |= (EZ80_UARTFCTL_CLRTxF|EZ80_UARTFCTL_CLRRxF);
ez80_putreg(reg, EZ80_UART_FCTL);
/* Set the receive trigger level to 1 */
reg |= EZ80_UARTTRIG_1;
ez80_putreg(reg, EZ80_UART_FCTL);
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
}
#endif /* CONFIG_USE_LOWUARTINIT */

14
arch/z80/src/ez80/ez80_serial.c
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@ -61,8 +61,6 @@
* Definitions
****************************************************************************/
#define BASE_BAUD 115200
/* The system clock frequency is defined in the linkcmd file */
extern unsigned long SYS_CLK_FREQ;
@ -253,7 +251,7 @@ static inline void ez80_serialout(struct ez80_dev_s *priv, ubyte offset, ubyte v
static inline void ez80_disableuartint(struct ez80_dev_s *priv)
{
ubyte ier = ez80_serialin(EZ80_UART_IER);
ubyte ier = ez80_serialin(priv, EZ80_UART_IER);
ier &= ~EZ80_UARTEIR_INTMASK;
ez80_serialout(priv, EZ80_UART_IER, ier);
}
@ -264,7 +262,7 @@ static inline void ez80_disableuartint(struct ez80_dev_s *priv)
static inline void ez80_restoreuartint(struct ez80_dev_s *priv, ubyte bits)
{
ubyte ier = ez80_serialin(EZ80_UART_IER);
ubyte ier = ez80_serialin(priv, EZ80_UART_IER);
ier |= bits & (EZ80_UARTEIR_TIE|EZ80_UARTEIR_RIE);
ez80_serialout(priv, EZ80_UART_IER, ier);
}
@ -305,7 +303,7 @@ static inline void ez80_setbaud(struct ez80_dev_s *priv, uint24 baud)
* BRG_Divisor = SYSTEM_CLOCK_FREQUENCY / 16 / BAUD
*/
brg_divisor = ( _DEFCLK + (bard << 3)) / ((baud << 4);
brg_divisor = ( _DEFCLK + (baud << 3)) / (baud << 4);
/* Set the DLAB bit to enable access to the BRG registers */
@ -347,7 +345,7 @@ static int ez80_setup(struct uart_dev_s *dev)
if (priv->stopbits2)
{
cval |= EZ80_UARTLCTl_2STOP;
cval |= EZ80_UARTLCTL_2STOP;
}
if (priv->parity == 1) /* Odd parity */
@ -363,11 +361,11 @@ static int ez80_setup(struct uart_dev_s *dev)
ez80_disableuartint(priv, NULL);
ez80_setbaud(priv, priv->baud);
ez80_serial_out(priv, EZ80_UART_MCTL, 0)
ez80_serialout(priv, EZ80_UART_MCTL, 0);
/* Set the character properties */
reg = (ez80_serialin(priv, EZ80_UART_LCTL) & 0x3f) | cval;
reg = (ez80_serialin(priv, EZ80_UART_LCTL) & ~EZ80_UARTLCTL_MASK) | cval;
ez80_serialout(priv, EZ80_UART_LCTL, reg);
/* Enable and flush the receive FIFO */