Drop STM32 F2/4 SDIO clock from 24 to 16 MHz. Seems to fix SD accesses on STM3240G-EVAL

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5020 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-08-10 22:42:46 +00:00
parent 8e48ba3224
commit 7cbb44ffb8
5 changed files with 10 additions and 4 deletions

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@ -3147,3 +3147,7 @@
* arch/arm/src/stm32/stm32f2xx_dma.c, stm32f4xx_dma.c, stm32_serial.c, and
stm32_spic.c: DMA priority was getting zeroed by STM32 F2/F4 DMA drivers
so that all DMAs ran at the lowest priority.
* configs/stm3240g-eval/include/board.h and configs/stm3220: Drop SD card
frequency from 24 to 16 MHz. Apparently 24 MHz is too fast for the board.
This (plus the change to the STM32 DMA (above) fixes SDIO DMA on the
STM3240G-EVAL (and probably STM3220G-EVAL -- untested).

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@ -783,6 +783,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
* mode to determine when the buffer is half-full, or in double-buffered
* mode to determine when one of the two buffers is full.
*/
scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE;
}

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@ -783,6 +783,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
* mode to determine when the buffer is half-full, or in double-buffered
* mode to determine when one of the two buffers is full.
*/
scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE;
}

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@ -185,12 +185,12 @@
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(0+2)= 24 MHz
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)= 16 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif

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@ -182,12 +182,12 @@
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HSDIOCLK=48MHz, SDIO_CK=SDIOCLK/(0+2)=24 MHz
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif