Add reset register control definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2476 42af7a65-404d-4744-a932-0658087f49c3
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/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
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#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
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#define SAM3U_MATRIX_BASE 0x400e0000 /* 0x400e0200-0x400e03ff: MATRIX */
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#define SAM3U_PMC_BASE 0x400e0000 /* 0x400e0400-0x400e05ff: Power Management Controller */
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#define SAM3U_UART_BASE 0x400e0000 /* 0x400e0600-0x400e073f: UART */
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#define SAM3U_CHIPID_BASE 0x400e0000 /* 0x400e0740-0x400e07ff: CHIP ID */
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#define SAM3U_EFC0_BASE 0x400e0000 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
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#define SAM3U_EFC1_BASE 0x400e0000 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
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#define SAM3U_PIOA_BASE 0x400e0000 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
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#define SAM3U_PIOB_BASE 0x400e0000 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
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#define SAM3U_PIOC_BASE 0x400e0000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
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#define SAM3U_RSTC_BASE 0x400e0000 /* 0x400e1200-0x400e120f: Reset Controller */
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#define SAM3U_SUPC_BASE 0x400e0000 /* 0x400e1210-0x400e122f: Supply Controller */
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#define SAM3U_RTT_BASE 0x400e0000 /* 0x400e1230-0x400e124f: Real Time Timer */
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#define SAM3U_WDT_BASE 0x400e0000 /* 0x400e1250-0x400e125f: Watchdog Timer */
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#define SAM3U_RTC_BASE 0x400e0000 /* 0x400e1260-0x400e128f: Real Time Clock */
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#define SAM3U_GPBR_BASE 0x400e0000 /* 0x400e1290-0x400e13ff: GPBR */
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#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
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#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
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#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */
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#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
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#define SAM3U_EFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
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#define SAM3U_EFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
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#define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
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#define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
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#define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
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#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */
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#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */
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#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */
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#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
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#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
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#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
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/* 0x490e1400-0x4007ffff: Reserved */
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/************************************************************************************************
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102
arch/arm/src/sam3u/sam3u_rstc.h
Executable file
102
arch/arm/src/sam3u/sam3u_rstc.h
Executable file
@ -0,0 +1,102 @@
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/****************************************************************************************
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* arch/arm/src/sam3u/sam3u_rstc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam3u_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* RSTC register offsets ****************************************************************/
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#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */
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#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */
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#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */
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/* RSTC register adresses ***************************************************************/
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#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET)
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#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET)
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#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET)
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/* RSTC register bit definitions ********************************************************/
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#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */
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#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */
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#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
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#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
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#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
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#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
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#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT)
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# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */
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# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */
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# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */
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# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */
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# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */
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#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */
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#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */
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#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */
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#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */
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#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */
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#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
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#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */
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