From 7cdef222889fa9e0d325f2b30b270da9e9211791 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sun, 24 May 2015 07:50:57 -0600
Subject: [PATCH] Update ChangeLog

---
 ChangeLog                               |  3 +++
 configs/saml21-xplained/include/board.h | 24 ++++++++++++------------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/ChangeLog b/ChangeLog
index c5c24ebb50..15c6f8411d 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -10425,3 +10425,6 @@
 	* LPCXpresso-LPC1115:  Add a minimal NSH configuration that has the
 	  file system disabled.  Update README with OpenOCD instructions.
 	  From Alan Carvalho de Assis (2015-05-23).
+	* Fix numerous typos in configuration variable names.  Tracked down
+	  by Alan Carvalho de Assis (2015-05-23).
+
diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h
index 3b2934be3b..0d5a030a29 100644
--- a/configs/saml21-xplained/include/board.h
+++ b/configs/saml21-xplained/include/board.h
@@ -60,16 +60,16 @@
  * We will use its default, POR frequency of 4MHz to avoid an additional clock
  * switch.
  *
- * OSC16M             Output = 4MHz
- *  `- GCLK1          Input  = 4MHz Prescaler     = 1  output         = 4MHz
- *      `- DFLL       Input  = 4MHz  Multiplier   = 12 output         = 48MHz
- *          `- GCLK0  Input  = 48MHz Prescaler    = 1  output         = 48MHz
- *              `- PM Input  = 48Mhz CPU divider  = 1  CPU frequency  = 48MHz
- *                                   APBA divider = 1  APBA frequency = 48MHz
- *                                   APBB divider = 1  APBB frequency = 48MHz
- *                                   APBC divider = 1  APBC frequency = 48MHz
- *                                   APBD divider = 1  APBD frequency = 48MHz
- *                                   APBE divider = 1  APBE frequency = 48MHz
+ * OSC16M               Output = 4MHz
+ *  `- GCLK1            Input  = 4MHz Prescaler     = 1  output         = 4MHz
+ *      `- DFLL         Input  = 4MHz  Multiplier   = 12 output         = 48MHz
+ *          `- GCLK0    Input  = 48MHz Prescaler    = 1  output         = 48MHz
+ *              `- MCLK Input  = 48Mhz CPU divider  = 1  CPU frequency  = 48MHz
+ *                                     APBA divider = 1  APBA frequency = 48MHz
+ *                                     APBB divider = 1  APBB frequency = 48MHz
+ *                                     APBC divider = 1  APBC frequency = 48MHz
+ *                                     APBD divider = 1  APBD frequency = 48MHz
+ *                                     APBE divider = 1  APBE frequency = 48MHz
  *
  * The SAML21 Xplained Pro has one on-board crystal:
  *
@@ -412,8 +412,8 @@
  *                1             48 MHz
  */
 
-#if 0 /* REVISIT -- Sample code is running with zero wait states */
-#  define BOARD_FLASH_WAITSTATES     0
+#if 0
+#  define BOARD_FLASH_WAITSTATES     3
 #else
 #  define BOARD_FLASH_WAITSTATES     1
 #endif