Add TWI header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2487 42af7a65-404d-4744-a932-0658087f49c3
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# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
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# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
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# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */
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# define SAM3U_TWI_BASE(n) (0x40084000+((n)<<14))
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# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */
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# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */
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# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */
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192
arch/arm/src/sam3u/sam3u_twi.h
Executable file
192
arch/arm/src/sam3u/sam3u_twi.h
Executable file
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/****************************************************************************************
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* arch/arm/src/sam3u/sam3u_twi.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam3u_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* TWI register offsets *****************************************************************/
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#define SAM3U_TWI_CR_OFFSET 0x00 /* Control Register */
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#define SAM3U_TWI_MMR_OFFSET 0x04 /* Master Mode Register */
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#define SAM3U_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */
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#define SAM3U_TWI_IADR_OFFSET 0x0c /* Internal Address Register */
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#define SAM3U_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */
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#define SAM3U_TWI_SR_OFFSET 0x20 /* Status Register */
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#define SAM3U_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */
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#define SAM3U_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */
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#define SAM3U_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */
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#define SAM3U_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */
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#define SAM3U_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */
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/* 0x38-0xfc: Reserved */
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/* 0x100-0x124: Reserved for the PDC */
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/* TWI register adresses ****************************************************************/
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#define SAM3U_TWI_CR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_CR_OFFSET)
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#define SAM3U_TWI_MMR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_MMR_OFFSET)
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#define SAM3U_TWI_SMR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_SMR_OFFSET)
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#define SAM3U_TWI_IADR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_IADR_OFFSET)
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#define SAM3U_TWI_CWGR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_CWGR_OFFSET)
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#define SAM3U_TWI_SR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_SR_OFFSET)
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#define SAM3U_TWI_IER(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_IER_OFFSET)
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#define SAM3U_TWI_IDR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_IDR_OFFSET)
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#define SAM3U_TWI_IMR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_IMR_OFFSET)
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#define SAM3U_TWI_RHR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_RHR_OFFSET)
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#define SAM3U_TWI_THR(n) (SAM3U_TWI_BASE(n)+SAM3U_TWI_THR_OFFSET)
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#define SAM3U_TWI0_CR (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET)
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#define SAM3U_TWI0_MMR (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET)
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#define SAM3U_TWI0_SMR (SAM3U_TWI0_BASE+SAM3U_TWI_SMR_OFFSET)
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#define SAM3U_TWI0_IADR (SAM3U_TWI0_BASE+SAM3U_TWI_IADR_OFFSET)
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#define SAM3U_TWI0_CWGR (SAM3U_TWI0_BASE+SAM3U_TWI_CWGR_OFFSET)
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#define SAM3U_TWI0_SR (SAM3U_TWI0_BASE+SAM3U_TWI_SR_OFFSET)
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#define SAM3U_TWI0_IER (SAM3U_TWI0_BASE+SAM3U_TWI_IER_OFFSET)
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#define SAM3U_TWI0_IDR (SAM3U_TWI0_BASE+SAM3U_TWI_IDR_OFFSET)
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#define SAM3U_TWI0_IMR (SAM3U_TWI0_BASE+SAM3U_TWI_IMR_OFFSET)
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#define SAM3U_TWI0_RHR (SAM3U_TWI0_BASE+SAM3U_TWI_RHR_OFFSET)
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#define SAM3U_TWI0_THR (SAM3U_TWI0_BASE+SAM3U_TWI_THR_OFFSET)
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#define SAM3U_TWI1_CR (SAM3U_TWI1_BASE+SAM3U_TWI_CR_OFFSET)
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#define SAM3U_TWI1_MMR (SAM3U_TWI1_BASE+SAM3U_TWI_MMR_OFFSET)
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#define SAM3U_TWI1_SMR (SAM3U_TWI1_BASE+SAM3U_TWI_SMR_OFFSET)
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#define SAM3U_TWI1_IADR (SAM3U_TWI1_BASE+SAM3U_TWI_IADR_OFFSET)
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#define SAM3U_TWI1_CWGR (SAM3U_TWI1_BASE+SAM3U_TWI_CWGR_OFFSET)
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#define SAM3U_TWI1_SR (SAM3U_TWI1_BASE+SAM3U_TWI_SR_OFFSET)
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#define SAM3U_TWI1_IER (SAM3U_TWI1_BASE+SAM3U_TWI_IER_OFFSET)
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#define SAM3U_TWI1_IDR (SAM3U_TWI1_BASE+SAM3U_TWI_IDR_OFFSET)
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#define SAM3U_TWI1_IMR (SAM3U_TWI1_BASE+SAM3U_TWI_IMR_OFFSET)
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#define SAM3U_TWI1_RHR (SAM3U_TWI1_BASE+SAM3U_TWI_RHR_OFFSET)
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#define SAM3U_TWI1_THR (SAM3U_TWI1_BASE+SAM3U_TWI_THR_OFFSET)
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/* TWI register bit definitions *********************************************************/
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/* TWI Control Register */
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#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */
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#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */
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#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */
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#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */
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#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */
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#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */
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#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */
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#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
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/* TWI Master Mode Register */'
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#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */
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#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT)
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# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */
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# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */
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# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
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# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
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#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
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#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */
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#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT)
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/* TWI Slave Mode Register */
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#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */
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#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT)
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/* TWI Internal Address Register */
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#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */
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#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT)
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/* TWI Clock Waveform Generator Register */
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#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */
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#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
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#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */
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#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
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#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */
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#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT)
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/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable
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* Register, and TWI Interrupt Mask Register common bit fields.
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*/
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#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */
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#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */
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#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */
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#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */
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#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */
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#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */
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#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */
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#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */
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#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */
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#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */
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#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */
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#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */
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#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */
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#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */
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#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */
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/* TWI Receive Holding Register */
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#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */
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#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
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/* TWI Transmit Holding Register */
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#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */
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#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H */
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