arch/arm/src/stm32f7: USB High speed for STM32F7 series
This commit is contained in:
Ramtin Amin
Gregory Nutt
parent
2c2729521b
commit
7d2bd2371f
@ -258,9 +258,11 @@ void up_initialize(void)
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(void)telnet_initialize();
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#endif
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#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
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/* Initialize USB -- device and/or host */
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up_usbinitialize();
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#endif
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/* Initialize the L2 cache if present and selected */
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@ -95,6 +95,7 @@ config ARCH_CHIP_STM32F723RE
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config ARCH_CHIP_STM32F723VC
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bool "STM32F723VC"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_V
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---help---
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@ -103,6 +104,7 @@ config ARCH_CHIP_STM32F723VC
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config ARCH_CHIP_STM32F723VE
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bool "STM32F723VE"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_V
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---help---
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@ -111,6 +113,7 @@ config ARCH_CHIP_STM32F723VE
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config ARCH_CHIP_STM32F723ZC
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bool "STM32F723ZC"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_Z
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---help---
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@ -119,6 +122,7 @@ config ARCH_CHIP_STM32F723ZC
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config ARCH_CHIP_STM32F723ZE
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bool "STM32F723ZE"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_Z
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---help---
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@ -127,6 +131,7 @@ config ARCH_CHIP_STM32F723ZE
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config ARCH_CHIP_STM32F723IC
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bool "STM32F723IC"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_I
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---help---
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@ -135,6 +140,7 @@ config ARCH_CHIP_STM32F723IC
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config ARCH_CHIP_STM32F723IE
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bool "STM32F723IE"
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select STM32F7_STM32F723XX
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select STM32F7_HAVE_INTERNAL_ULPI
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_I
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---help---
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@ -666,6 +672,7 @@ config STM32F7_STM32F722XX
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select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V)
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select STM32F7_HAVE_CRYP
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select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R
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select STM32F7_HAVE_EXTERNAL_ULPI
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config STM32F7_STM32F723XX
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bool
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@ -724,6 +731,7 @@ config STM32F7_STM32F746XX
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select STM32F7_HAVE_DMA2D
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select STM32F7_HAVE_CAN2
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select STM32F7_HAVE_SPI4
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select STM32F7_HAVE_EXTERNAL_ULPI
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config STM32F7_STM32F756XX
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bool
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@ -1199,6 +1207,14 @@ config STM32F7_HAVE_DFSDM1
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bool
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default n
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config STM32F7_HAVE_INTERNAL_ULPI
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bool
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default n
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config STM32F7_HAVE_EXTERNAL_ULPI
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bool
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default n
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# These "hidden" settings are the OR of individual peripheral selections
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# indicating that the general capability is required.
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@ -1427,8 +1443,8 @@ config STM32F7_OTGFS
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default n
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select USBHOST_HAVE_ASYNCH if USBHOST
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config STM32F7_OTGHS
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bool "OTG HS"
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config STM32F7_OTGFSHS
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bool "OTG FS/HS"
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default n
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select USBHOST_HAVE_ASYNCH if USBHOST
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@ -1953,6 +1969,36 @@ endif
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endmenu # U[S]ART Configuration
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menu "STM32F7_OTG_HS Configuration"
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depends on STM32F7_OTGFSHS
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choice
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prompt "ULPI Selection"
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default STM32F7_NO_ULPI
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config STM32F7_NO_ULPI
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bool "No External ULPI"
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default y
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---help---
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Select to enable the presence of an external ULPI PHY
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config STM32F7_EXTERNAL_ULPI
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bool "External ULPI"
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depends on STM32F7_HAVE_EXTERNAL_ULPI
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default n
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---help---
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Select to enable the presence of an external ULPI PHY
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config STM32F7_INTERNAL_ULPI
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bool "Internal ULPI PHY"
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depends on STM32F7_HAVE_INTERNAL_ULPI
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default y
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---help---
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Select to enable the internal ULPI for USB HS
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endchoice #"ULPI Selection"
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endmenu # OTG_HS Config
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menu "QuadSPI Configuration"
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depends on STM32F7_QUADSPI
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@ -149,6 +149,11 @@
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#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
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#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
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/* USB PHY OFFSET */
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#define STM32_USBPHYC_PLL1_OFFSET 0x0000 /* USBPHYC PLL1 control register */
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#define STM32_USBPHYC_TUNE_OFFSET 0x000c /* USBPHYC tuning control register */
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#define STM32_USBPHYC_LDO_OFFSET 0x0018 /* USBPHYC LDO control and status register */
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/* Register Addresses *******************************************************************************/
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@ -231,6 +236,11 @@
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#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
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#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
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/* USB PHY Registers */
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#define STM32_USBPHYC_PLL1 (STM32_USBPHYC_BASE+STM32_USBPHYC_PLL1_OFFSET)
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#define STM32_USBPHYC_TUNE (STM32_USBPHYC_BASE+STM32_USBPHYC_TUNE_OFFSET)
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#define STM32_USBPHYC_LDO (STM32_USBPHYC_BASE+STM32_USBPHYC_LDO_OFFSET)
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/* Register Bitfield Definitions ********************************************************************/
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/* Core global control and status registers */
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@ -282,6 +292,7 @@
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#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
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#define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT)
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/* Bits 3-5: Reserved, must be kept at reset value */
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#define OTG_GUSBCFG_ULPISEL (1 << 4) /* Bit 4: Select which high speed interface is to be used STM32F7x3 only*/
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#define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */
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/* Bit 7: Reserved, must be kept at reset value */
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#define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */
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@ -289,10 +300,21 @@
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#define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
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#define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT)
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# define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT)
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/* Bits 14-28: Reserved, must be kept at reset value */
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/* Bit 14: Reserved, must be kept at reset value */
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#define OTG_GUSBCFG_PHYLPC (1 << 15) /* Bit 15: PHY Low-power clock select for USB OTG HS */
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/* Bit 16: Reserved, must be kept at reset value */
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#define OTG_GUSBCFG_ULPIFSLS (1 << 17) /* Bit 17: ULPI FS/LS select for USB OTG HS */
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#define OTG_GUSBCFG_ULPIAR (1 << 18) /* Bit 18: ULPI Auto-resume for USB OTG HS */
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#define OTG_GUSBCFG_ULPICSM (1 << 19) /* Bit 19: ULPI clock SuspendM for USB OTG HS */
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#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20) /* Bit 20: ULPI External VBUS Drive for USB OTG HS */
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#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21) /* Bit 21: ULPI external VBUS indicator for USB OTG HS */
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#define OTG_GUSBCFG_TSDPS (1 << 22) /* Bit 22: TermSel DLine pulsing selection for USB OTG HS */
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#define OTG_GUSBCFG_PCCI (1 << 23) /* Bit 23: Indicator complement for USB OTG HS */
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#define OTG_GUSBCFG_PTCI (1 << 24) /* Bit 24: Indicator pass through for USB OTG HS */
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#define OTG_GUSBCFG_ULPIIPD (1 << 25) /* Bit 24: ULPI interface protect disable for USB OTG HS */
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/* Bit 26-28: Reserved, must be kept at reset value */
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#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
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#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
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#define OTG_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */
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/* Bits 20-31: Reserved, must be kept at reset value */
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/* Reset register */
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@ -337,12 +359,15 @@
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#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
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#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
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#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
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#define OTG_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */
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#define OTG_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
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#define OTG_GINT_DATAFSUSP (1 << 22) /* Bit 22: Data fetch suspended for USB OTG HS */
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#define OTG_GINT_RES23 (1 << 23) /* Bit 23: Reserved, must be kept at reset value */
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#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
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#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
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#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
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#define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
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#define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
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#define OTG_GINT_RES27 (1 << 27) /* Bit 27: Reserved, must be kept at reset value */
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#define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
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#define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
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#define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
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@ -437,6 +462,7 @@
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#define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */
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/* Bit 17 Reserved, must be kept at reset value */
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#define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
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#define OTG_GCCFG_PHYHSEN (1 << 23) /* Bit 21: NOT In datasheet but in STMCube.. */
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/* Bits 22-31: Reserved, must be kept at reset value */
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/* Core ID register (32-bit product ID) */
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@ -593,6 +619,8 @@
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#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
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#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT)
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# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High Speed */
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# define OTG_DCFG_DSPD_FS_USING_HS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using High Speed*/
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# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */
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#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
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/* Bit 3: Reserved, must be kept at reset value */
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@ -650,12 +678,17 @@
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#define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
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#define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
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/* Bit 2: Reserved, must be kept at reset value */
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#define OTG_DIEPMSK_AHBERRM (1 << 2) /* Bit 2: AHB error mask for USB OTG HS */
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#define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
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#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */
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#define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */
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#define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */
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/* Bits 7-31: Reserved, must be kept at reset value */
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/* Bit 7: Reserved, must be kept at reset value */
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#define OTG_DIEPMSK_TXFURM (1 << 8) /* Bit 8: FIFO underrun mask */
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/* Bits 9-12: Reserved, must be kept at reset value */
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#define OTG_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */
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/* Bits 14-31: Reserved, must be kept at reset value */
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/* Device OUT endpoint common interrupt mask register */
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#define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
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@ -870,4 +903,53 @@
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#define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
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/* Bits 5-31: Reserved, must be kept at reset value */
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/* USB PHYC Registers */
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/* USBPHYC PLL1 control register */
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#define USBPHYC_PLL1_EN (1 << 0) /* Bit 0: Enable the PLL1 inside PHY */
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#define USBPHYC_PLL1_SEL_SHIFT (1) /* Bits 1-3: Controls the PHY PLL1 input clock frequency selection */
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#define USBPHYC_PLL1_SEL_MASK (7 << USBPHYC_PLL1SEL_SHIFT)
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# define USBPHYC_PLL1_SEL_12MHz (0 << USBPHYC_PLL1_SEL_SHIFT) /* 12 MHz */
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# define USBPHYC_PLL1_SEL_12_5MHz (1 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */
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# define USBPHYC_PLL1_SEL_12_5bMHz (2 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */
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# define USBPHYC_PLL1_SEL_16MHz (3 << USBPHYC_PLL1_SEL_SHIFT) /* 16 MHz */
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# define USBPHYC_PLL1_SEL_24MHz (4 << USBPHYC_PLL1_SEL_SHIFT) /* 24 MHz */
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# define USBPHYC_PLL1_SEL_25MHz (5 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */
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# define USBPHYC_PLL1_SEL_25bMHz (6 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */
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/* USBPHYC tuning control register */
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#define USBPHYC_TUNE_INCURREN (1 << 0) /* Bit 0: Controls the current boosting function */
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#define USBPHYC_TUNE_INCURRINT (1 << 1) /* Bit 1: Controls PHY current boosting */
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#define USBPHYC_TUNE_LFSCAPEN (1 << 2) /* Bit 2: Enables the Low Full Speed feedback capacitor */
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#define USBPHYC_TUNE_HSDRVSLEW (1 << 3) /* Bit 3: Controls the HS driver slew rate */
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#define USBPHYC_TUNE_HSDRVDCLEV (1 << 4) /* Bit 4: Decreases the HS driver DC level */
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#define USBPHYC_TUNE_HSDRVDCCUR (1 << 5) /* Bit 5: Increases the HS Driver DC level. Not applicable
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* during the HS Test J and Test K data transfer */
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#define USBPHYC_TUNE_HSDRVCURINCR (1 << 6) /* Bit 6: Enable the HS driver current increase feature */
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#define USBPHYC_TUNE_FSDRVRFADJ (1 << 7) /* Bit 7: Tuning pin to adjust the full speed rise/fall time */
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#define USBPHYC_TUNE_HSDRVRFRED (1 << 8) /* Bit 8: High Speed rise-fall reduction enable */
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#define USBPHYC_TUNE_HSDRVCHKITRM_SHIFT (9) /* Bits 9-12 : HS Driver current trimming pins for choke compensation */
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#define USBPHYC_TUNE_HSDRVCHKITRM_MASK (0xF << USBPHYC_TUNE_HSDRVCHKITRM_SHIFT)
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#define USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT (13) /* Bits 13-14 : Controls the PHY bus HS driver impedance tuning for choke */
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#define USBPHYC_TUNE_HSDRVCHKZTRM_MASK (3 << USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT)
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#define USBPHYC_TUNE_SQLCHCTL_SHIFT (15) /* Bits 15-16 : Adjust the squelch DC threshold value */
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#define USBPHYC_TUNE_SQLCHCTL_MASK (3 << USBPHYC_TUNE_SQLCHCTL_SHIFT)
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#define USBPHYC_TUNE_HDRXGNEQEN (1 << 17) /* Bit 17: Enables the HS Rx Gain Equalizer */
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#define USBPHYC_TUNE_STAGSEL (1 << 18) /* Bit 18: HS Tx staggering enable */
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#define USBPHYC_TUNE_HSFALLPREEM (1 << 19) /* Bit 19: HS Fall time control of single ended signals during pre-emphasis */
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#define USBPHYC_TUNE_HSRXOFF_SHIFT (20) /* Bits 20-21 : HS Receiver Offset adjustment */
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#define USBPHYC_TUNE_HSRXOFF_MASK (3 << USBPHYC_TUNE_HSRXOFF_SHIFT)
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#define USBPHYC_TUNE_SHTCCTCTLPROT (1 << 22) /* Bit 22: Enables the short circuit protection circuitry in LS/FS driver */
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#define USBPHYC_TUNE_SQLBYP (1 << 23) /* Bit 23: This pin is used to bypass the squelch inter-locking circuitry */
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/* USBPHYC LDO control and status register */
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#define USBPHYC_LDO_USED (1 << 0) /* Bit 0: Indicates the presence of the LDO in the chip. */
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#define USBPHYC_LDO_STATUS (1 << 1) /* Bit 1: Monitors the status of the PHY's LDO. */
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/* It looks like they made a mistake, is it ENABLE or DISABLE? */
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#define USBPHYC_LDO_ENABLE (1 << 2) /* Bit 2: Controls disable of the High Speed PHY's LDO. */
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */
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@ -900,8 +900,11 @@
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#define GPIO_UART4_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
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#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_UART4_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
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#define GPIO_UART4_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
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#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_UART4_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
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#define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9)
|
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#define GPIO_UART5_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8)
|
||||
|
||||
@ -732,20 +732,20 @@
|
||||
|
||||
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11)
|
||||
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0)
|
||||
|
||||
/* QuadSPI */
|
||||
|
||||
|
||||
@ -47,13 +47,18 @@
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_otg.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)
|
||||
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#ifndef CONFIG_OTG_PRI
|
||||
# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_OTGFS)
|
||||
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
|
||||
# define STM32_OTG_BASE STM32_USBOTGFS_BASE
|
||||
@ -62,17 +67,19 @@
|
||||
# define GPIO_OTG_DP GPIO_OTGFS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGFS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGFS_SOF
|
||||
# define GPIO_OTG_VBUS GPIO_OTGFS_VBUS
|
||||
# define STM32_OTG_FIFO_SIZE 1280
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_OTGHS)
|
||||
#if defined(CONFIG_STM32F7_OTGFSHS)
|
||||
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
|
||||
# define STM32_OTG_BASE STM32_USBOTGHS_BASE
|
||||
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
|
||||
# define GPIO_OTG_DM GPIO_OTGHS_DM
|
||||
# define GPIO_OTG_DP GPIO_OTGHS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGHS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGHS_SOF
|
||||
# define GPIO_OTG_DM GPIO_OTGHSFS_DM
|
||||
# define GPIO_OTG_DP GPIO_OTGHSFS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGHSFS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGHSFS_SOF
|
||||
# define GPIO_OTG_VBUS GPIO_OTGHSFS_VBUS
|
||||
# define STM32_OTG_FIFO_SIZE 4096
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -43,7 +43,7 @@
|
||||
* CONFIG_USBHOST - Enable general USB host support
|
||||
* CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
|
||||
* or
|
||||
* CONFIG_STM32F7_OTGHS - Enable the STM32 USB OTG HS block
|
||||
* CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block
|
||||
* CONFIG_STM32F7_SYSCFG - Needed
|
||||
*
|
||||
* Options:
|
||||
@ -68,7 +68,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)) && \
|
||||
#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \
|
||||
defined(CONFIG_USBHOST)
|
||||
|
||||
/************************************************************************************
|
||||
@ -120,5 +120,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGHS) && CONFIG_USBHOST */
|
||||
#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */
|
||||
|
||||
@ -227,8 +227,8 @@ static inline void rcc_enableahb1(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGHS
|
||||
#ifdef BOARD_ENABLE_USBOTG_HSULPI
|
||||
#ifdef CONFIG_STM32F7_OTGFSHS
|
||||
#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
|
||||
/* Enable clocking for USB OTG HS and external PHY */
|
||||
|
||||
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
|
||||
@ -237,7 +237,7 @@ static inline void rcc_enableahb1(void)
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
#endif
|
||||
#endif /* CONFIG_STM32F7_OTGHS */
|
||||
#endif /* CONFIG_STM32F7_OTGFSHS */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -657,6 +657,13 @@ static inline void rcc_enableapb2(void)
|
||||
regval |= RCC_APB2ENR_LTDCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGFSHS
|
||||
#ifdef CONFIG_STM32F7_INTERNAL_ULPI
|
||||
regval |= RCC_APB2ENR_OTGPHYCEN;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
@ -833,8 +840,8 @@ static void stm32_stdclockconfig(void)
|
||||
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
|
||||
|
||||
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
|
||||
/* The Flash memory interface accelerates code execution with a system of
|
||||
* instruction prefetch and cache lines on ITCM interface (ART
|
||||
/* The Flash memory interface accelerates code execution with a system
|
||||
* of instruction prefetch and cache lines on ITCM interface (ART
|
||||
* Accelerator™).
|
||||
*/
|
||||
|
||||
@ -899,7 +906,6 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR1);
|
||||
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
|
||||
@ -230,17 +230,18 @@ static inline void rcc_enableahb1(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGHS
|
||||
#ifdef BOARD_ENABLE_USBOTG_HSULPI
|
||||
#ifdef CONFIG_STM32F7_OTGFSHS
|
||||
#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
|
||||
/* Enable clocking for USB OTG HS and external PHY */
|
||||
|
||||
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
|
||||
#else
|
||||
|
||||
/* Enable only clocking for USB OTG HS */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
#endif
|
||||
#endif /* CONFIG_STM32F7_OTGHS */
|
||||
#endif /* CONFIG_STM32F7_OTGFSHS */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -836,8 +837,8 @@ static void stm32_stdclockconfig(void)
|
||||
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
|
||||
|
||||
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
|
||||
/* The Flash memory interface accelerates code execution with a system of
|
||||
* instruction prefetch and cache lines on ITCM interface (ART
|
||||
/* The Flash memory interface accelerates code execution with a system
|
||||
* of instruction prefetch and cache lines on ITCM interface (ART
|
||||
* Accelerator™).
|
||||
*/
|
||||
|
||||
@ -892,7 +893,6 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR1);
|
||||
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
|
||||
@ -236,7 +236,7 @@ static inline void rcc_enableahb1(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGHS
|
||||
#ifdef CONFIG_STM32F7_OTGFSHS
|
||||
#ifdef BOARD_ENABLE_USBOTG_HSULPI
|
||||
/* Enable clocking for USB OTG HS and external PHY */
|
||||
|
||||
@ -246,7 +246,7 @@ static inline void rcc_enableahb1(void)
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
#endif
|
||||
#endif /* CONFIG_STM32F7_OTGHS */
|
||||
#endif /* CONFIG_STM32F7_OTGFSHS */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -503,7 +503,6 @@ static inline void rcc_enableapb1(void)
|
||||
regval |= (RCC_APB1ENR_CAN3EN);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32F7_CEC
|
||||
/* CEC clock enable. */
|
||||
|
||||
@ -855,8 +854,8 @@ static void stm32_stdclockconfig(void)
|
||||
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
|
||||
|
||||
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
|
||||
/* The Flash memory interface accelerates code execution with a system of
|
||||
* instruction prefetch and cache lines on ITCM interface (ART
|
||||
/* The Flash memory interface accelerates code execution with a system
|
||||
* of instruction prefetch and cache lines on ITCM interface (ART
|
||||
* Accelerator™).
|
||||
*/
|
||||
|
||||
|
||||
@ -128,6 +128,52 @@ config USBDEV_TRACE_INITIALIDSET
|
||||
|
||||
endif # USBDEV_TRACE
|
||||
|
||||
menuconfig USBDEV_CUSTOM_TXFIFO_SIZE
|
||||
bool "Custom TX Fifo size"
|
||||
default n
|
||||
---help---
|
||||
Enables custom TX Fifo size
|
||||
|
||||
if USBDEV_CUSTOM_TXFIFO_SIZE
|
||||
|
||||
config USBDEV_EP0_TXFIFO_SIZE
|
||||
int "USBDEV_EP0_TXFIFO_SIZE"
|
||||
default 64
|
||||
|
||||
config USBDEV_EP1_TXFIFO_SIZE
|
||||
int "USBDEV_EP1_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP2_TXFIFO_SIZE
|
||||
int "USBDEV_EP2_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP3_TXFIFO_SIZE
|
||||
int "USBDEV_EP3_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP4_TXFIFO_SIZE
|
||||
int "USBDEV_EP4_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP5_TXFIFO_SIZE
|
||||
int "USBDEV_EP5_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP6_TXFIFO_SIZE
|
||||
int "USBDEV_EP6_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP7_TXFIFO_SIZE
|
||||
int "USBDEV_EP7_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
config USBDEV_EP8_TXFIFO_SIZE
|
||||
int "USBDEV_EP8_TXFIFO_SIZE"
|
||||
default 0
|
||||
|
||||
endif # USBDEV_CUSTOM_TXFIFO_SIZE
|
||||
|
||||
comment "USB Device Class Driver Options"
|
||||
|
||||
menuconfig USBDEV_COMPOSITE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user