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arch/arm/src/stm32f7: USB High speed for STM32F7 series

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This commit is contained in:
Ramtin Amin 2019-04-07 19:05:06 -06:00 committed by Gregory Nutt
parent 2c2729521b
commit 7d2bd2371f
12 changed files with 1652 additions and 1393 deletions
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2
arch/arm/src/common/up_initialize.c
View File

@ -258,9 +258,11 @@ void up_initialize(void)
(void)telnet_initialize();
#endif
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
/* Initialize USB -- device and/or host */
up_usbinitialize();
#endif
/* Initialize the L2 cache if present and selected */

52
arch/arm/src/stm32f7/Kconfig
View File

@ -95,6 +95,7 @@ config ARCH_CHIP_STM32F723RE
config ARCH_CHIP_STM32F723VC
bool "STM32F723VC"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_C
select STM32F7_IO_CONFIG_V
---help---
@ -103,6 +104,7 @@ config ARCH_CHIP_STM32F723VC
config ARCH_CHIP_STM32F723VE
bool "STM32F723VE"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_E
select STM32F7_IO_CONFIG_V
---help---
@ -111,6 +113,7 @@ config ARCH_CHIP_STM32F723VE
config ARCH_CHIP_STM32F723ZC
bool "STM32F723ZC"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_C
select STM32F7_IO_CONFIG_Z
---help---
@ -119,6 +122,7 @@ config ARCH_CHIP_STM32F723ZC
config ARCH_CHIP_STM32F723ZE
bool "STM32F723ZE"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_E
select STM32F7_IO_CONFIG_Z
---help---
@ -127,6 +131,7 @@ config ARCH_CHIP_STM32F723ZE
config ARCH_CHIP_STM32F723IC
bool "STM32F723IC"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_C
select STM32F7_IO_CONFIG_I
---help---
@ -135,6 +140,7 @@ config ARCH_CHIP_STM32F723IC
config ARCH_CHIP_STM32F723IE
bool "STM32F723IE"
select STM32F7_STM32F723XX
select STM32F7_HAVE_INTERNAL_ULPI
select STM32F7_FLASH_CONFIG_E
select STM32F7_IO_CONFIG_I
---help---
@ -666,6 +672,7 @@ config STM32F7_STM32F722XX
select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V)
select STM32F7_HAVE_CRYP
select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R
select STM32F7_HAVE_EXTERNAL_ULPI
config STM32F7_STM32F723XX
bool
@ -724,6 +731,7 @@ config STM32F7_STM32F746XX
select STM32F7_HAVE_DMA2D
select STM32F7_HAVE_CAN2
select STM32F7_HAVE_SPI4
select STM32F7_HAVE_EXTERNAL_ULPI
config STM32F7_STM32F756XX
bool
@ -1199,6 +1207,14 @@ config STM32F7_HAVE_DFSDM1
bool
default n
config STM32F7_HAVE_INTERNAL_ULPI
bool
default n
config STM32F7_HAVE_EXTERNAL_ULPI
bool
default n
# These "hidden" settings are the OR of individual peripheral selections
# indicating that the general capability is required.
@ -1427,8 +1443,8 @@ config STM32F7_OTGFS
default n
select USBHOST_HAVE_ASYNCH if USBHOST
config STM32F7_OTGHS
bool "OTG HS"
config STM32F7_OTGFSHS
bool "OTG FS/HS"
default n
select USBHOST_HAVE_ASYNCH if USBHOST
@ -1953,6 +1969,36 @@ endif
endmenu # U[S]ART Configuration
menu "STM32F7_OTG_HS Configuration"
depends on STM32F7_OTGFSHS
choice
prompt "ULPI Selection"
default STM32F7_NO_ULPI
config STM32F7_NO_ULPI
bool "No External ULPI"
default y
---help---
Select to enable the presence of an external ULPI PHY
config STM32F7_EXTERNAL_ULPI
bool "External ULPI"
depends on STM32F7_HAVE_EXTERNAL_ULPI
default n
---help---
Select to enable the presence of an external ULPI PHY
config STM32F7_INTERNAL_ULPI
bool "Internal ULPI PHY"
depends on STM32F7_HAVE_INTERNAL_ULPI
default y
---help---
Select to enable the internal ULPI for USB HS
endchoice #"ULPI Selection"
endmenu # OTG_HS Config
menu "QuadSPI Configuration"
depends on STM32F7_QUADSPI
@ -2103,7 +2149,7 @@ config STM32F7_SPI_DMA
default n
---help---
Use DMA to improve SPI transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT.
config STM32F7_SPI1_DMA
bool "SPI1 DMA"
default n

208
arch/arm/src/stm32f7/chip/stm32_otg.h
View File

@ -149,6 +149,11 @@
#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
/* USB PHY OFFSET */
#define STM32_USBPHYC_PLL1_OFFSET 0x0000 /* USBPHYC PLL1 control register */
#define STM32_USBPHYC_TUNE_OFFSET 0x000c /* USBPHYC tuning control register */
#define STM32_USBPHYC_LDO_OFFSET 0x0018 /* USBPHYC LDO control and status register */
/* Register Addresses *******************************************************************************/
@ -231,6 +236,11 @@
#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
/* USB PHY Registers */
#define STM32_USBPHYC_PLL1 (STM32_USBPHYC_BASE+STM32_USBPHYC_PLL1_OFFSET)
#define STM32_USBPHYC_TUNE (STM32_USBPHYC_BASE+STM32_USBPHYC_TUNE_OFFSET)
#define STM32_USBPHYC_LDO (STM32_USBPHYC_BASE+STM32_USBPHYC_LDO_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* Core global control and status registers */
@ -250,56 +260,68 @@
#define OTG_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */
#define OTG_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */
#define OTG_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */
/* Bits 13-15: Reserved, must be kept at reset value */
/* Bits 13-15: Reserved, must be kept at reset value */
#define OTG_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */
#define OTG_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */
#define OTG_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */
#define OTG_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */
#define OTG_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Interrupt register */
/* Bits 1:0 Reserved, must be kept at reset value */
/* Bits 1:0 Reserved, must be kept at reset value */
#define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */
/* Bits 3-7: Reserved, must be kept at reset value */
/* Bits 3-7: Reserved, must be kept at reset value */
#define OTG_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */
#define OTG_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */
/* Bits 16:10 Reserved, must be kept at reset value */
/* Bits 16:10 Reserved, must be kept at reset value */
#define OTG_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */
#define OTG_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */
#define OTG_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */
#define OTG_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Bits 21-31: Reserved, must be kept at reset value */
/* AHB configuration register */
#define OTG_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */
/* Bits 1-6: Reserved, must be kept at reset value */
/* Bits 1-6: Reserved, must be kept at reset value */
#define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */
#define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */
/* Bits 20-31: Reserved, must be kept at reset value */
/* Bits 20-31: Reserved, must be kept at reset value */
/* USB configuration register */
#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
#define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT)
/* Bits 3-5: Reserved, must be kept at reset value */
/* Bits 3-5: Reserved, must be kept at reset value */
#define OTG_GUSBCFG_ULPISEL (1 << 4) /* Bit 4: Select which high speed interface is to be used STM32F7x3 only*/
#define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */
/* Bit 7: Reserved, must be kept at reset value */
/* Bit 7: Reserved, must be kept at reset value */
#define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */
#define OTG_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */
#define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
#define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT)
# define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT)
/* Bits 14-28: Reserved, must be kept at reset value */
/* Bit 14: Reserved, must be kept at reset value */
#define OTG_GUSBCFG_PHYLPC (1 << 15) /* Bit 15: PHY Low-power clock select for USB OTG HS */
/* Bit 16: Reserved, must be kept at reset value */
#define OTG_GUSBCFG_ULPIFSLS (1 << 17) /* Bit 17: ULPI FS/LS select for USB OTG HS */
#define OTG_GUSBCFG_ULPIAR (1 << 18) /* Bit 18: ULPI Auto-resume for USB OTG HS */
#define OTG_GUSBCFG_ULPICSM (1 << 19) /* Bit 19: ULPI clock SuspendM for USB OTG HS */
#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20) /* Bit 20: ULPI External VBUS Drive for USB OTG HS */
#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21) /* Bit 21: ULPI external VBUS indicator for USB OTG HS */
#define OTG_GUSBCFG_TSDPS (1 << 22) /* Bit 22: TermSel DLine pulsing selection for USB OTG HS */
#define OTG_GUSBCFG_PCCI (1 << 23) /* Bit 23: Indicator complement for USB OTG HS */
#define OTG_GUSBCFG_PTCI (1 << 24) /* Bit 24: Indicator pass through for USB OTG HS */
#define OTG_GUSBCFG_ULPIIPD (1 << 25) /* Bit 24: ULPI interface protect disable for USB OTG HS */
/* Bit 26-28: Reserved, must be kept at reset value */
#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
#define OTG_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */
/* Bits 20-31: Reserved, must be kept at reset value */
/* Bits 20-31: Reserved, must be kept at reset value */
/* Reset register */
#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */
#define OTG_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */
#define OTG_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */
/* Bit 3 Reserved, must be kept at reset value */
/* Bit 3 Reserved, must be kept at reset value */
#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */
@ -337,12 +359,15 @@
#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
#define OTG_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */
#define OTG_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
#define OTG_GINT_DATAFSUSP (1 << 22) /* Bit 22: Data fetch suspended for USB OTG HS */
#define OTG_GINT_RES23 (1 << 23) /* Bit 23: Reserved, must be kept at reset value */
#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
#define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
#define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
#define OTG_GINT_RES27 (1 << 27) /* Bit 27: Reserved, must be kept at reset value */
#define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
#define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
#define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
@ -388,7 +413,7 @@
# define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-31: Reserved, must be kept at reset value */
/* Bits 25-31: Reserved, must be kept at reset value */
/* Receive FIFO size register */
#define OTG_GRXFSIZ_MASK (0xffff)
@ -431,13 +456,14 @@
# define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT)
# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT)
/* Bit 31 Reserved, must be kept at reset value */
/* Bit 31 Reserved, must be kept at reset value */
/* General core configuration register */
/* Bits 0-15: Reserved, must be kept at reset value */
/* Bits 0-15: Reserved, must be kept at reset value */
#define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */
/* Bit 17 Reserved, must be kept at reset value */
/* Bit 17 Reserved, must be kept at reset value */
#define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
/* Bits 22-31: Reserved, must be kept at reset value */
#define OTG_GCCFG_PHYHSEN (1 << 23) /* Bit 21: NOT In datasheet but in STMCube.. */
/* Bits 22-31: Reserved, must be kept at reset value */
/* Core ID register (32-bit product ID) */
/* Host periodic transmit FIFO size register */
@ -465,7 +491,7 @@
# define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
# define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
/* Bits 31:3 Reserved, must be kept at reset value */
/* Bits 31:3 Reserved, must be kept at reset value */
/* Host frame interval register */
#define OTG_HFIR_MASK (0xffff)
@ -514,7 +540,7 @@
#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
/* Bit 9: Reserved, must be kept at reset value */
/* Bit 9: Reserved, must be kept at reset value */
#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
#define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT)
# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
@ -532,7 +558,7 @@
#define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT)
# define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */
# define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */
/* Bits 19-31: Reserved, must be kept at reset value */
/* Bits 19-31: Reserved, must be kept at reset value */
/* Host channel-n characteristics register */
@ -543,7 +569,7 @@
#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
# define OTG_HCCHAR_EPDIR_OUT (0)
# define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR
/* Bit 16 Reserved, must be kept at reset value */
/* Bit 16 Reserved, must be kept at reset value */
#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT)
@ -563,7 +589,7 @@
#define OTG_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
#define OTG_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
/* Bit 2: Reserved, must be kept at reset value */
/* Bit 2: Reserved, must be kept at reset value */
#define OTG_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
#define OTG_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
#define OTG_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
@ -572,7 +598,7 @@
#define OTG_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
#define OTG_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
#define OTG_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */
/* Bits 11-31 Reserved, must be kept at reset value */
/* Bits 11-31 Reserved, must be kept at reset value */
/* Host channel-n interrupt register */
#define OTG_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
@ -586,16 +612,18 @@
# define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */
# define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */
/* Bit 31 Reserved, must be kept at reset value */
/* Bit 31 Reserved, must be kept at reset value */
/* Device-mode control and status registers */
/* Device configuration register */
#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT)
# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High Speed */
# define OTG_DCFG_DSPD_FS_USING_HS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using High Speed*/
# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */
#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
/* Bit 3: Reserved, must be kept at reset value */
/* Bit 3: Reserved, must be kept at reset value */
#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
#define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT)
#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
@ -604,7 +632,7 @@
# define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bits 13-31 Reserved, must be kept at reset value */
/* Bits 13-31 Reserved, must be kept at reset value */
/* Device control register */
#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */
@ -631,42 +659,47 @@
#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
/* Bits 12-31: Reserved, must be kept at reset value */
/* Bits 12-31: Reserved, must be kept at reset value */
/* Device status register */
#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
#define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT)
# define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */
/* Bits 4-7: Reserved, must be kept at reset value */
/* Bits 4-7: Reserved, must be kept at reset value */
#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
#define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT)
#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */
#define OTG_DSTS_SOFFN_EVEN 0
#define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0
/* Bits 22-31: Reserved, must be kept at reset value */
/* Bits 22-31: Reserved, must be kept at reset value */
/* Device IN endpoint common interrupt mask register */
#define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
/* Bit 2: Reserved, must be kept at reset value */
#define OTG_DIEPMSK_AHBERRM (1 << 2) /* Bit 2: AHB error mask for USB OTG HS */
#define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */
#define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */
#define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */
/* Bits 7-31: Reserved, must be kept at reset value */
/* Bit 7: Reserved, must be kept at reset value */
#define OTG_DIEPMSK_TXFURM (1 << 8) /* Bit 8: FIFO underrun mask */
/* Bits 9-12: Reserved, must be kept at reset value */
#define OTG_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */
/* Bits 14-31: Reserved, must be kept at reset value */
/* Device OUT endpoint common interrupt mask register */
#define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTG_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
/* Bit 2: Reserved, must be kept at reset value */
/* Bit 2: Reserved, must be kept at reset value */
#define OTG_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */
#define OTG_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */
/* Bits 5-31: Reserved, must be kept at reset value */
/* Bits 5-31: Reserved, must be kept at reset value */
/* Device all endpoints interrupt and All endpoints interrupt mask registers */
#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */
#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */
#define OTG_DAINT_IEP_MASK (0xffff << OTG_DAINT_IEP_SHIFT)
# define OTG_DAINT_IEP(n) (1 << (n))
#define OTG_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */
@ -693,20 +726,20 @@
# define OTG_DIEPCTL0_MPSIZ_32 (1 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTG_DIEPCTL0_MPSIZ_16 (2 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTG_DIEPCTL0_MPSIZ_8 (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved, must be kept at reset value */
/* Bits 2-14: Reserved, must be kept at reset value */
#define OTG_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved, must be kept at reset value */
/* Bit 16: Reserved, must be kept at reset value */
#define OTG_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DIEPCTL0_EPTYP_MASK (3 << OTG_DIEPCTL0_EPTYP_SHIFT)
# define OTG_DIEPCTL0_EPTYP_CTRL (0 << OTG_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
/* Bit 20: Reserved, must be kept at reset value */
/* Bit 20: Reserved, must be kept at reset value */
#define OTG_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTG_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTG_DIEPCTL0_TXFNUM_MASK (15 << OTG_DIEPCTL0_TXFNUM_SHIFT)
#define OTG_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved, must be kept at reset value */
/* Bits 28-29: Reserved, must be kept at reset value */
#define OTG_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
@ -714,7 +747,7 @@
#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved, must be kept at reset value */
/* Bits 11-14: Reserved, must be kept at reset value */
#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
# define OTG_DIEPCTL_EVEN (0)
@ -728,7 +761,7 @@
# define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
/* Bit 20: Reserved, must be kept at reset value */
/* Bit 20: Reserved, must be kept at reset value */
#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT)
@ -744,21 +777,21 @@
#define OTG_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTG_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
/* Bit 2: Reserved, must be kept at reset value */
/* Bit 2: Reserved, must be kept at reset value */
#define OTG_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */
#define OTG_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */
/* Bit 5: Reserved, must be kept at reset value */
/* Bit 5: Reserved, must be kept at reset value */
#define OTG_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */
#define OTG_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */
/* Bits 8-31: Reserved, must be kept at reset value */
/* Bits 8-31: Reserved, must be kept at reset value */
/* Device IN endpoint 0 transfer size register */
#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
#define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT)
/* Bits 21-31: Reserved, must be kept at reset value */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Device IN endpoint n transfer size register */
#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
@ -767,7 +800,7 @@
#define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT)
#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
#define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT)
/* Bit 31: Reserved, must be kept at reset value */
/* Bit 31: Reserved, must be kept at reset value */
/* Device OUT endpoint TxFIFO status register */
#define OTG_DTXFSTS_MASK (0xffff)
@ -780,19 +813,19 @@
# define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved, must be kept at reset value */
/* Bits 2-14: Reserved, must be kept at reset value */
#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved, must be kept at reset value */
/* Bit 16: Reserved, must be kept at reset value */
#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT)
# define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved, must be kept at reset value */
/* Bits 22-25: Reserved, must be kept at reset value */
#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved, must be kept at reset value */
/* Bits 28-29: Reserved, must be kept at reset value */
#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
@ -800,7 +833,7 @@
#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved, must be kept at reset value */
/* Bits 11-14: Reserved, must be kept at reset value */
#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */
# define OTG_DOEPCTL_DATA0 (0)
@ -817,7 +850,7 @@
# define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved, must be kept at reset value */
/* Bits 22-25: Reserved, must be kept at reset value */
#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
@ -831,22 +864,22 @@
#define OTG_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTG_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
/* Bit 2: Reserved, must be kept at reset value */
/* Bit 2: Reserved, must be kept at reset value */
#define OTG_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */
#define OTG_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */
/* Bit 5: Reserved, must be kept at reset value */
/* Bit 5: Reserved, must be kept at reset value */
#define OTG_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */
/* Bits 7-31: Reserved, must be kept at reset value */
/* Bits 7-31: Reserved, must be kept at reset value */
/* Device OUT endpoint-0 transfer size register */
#define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTG_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */
/* Bits 20-28: Reserved, must be kept at reset value */
/* Bits 20-28: Reserved, must be kept at reset value */
#define OTG_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
#define OTG_DOEPTSIZ0_STUPCNT_MASK (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT)
/* Bit 31: Reserved, must be kept at reset value */
/* Bit 31: Reserved, must be kept at reset value */
/* Device OUT endpoint-n transfer size register */
#define OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
@ -866,8 +899,57 @@
#define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */
#define OTG_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */
/* Bits 2-3: Reserved, must be kept at reset value */
/* Bits 2-3: Reserved, must be kept at reset value */
#define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
/* Bits 5-31: Reserved, must be kept at reset value */
/* Bits 5-31: Reserved, must be kept at reset value */
/* USB PHYC Registers */
/* USBPHYC PLL1 control register */
#define USBPHYC_PLL1_EN (1 << 0) /* Bit 0: Enable the PLL1 inside PHY */
#define USBPHYC_PLL1_SEL_SHIFT (1) /* Bits 1-3: Controls the PHY PLL1 input clock frequency selection */
#define USBPHYC_PLL1_SEL_MASK (7 << USBPHYC_PLL1SEL_SHIFT)
# define USBPHYC_PLL1_SEL_12MHz (0 << USBPHYC_PLL1_SEL_SHIFT) /* 12 MHz */
# define USBPHYC_PLL1_SEL_12_5MHz (1 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */
# define USBPHYC_PLL1_SEL_12_5bMHz (2 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */
# define USBPHYC_PLL1_SEL_16MHz (3 << USBPHYC_PLL1_SEL_SHIFT) /* 16 MHz */
# define USBPHYC_PLL1_SEL_24MHz (4 << USBPHYC_PLL1_SEL_SHIFT) /* 24 MHz */
# define USBPHYC_PLL1_SEL_25MHz (5 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */
# define USBPHYC_PLL1_SEL_25bMHz (6 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */
/* USBPHYC tuning control register */
#define USBPHYC_TUNE_INCURREN (1 << 0) /* Bit 0: Controls the current boosting function */
#define USBPHYC_TUNE_INCURRINT (1 << 1) /* Bit 1: Controls PHY current boosting */
#define USBPHYC_TUNE_LFSCAPEN (1 << 2) /* Bit 2: Enables the Low Full Speed feedback capacitor */
#define USBPHYC_TUNE_HSDRVSLEW (1 << 3) /* Bit 3: Controls the HS driver slew rate */
#define USBPHYC_TUNE_HSDRVDCLEV (1 << 4) /* Bit 4: Decreases the HS driver DC level */
#define USBPHYC_TUNE_HSDRVDCCUR (1 << 5) /* Bit 5: Increases the HS Driver DC level. Not applicable
* during the HS Test J and Test K data transfer */
#define USBPHYC_TUNE_HSDRVCURINCR (1 << 6) /* Bit 6: Enable the HS driver current increase feature */
#define USBPHYC_TUNE_FSDRVRFADJ (1 << 7) /* Bit 7: Tuning pin to adjust the full speed rise/fall time */
#define USBPHYC_TUNE_HSDRVRFRED (1 << 8) /* Bit 8: High Speed rise-fall reduction enable */
#define USBPHYC_TUNE_HSDRVCHKITRM_SHIFT (9) /* Bits 9-12 : HS Driver current trimming pins for choke compensation */
#define USBPHYC_TUNE_HSDRVCHKITRM_MASK (0xF << USBPHYC_TUNE_HSDRVCHKITRM_SHIFT)
#define USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT (13) /* Bits 13-14 : Controls the PHY bus HS driver impedance tuning for choke */
#define USBPHYC_TUNE_HSDRVCHKZTRM_MASK (3 << USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT)
#define USBPHYC_TUNE_SQLCHCTL_SHIFT (15) /* Bits 15-16 : Adjust the squelch DC threshold value */
#define USBPHYC_TUNE_SQLCHCTL_MASK (3 << USBPHYC_TUNE_SQLCHCTL_SHIFT)
#define USBPHYC_TUNE_HDRXGNEQEN (1 << 17) /* Bit 17: Enables the HS Rx Gain Equalizer */
#define USBPHYC_TUNE_STAGSEL (1 << 18) /* Bit 18: HS Tx staggering enable */
#define USBPHYC_TUNE_HSFALLPREEM (1 << 19) /* Bit 19: HS Fall time control of single ended signals during pre-emphasis */
#define USBPHYC_TUNE_HSRXOFF_SHIFT (20) /* Bits 20-21 : HS Receiver Offset adjustment */
#define USBPHYC_TUNE_HSRXOFF_MASK (3 << USBPHYC_TUNE_HSRXOFF_SHIFT)
#define USBPHYC_TUNE_SHTCCTCTLPROT (1 << 22) /* Bit 22: Enables the short circuit protection circuitry in LS/FS driver */
#define USBPHYC_TUNE_SQLBYP (1 << 23) /* Bit 23: This pin is used to bypass the squelch inter-locking circuitry */
/* USBPHYC LDO control and status register */
#define USBPHYC_LDO_USED (1 << 0) /* Bit 0: Indicates the presence of the LDO in the chip. */
#define USBPHYC_LDO_STATUS (1 << 1) /* Bit 1: Monitors the status of the PHY's LDO. */
/* It looks like they made a mistake, is it ENABLE or DISABLE? */
#define USBPHYC_LDO_ENABLE (1 << 2) /* Bit 2: Controls disable of the High Speed PHY's LDO. */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */

3
arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
View File

@ -900,8 +900,11 @@
#define GPIO_UART4_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
#define GPIO_UART4_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
#define GPIO_UART4_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
#define GPIO_UART4_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
#define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9)
#define GPIO_UART5_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8)

28
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
View File

@ -732,20 +732,20 @@
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11)
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11)
#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4)
#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0)
/* QuadSPI */

19
arch/arm/src/stm32f7/stm32_otg.h
View File

@ -47,13 +47,18 @@
#include "chip.h"
#include "chip/stm32_otg.h"
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTG_PRI
# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
#if defined(CONFIG_STM32F7_OTGFS)
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
# define STM32_OTG_BASE STM32_USBOTGFS_BASE
@ -62,17 +67,19 @@
# define GPIO_OTG_DP GPIO_OTGFS_DP
# define GPIO_OTG_ID GPIO_OTGFS_ID
# define GPIO_OTG_SOF GPIO_OTGFS_SOF
# define GPIO_OTG_VBUS GPIO_OTGFS_VBUS
# define STM32_OTG_FIFO_SIZE 1280
#endif
#if defined(CONFIG_STM32F7_OTGHS)
#if defined(CONFIG_STM32F7_OTGFSHS)
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
# define STM32_OTG_BASE STM32_USBOTGHS_BASE
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
# define GPIO_OTG_DM GPIO_OTGHS_DM
# define GPIO_OTG_DP GPIO_OTGHS_DP
# define GPIO_OTG_ID GPIO_OTGHS_ID
# define GPIO_OTG_SOF GPIO_OTGHS_SOF
# define GPIO_OTG_DM GPIO_OTGHSFS_DM
# define GPIO_OTG_DP GPIO_OTGHSFS_DP
# define GPIO_OTG_ID GPIO_OTGHSFS_ID
# define GPIO_OTG_SOF GPIO_OTGHSFS_SOF
# define GPIO_OTG_VBUS GPIO_OTGHSFS_VBUS
# define STM32_OTG_FIFO_SIZE 4096
#endif

2606
arch/arm/src/stm32f7/stm32_otgdev.c
View File

File diff suppressed because it is too large Load Diff

6
arch/arm/src/stm32f7/stm32_usbhost.h
View File

@ -43,7 +43,7 @@
* CONFIG_USBHOST - Enable general USB host support
* CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
* or
* CONFIG_STM32F7_OTGHS - Enable the STM32 USB OTG HS block
* CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block
* CONFIG_STM32F7_SYSCFG - Needed
*
* Options:
@ -68,7 +68,7 @@
#include <nuttx/config.h>
#include <stdbool.h>
#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)) && \
#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \
defined(CONFIG_USBHOST)
/************************************************************************************
@ -120,5 +120,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable);
#endif
#endif /* __ASSEMBLY__ */
#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGHS) && CONFIG_USBHOST */
#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */

26
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
View File

@ -227,8 +227,8 @@ static inline void rcc_enableahb1(void)
#endif
#endif
#ifdef CONFIG_STM32F7_OTGHS
#ifdef BOARD_ENABLE_USBOTG_HSULPI
#ifdef CONFIG_STM32F7_OTGFSHS
#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
@ -237,7 +237,7 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGHS */
#endif /* CONFIG_STM32F7_OTGFSHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
@ -657,6 +657,13 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_LTDCEN;
#endif
#ifdef CONFIG_STM32F7_OTGFSHS
#ifdef CONFIG_STM32F7_INTERNAL_ULPI
regval |= RCC_APB2ENR_OTGPHYCEN;
#endif
#endif
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
}
@ -833,8 +840,8 @@ static void stm32_stdclockconfig(void)
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
/* The Flash memory interface accelerates code execution with a system of
* instruction prefetch and cache lines on ITCM interface (ART
/* The Flash memory interface accelerates code execution with a system
* of instruction prefetch and cache lines on ITCM interface (ART
* Accelerator™).
*/
@ -862,7 +869,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIP_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK
# if defined(CONFIG_STM32F7_LTDC)
@ -899,7 +906,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR1);
/* Enable PLLSAI */
regval = getreg32(STM32_RCC_CR);
@ -917,7 +923,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX)
| RCC_PLLI2SCFGR_PLLI2SP_MASK
# endif
@ -932,7 +938,7 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_PLLI2SCFGR);
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
| RCC_DCKCFGR2_UART4SEL_MASK
| RCC_DCKCFGR2_UART5SEL_MASK
@ -951,7 +957,7 @@ static void stm32_stdclockconfig(void)
| RCC_DCKCFGR2_SDMMCSEL_MASK
| RCC_DCKCFGR2_SDMMC2SEL_MASK);
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
regval |= (STM32_RCC_DCKCFGR2_USART1SRC
| STM32_RCC_DCKCFGR2_USART2SRC
| STM32_RCC_DCKCFGR2_UART4SRC
| STM32_RCC_DCKCFGR2_UART5SRC

20
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
View File

@ -230,17 +230,18 @@ static inline void rcc_enableahb1(void)
#endif
#endif
#ifdef CONFIG_STM32F7_OTGHS
#ifdef BOARD_ENABLE_USBOTG_HSULPI
#ifdef CONFIG_STM32F7_OTGFSHS
#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGHS */
#endif /* CONFIG_STM32F7_OTGFSHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
@ -836,8 +837,8 @@ static void stm32_stdclockconfig(void)
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
/* The Flash memory interface accelerates code execution with a system of
* instruction prefetch and cache lines on ITCM interface (ART
/* The Flash memory interface accelerates code execution with a system
* of instruction prefetch and cache lines on ITCM interface (ART
* Accelerator™).
*/
@ -865,7 +866,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIP_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK);
@ -892,7 +893,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR1);
/* Enable PLLSAI */
regval = getreg32(STM32_RCC_CR);
@ -910,7 +910,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_PLLI2SCFGR);
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
| RCC_DCKCFGR2_UART4SEL_MASK
| RCC_DCKCFGR2_UART5SEL_MASK
@ -937,7 +937,7 @@ static void stm32_stdclockconfig(void)
| RCC_DCKCFGR2_CK48MSEL_MASK
| RCC_DCKCFGR2_SDMMCSEL_MASK);
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
regval |= (STM32_RCC_DCKCFGR2_USART1SRC
| STM32_RCC_DCKCFGR2_USART2SRC
| STM32_RCC_DCKCFGR2_UART4SRC
| STM32_RCC_DCKCFGR2_UART5SRC

17
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
View File

@ -236,7 +236,7 @@ static inline void rcc_enableahb1(void)
#endif
#endif
#ifdef CONFIG_STM32F7_OTGHS
#ifdef CONFIG_STM32F7_OTGFSHS
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
@ -246,7 +246,7 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGHS */
#endif /* CONFIG_STM32F7_OTGFSHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
@ -503,7 +503,6 @@ static inline void rcc_enableapb1(void)
regval |= (RCC_APB1ENR_CAN3EN);
#endif
#ifdef CONFIG_STM32F7_CEC
/* CEC clock enable. */
@ -855,8 +854,8 @@ static void stm32_stdclockconfig(void)
regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
/* The Flash memory interface accelerates code execution with a system of
* instruction prefetch and cache lines on ITCM interface (ART
/* The Flash memory interface accelerates code execution with a system
* of instruction prefetch and cache lines on ITCM interface (ART
* Accelerator™).
*/
@ -884,7 +883,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIP_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK);
@ -932,7 +931,7 @@ static void stm32_stdclockconfig(void)
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
@ -956,7 +955,7 @@ static void stm32_stdclockconfig(void)
#endif
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
| RCC_DCKCFGR2_UART4SEL_MASK
| RCC_DCKCFGR2_UART5SEL_MASK
@ -974,7 +973,7 @@ static void stm32_stdclockconfig(void)
| RCC_DCKCFGR2_SDMMC2SEL_MASK
| RCC_DCKCFGR2_DSISEL_MASK);
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
regval |= (STM32_RCC_DCKCFGR2_USART1SRC
| STM32_RCC_DCKCFGR2_USART2SRC
| STM32_RCC_DCKCFGR2_UART4SRC
| STM32_RCC_DCKCFGR2_UART5SRC

58
drivers/usbdev/Kconfig
View File

@ -128,6 +128,52 @@ config USBDEV_TRACE_INITIALIDSET
endif # USBDEV_TRACE
menuconfig USBDEV_CUSTOM_TXFIFO_SIZE
bool "Custom TX Fifo size"
default n
---help---
Enables custom TX Fifo size
if USBDEV_CUSTOM_TXFIFO_SIZE
config USBDEV_EP0_TXFIFO_SIZE
int "USBDEV_EP0_TXFIFO_SIZE"
default 64
config USBDEV_EP1_TXFIFO_SIZE
int "USBDEV_EP1_TXFIFO_SIZE"
default 0
config USBDEV_EP2_TXFIFO_SIZE
int "USBDEV_EP2_TXFIFO_SIZE"
default 0
config USBDEV_EP3_TXFIFO_SIZE
int "USBDEV_EP3_TXFIFO_SIZE"
default 0
config USBDEV_EP4_TXFIFO_SIZE
int "USBDEV_EP4_TXFIFO_SIZE"
default 0
config USBDEV_EP5_TXFIFO_SIZE
int "USBDEV_EP5_TXFIFO_SIZE"
default 0
config USBDEV_EP6_TXFIFO_SIZE
int "USBDEV_EP6_TXFIFO_SIZE"
default 0
config USBDEV_EP7_TXFIFO_SIZE
int "USBDEV_EP7_TXFIFO_SIZE"
default 0
config USBDEV_EP8_TXFIFO_SIZE
int "USBDEV_EP8_TXFIFO_SIZE"
default 0
endif # USBDEV_CUSTOM_TXFIFO_SIZE
comment "USB Device Class Driver Options"
menuconfig USBDEV_COMPOSITE
@ -691,12 +737,12 @@ menuconfig RNDIS
if RNDIS
config RNDIS_COMPOSITE
bool "RNDIS composite support"
default n
depends on USBDEV_COMPOSITE
---help---
Configure the RNDIS driver as part of a composite driver
(only if USBDEV_COMPOSITE is also defined)
bool "RNDIS composite support"
default n
depends on USBDEV_COMPOSITE
---help---
Configure the RNDIS driver as part of a composite driver
(only if USBDEV_COMPOSITE is also defined)
if !RNDIS_COMPOSITE