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Adapt some drivers to utilize the IRQ argument feature.

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This commit is contained in:
Gregory Nutt 2017-02-27 20:54:18 -06:00
parent 704df7bd39
commit 7d2d541c70
21 changed files with 169 additions and 1308 deletions
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103
arch/arm/src/a1x/a1x_serial.c
View File

@ -93,7 +93,6 @@ struct up_dev_s
uint32_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t ier; /* Saved IER value */
xcpt_t handler; /* UART interrupt handler */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
@ -108,31 +107,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int uart_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_A1X_UART0
static int uart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART1
static int uart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART2
static int uart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART3
static int uart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART4
static int uart4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART5
static int uart5_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART6
static int uart6_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_A1X_UART7
static int uart7_interrupt(int irq, void *context, FAR void *arg);
#endif
static int uart_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@ -214,7 +189,6 @@ static struct up_dev_s g_uart0priv =
{
.uartbase = A1X_UART0_VADDR,
.baud = CONFIG_UART0_BAUD,
.handler = uart0_interrupt,
.irq = A1X_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
@ -245,7 +219,6 @@ static struct up_dev_s g_uart1priv =
{
.uartbase = A1X_UART1_VADDR,
.baud = CONFIG_UART1_BAUD,
.handler = uart1_interrupt,
.irq = A1X_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
@ -276,7 +249,6 @@ static struct up_dev_s g_uart2priv =
{
.uartbase = A1X_UART2_VADDR,
.baud = CONFIG_UART2_BAUD,
.handler = uart2_interrupt,
.irq = A1X_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
@ -307,7 +279,6 @@ static struct up_dev_s g_uart3priv =
{
.uartbase = A1X_UART3_VADDR,
.baud = CONFIG_UART3_BAUD,
.handler = uart3_interrupt,
.irq = A1X_IRQ_UART3,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
@ -338,7 +309,6 @@ static struct up_dev_s g_uart4priv =
{
.uartbase = A1X_UART4_VADDR,
.baud = CONFIG_UART4_BAUD,
.handler = uart4_interrupt,
.irq = A1X_IRQ_UART4,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
@ -369,7 +339,6 @@ static struct up_dev_s g_uart5priv =
{
.uartbase = A1X_UART5_VADDR,
.baud = CONFIG_UART5_BAUD,
.handler = uart5_interrupt,
.irq = A1X_IRQ_UART5,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
@ -400,7 +369,6 @@ static struct up_dev_s g_uart6priv =
{
.uartbase = A1X_UART6_VADDR,
.baud = CONFIG_UART6_BAUD,
.handler = uart6_interrupt,
.irq = A1X_IRQ_UART6,
.parity = CONFIG_UART6_PARITY,
.bits = CONFIG_UART6_BITS,
@ -431,7 +399,6 @@ static struct up_dev_s g_uart7priv =
{
.uartbase = A1X_UART7_VADDR,
.baud = CONFIG_UART7_BAUD,
.handler = uart7_interrupt,
.irq = A1X_IRQ_UART7,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
@ -1068,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, uart_interrupt, priv);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -1110,12 +1077,14 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int uart_interrupt(struct uart_dev_s *dev)
static int uart_interrupt(int irq, void *context, void *arg)
{
struct up_dev_s *priv;
uint32_t status;
int passes;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv = (struct up_dev_s *)arg;
uint32_t status;
int passes;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
@ -1201,62 +1170,6 @@ static int uart_interrupt(struct uart_dev_s *dev)
return OK;
}
#ifdef CONFIG_A1X_UART0
static int uart0_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart0port);
}
#endif
#ifdef CONFIG_A1X_UART1
static int uart1_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart1port);
}
#endif
#ifdef CONFIG_A1X_UART2
static int uart2_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart2port);
}
#endif
#ifdef CONFIG_A1X_UART3
static int uart3_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart3port);
}
#endif
#ifdef CONFIG_A1X_UART4
static int uart4_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart4port);
}
#endif
#ifdef CONFIG_A1X_UART5
static int uart5_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart5port);
}
#endif
#ifdef CONFIG_A1X_UART6
static int uart6_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart6port);
}
#endif
#ifdef CONFIG_A1X_UART7
static int uart7_interrupt(int irq, void *context, FAR void *arg)
{
return uart_interrupt(&g_uart7port);
}
#endif
/****************************************************************************
* Name: up_ioctl
*

35
arch/arm/src/efm32/efm32_leserial.c
View File

@ -134,7 +134,6 @@
struct efm32_config_s
{
uintptr_t uartbase; /* Base address of UART registers */
xcpt_t handler; /* Interrupt handler */
uint32_t baud; /* Configured baud */
uint8_t irq; /* IRQ associated with this LEUART (for enable) */
uint8_t parity; /* 0=none, 1=odd, 2=even */
@ -163,13 +162,7 @@ static int efm32_setup(struct uart_dev_s *dev);
static void efm32_shutdown(struct uart_dev_s *dev);
static int efm32_attach(struct uart_dev_s *dev);
static void efm32_detach(struct uart_dev_s *dev);
static int efm32_interrupt(struct uart_dev_s *dev);
#if defined(CONFIG_EFM32_LEUART0)
static int efm32_leuart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_EFM32_LEUART1)
static int efm32_leuart1_interrupt(int irq, void *context, FAR void *arg);
#endif
static int efm32_interrupt(int irq, void *context, FAR void *arg);
static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg);
static int efm32_receive(struct uart_dev_s *dev, uint32_t *status);
static void efm32_rxint(struct uart_dev_s *dev, bool enable);
@ -219,7 +212,6 @@ static char g_leuart1txbuffer[CONFIG_LEUART1_TXBUFSIZE];
static const struct efm32_config_s g_leuart0config =
{
.uartbase = EFM32_LEUART0_BASE,
.handler = efm32_leuart0_interrupt,
.baud = CONFIG_LEUART0_BAUD,
.irq = EFM32_IRQ_LEUART0,
.parity = CONFIG_LEUART0_PARITY,
@ -255,7 +247,6 @@ static struct uart_dev_s g_leuart0port =
static struct efm32_config_s g_leuart1config =
{
.uartbase = EFM32_LEUART1_BASE,
.handler = efm32_leuart1_interrupt,
.baud = CONFIG_LEUART1_BAUD,
.irq = EFM32_IRQ_LEUART1,
.parity = CONFIG_LEUART1_PARITY,
@ -429,7 +420,7 @@ static int efm32_attach(struct uart_dev_s *dev)
* disabled in the C2 register.
*/
ret = irq_attach(config->irq, config->handler, NULL);
ret = irq_attach(config->irq, efm32_interrupt, dev);
if (ret >= 0)
{
up_enable_irq(config->irq);
@ -471,12 +462,14 @@ static void efm32_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int efm32_interrupt(struct uart_dev_s *dev)
static int efm32_interrupt(int irq, void *context, FAR void *arg)
{
struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct efm32_leuart_s *priv;
uint32_t intflags;
DEBUGASSERT(priv);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct efm32_leuart_s *)dev->priv;
/* Read the interrupt flags register */
@ -534,20 +527,6 @@ static int efm32_interrupt(struct uart_dev_s *dev)
return OK;
}
#if defined(CONFIG_EFM32_LEUART0)
static int efm32_leuart0_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_interrupt(&g_leuart0port);
}
#endif
#if defined(CONFIG_EFM32_LEUART1)
static int efm32_leuart1_interrupt(int irq, void *context, FAR void *arg)
{
return efm32_interrupt(&g_leuart1port);
}
#endif
/****************************************************************************
* Name: efm32_ioctl
*

98
arch/arm/src/efm32/efm32_pwm.c
View File

@ -133,19 +133,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
defined(CONFIG_EFM32_TIMER2_PWM) || \
defined(CONFIG_EFM32_TIMER3_PWM) \
)
static int pwm_interrupt(struct efm32_pwmtimer_s *priv);
#if defined(CONFIG_EFM32_TIMER0_PWM)
static int pwm_timer0_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_EFM32_TIMER1_PWM)
static int pwm_timer1_interrupt(int irq, void *context);
#endif
#if defined(CONFIG_EFM32_TIMER2_PWM)
static int pwm_timer2_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_EFM32_TIMER3_PWM)
static int pwm_timer3_interrupt(int irq, void *context, FAR void *arg);
#endif
static int pwm_interrupt(int irq, void *context, FAR void *arg);
static uint8_t pwm_pulsecount(uint32_t count);
#endif
@ -446,7 +434,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
* Handle timer interrupts.
*
* Input parameters:
* priv - A reference to the lower half PWM driver state structure
* Standard interrupt handler arguments.
*
* Returned Value:
* Zero on success; a negated errno value on failure
@ -459,12 +447,15 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
defined(CONFIG_EFM32_TIMER3_PWM) \
)
#warning "not yet implemented"
static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
static int pwm_interrupt(int irq, void *context, FAR void *arg)
{
/* TODO pwm_interrupt */
#if 0
struct efm32_pwmtimer_s *priv = (struct efm32_pwmtimer_s *)arg;
uint32_t regval;
DEBUGASSERT(priv != NULL);
/* Verify that this is an update interrupt. Nothing else is expected. */
regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
@ -532,48 +523,6 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
}
#endif
/****************************************************************************
* Name: pwm_timer1/3_interrupt
*
* Description:
* Handle timer 1..3 interrupts.
*
* Input parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER0_PWM)
static int pwm_timer0_interrupt(int irq, void *context, FAR void *arg)
{
return pwm_interrupt(&g_pwm0dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER1_PWM)
static int pwm_timer1_interrupt(int irq, void *context)
{
return pwm_interrupt(&g_pwm1dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER2_PWM)
static int pwm_timer2_interrupt(int irq, void *context, FAR void *arg)
{
return pwm_interrupt(&g_pwm2dev);
}
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_EFM32_TIMER3_PWM)
static int pwm_timer3_interrupt(int irq, void *context, FAR void *arg)
{
return pwm_interrupt(&g_pwm3dev);
}
#endif
/****************************************************************************
* Name: pwm_pulsecount
*
@ -866,50 +815,22 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
#ifdef CONFIG_EFM32_TIMER0_PWM
case 0:
lower = &g_pwm0dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer0_interrupt, NULL);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER1_PWM
case 1:
lower = &g_pwm1dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer0_interrupt, NULL);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER2_PWM
case 2:
lower = &g_pwm2dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer2_interrupt, NULL);
up_disable_irq(lower->irq);
#endif
break;
#endif
#ifdef CONFIG_EFM32_TIMER3_PWM
case 3:
lower = &g_pwm3dev;
/* Attach but disable the TIM1 update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_timer3_interrupt, NULL);
up_disable_irq(lower->irq);
#endif
break;
#endif
@ -918,6 +839,13 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
return NULL;
}
/* Attach but disable the timer update interrupt */
#ifdef CONFIG_PWM_PULSECOUNT
irq_attach(lower->irq, pwm_interrupt, lower);
up_disable_irq(lower->irq);
#endif
return (FAR struct pwm_lowerhalf_s *)lower;
}

79
arch/arm/src/imx6/imx_ecspi.c
View File

@ -186,7 +186,6 @@ struct imx_spidev_s
uint8_t spindx; /* SPI index */
#ifndef CONFIG_SPI_POLLWAIT
uint8_t irq; /* SPI IRQ number */
xcpt_t handler; /* ECSPI interrupt handler */
#endif
/* Per SPI callouts to board-specific logic */
@ -223,22 +222,7 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
/* Interrupt handling */
#ifndef CONFIG_SPI_POLLWAIT
static int spi_interrupt(struct imx_spidev_s *priv);
#ifdef CONFIG_IMX6_ECSPI1
static int ecspi1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_ECSPI2
static int ecspi2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_ECSPI3
static int ecspi3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_ECSPI4
static int ecspi4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_ECSPI5
static int ecspi5_interrupt(int irq, void *context, FAR void *arg);
#endif
static int spi_interrupt(int irq, void *context, FAR void *arg);
#endif
/* SPI methods */
@ -307,7 +291,6 @@ static struct imx_spidev_s g_spidev[] =
.spindx = SPI1_NDX,
#ifndef CONFIG_SPI_POLLWAIT
.irq = IMX_IRQ_ECSPI1,
.handler = ecspi1_interrupt,
#endif
.select = imx_spi1select,
.status = imx_spi1status,
@ -324,7 +307,6 @@ static struct imx_spidev_s g_spidev[] =
.spindx = SPI2_NDX,
#ifndef CONFIG_SPI_POLLWAIT
.irq = IMX_IRQ_ECSPI2,
.handler = ecspi2_interrupt,
#endif
.select = imx_spi2select,
.status = imx_spi2status,
@ -341,7 +323,6 @@ static struct imx_spidev_s g_spidev[] =
.spindx = SPI3_NDX,
#ifndef CONFIG_SPI_POLLWAIT
.irq = IMX_IRQ_ECSPI3,
.handler = ecspi3_interrupt,
#endif
.select = imx_spi3select,
.status = imx_spi3status,
@ -358,7 +339,6 @@ static struct imx_spidev_s g_spidev[] =
.spindx = SPI4_NDX,
#ifndef CONFIG_SPI_POLLWAIT
.irq = IMX_IRQ_ECSPI4,
.handler = ecspi4_interrupt,
#endif
.select = imx_spi4select,
.status = imx_spi4status,
@ -375,7 +355,6 @@ static struct imx_spidev_s g_spidev[] =
.spindx = SPI5_NDX,
#ifndef CONFIG_SPI_POLLWAIT
.irq = IMX_IRQ_ECSPI5,
.handler = ecspi5_interrupt,
#endif
.select = imx_spi5select,
.status = imx_spi5status,
@ -759,8 +738,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
****************************************************************************/
#ifndef CONFIG_SPI_POLLWAIT
static int spi_interrupt(struct imx_spidev_s *priv)
static int spi_interrupt(int irq, void *context, FAR void *arg)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)arg;
int ntxd;
DEBUGASSERT(priv != NULL);
@ -790,57 +770,6 @@ static int spi_interrupt(struct imx_spidev_s *priv)
}
#endif
/****************************************************************************
* Name: ecspiN_interrupt, N=1..5
*
* Description:
* Individual ECPSI interrupt handlers.
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* 0: success, <0:Negated error number on failure
*
****************************************************************************/
#ifndef CONFIG_SPI_POLLWAIT
#ifdef CONFIG_IMX6_ECSPI1
static int ecspi1_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spidev[SPI1_NDX]);
}
#endif
#ifdef CONFIG_IMX6_ECSPI2
static int ecspi2_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spidev[SPI2_NDX]);
}
#endif
#ifdef CONFIG_IMX6_ECSPI3
static int ecspi3_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spidev[SPI3_NDX]);
}
#endif
#ifdef CONFIG_IMX6_ECSPI4
static int ecspi4_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spidev[SPI4_NDX]);
}
#endif
#ifdef CONFIG_IMX6_ECSPI5
static int ecspi5_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spidev[SPI5_NDX]);
}
#endif
#endif
/****************************************************************************
* Name: spi_lock
*
@ -1425,7 +1354,7 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
/* Attach the interrupt */
#ifndef CONFIG_SPI_POLLWAIT
DEBUGVERIFY(irq_attach(priv->irq, priv->handler, NULL));
DEBUGVERIFY(irq_attach(priv->irq, spi_interrupt, priv));
#endif
/* Enable SPI */

75
arch/arm/src/imx6/imx_serial.c
View File

@ -199,7 +199,6 @@
struct imx_uart_s
{
xcpt_t handler; /* Interrupt handler */
uint32_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t ucr1; /* Saved UCR1 value */
@ -229,24 +228,7 @@ static int imx_setup(struct uart_dev_s *dev);
static void imx_shutdown(struct uart_dev_s *dev);
static int imx_attach(struct uart_dev_s *dev);
static void imx_detach(struct uart_dev_s *dev);
static int imx_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_IMX6_UART1
static int imx_uart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_UART2
static int imx_uart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_UART3
static int imx_uart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_UART4
static int imx_uart4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_IMX6_UART5
static int imx_uart5_interrupt(int irq, void *context, FAR void *arg);
#endif
static int imx_interrupt(int irq, void *context, FAR void *arg);
static int imx_ioctl(struct file *filep, int cmd, unsigned long arg);
static int imx_receive(struct uart_dev_s *dev, uint32_t *status);
static void imx_rxint(struct uart_dev_s *dev, bool enable);
@ -317,7 +299,6 @@ static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
#ifdef CONFIG_IMX6_UART1
static struct imx_uart_s g_uart1priv =
{
.handler = imx_uart1_interrupt,
.uartbase = IMX_UART1_VBASE,
.baud = CONFIG_UART1_BAUD,
.irq = IMX_IRQ_UART1,
@ -348,7 +329,6 @@ static struct uart_dev_s g_uart1port =
#ifdef CONFIG_IMX6_UART2
static struct imx_uart_s g_uart2priv =
{
.handler = imx_uart2_interrupt,
.uartbase = IMX_UART2_VBASE,
.baud = CONFIG_UART2_BAUD,
.irq = IMX_IRQ_UART2,
@ -377,7 +357,6 @@ static struct uart_dev_s g_uart2port =
#ifdef CONFIG_IMX6_UART3
static struct imx_uart_s g_uart3priv =
{
.handler = imx_uart3_interrupt,
.uartbase = IMX_UART3_REGISTER_BASE,
.baud = IMX_UART3_VBASE,
.irq = IMX_IRQ_UART3,
@ -406,7 +385,6 @@ static struct uart_dev_s g_uart3port =
#ifdef CONFIG_IMX6_UART4
static struct imx_uart_s g_uart4priv =
{
.handler = imx_uart4_interrupt,
.uartbase = IMX_UART4_REGISTER_BASE,
.baud = IMX_UART4_VBASE,
.irq = IMX_IRQ_UART4,
@ -435,7 +413,6 @@ static struct uart_dev_s g_uart4port =
#ifdef CONFIG_IMX6_UART5
static struct imx_uart_s g_uart5priv =
{
.handler = imx_uart5_interrupt,
.uartbase = IMX_UART5_REGISTER_BASE,
.baud = IMX_UART5_VBASE,
.irq = IMX_IRQ_UART5,
@ -618,7 +595,7 @@ static int imx_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, imx_interrupt, priv);
if (ret == OK)
{
/* Configure as a (high) level interrupt */
@ -663,12 +640,16 @@ static void imx_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int imx_interrupt(struct uart_dev_s *dev)
static int imx_interrupt(int irq, void *context, FAR void *arg)
{
struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct imx_uart_s *priv;
uint32_t usr1;
int passes = 0;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct imx_uart_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.
*/
@ -710,46 +691,6 @@ static int imx_interrupt(struct uart_dev_s *dev)
}
}
/****************************************************************************
* Name: imx_uart[n]_interrupt
*
* Description:
* UART-specific interrupt handlers just transfer control to the common
* UART interrupt handler, passing the relevant driver state structure.
*
****************************************************************************/
#ifdef CONFIG_IMX6_UART1
static int imx_uart1_interrupt(int irq, void *context, FAR void *arg)
{
return imx_interrupt(&g_uart1port);
}
#endif
#ifdef CONFIG_IMX6_UART2
static int imx_uart2_interrupt(int irq, void *context, FAR void *arg)
{
return imx_interrupt(&g_uart2port);
}
#endif
#ifdef CONFIG_IMX6_UART3
static int imx_uart3_interrupt(int irq, void *context, FAR void *arg)
{
return imx_interrupt(&g_uart3port);
}
#endif
#ifdef CONFIG_IMX6_UART4
static int imx_uart4_interrupt(int irq, void *context, FAR void *arg)
{
return imx_interrupt(&g_uart4port);
}
#endif
#ifdef CONFIG_IMX6_UART5
static int imx_uart5_interrupt(int irq, void *context, FAR void *arg)
{
return imx_interrupt(&g_uart5port);
}
#endif
/****************************************************************************
* Name: imx_ioctl
*

36
arch/arm/src/sam34/sam_twi.c
View File

@ -162,13 +162,7 @@ static inline void twi_putrel(struct twi_dev_s *priv, unsigned int offset,
static int twi_wait(struct twi_dev_s *priv);
static void twi_wakeup(struct twi_dev_s *priv, int result);
static int twi_interrupt(struct twi_dev_s *priv);
#ifdef CONFIG_SAM34_TWI0
static int twi0_interrupt(int irq, FAR void *context);
#endif
#ifdef CONFIG_SAM34_TWI1
static int twi1_interrupt(int irq, FAR void *context);
#endif
static int twi_interrupt(int irq, FAR void *context, FAR void *arg);
static void twi_timeout(int argc, uint32_t arg, ...);
static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg);
@ -436,14 +430,17 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
*
****************************************************************************/
static int twi_interrupt(struct twi_dev_s *priv)
static int twi_interrupt(int irq, FAR void *context, FAR void *arg);
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
struct i2c_msg_s *msg;
uint32_t sr;
uint32_t imr;
uint32_t pending;
uint32_t regval;
DEBUGASSERT(priv != NULL);
/* Retrieve masked interrupt status */
sr = twi_getrel(priv, SAM_TWI_SR_OFFSET);
@ -554,20 +551,6 @@ static int twi_interrupt(struct twi_dev_s *priv)
return OK;
}
#ifdef CONFIG_SAM34_TWI0
static int twi0_interrupt(int irq, FAR void *context)
{
return twi_interrupt(&g_twi0);
}
#endif
#ifdef CONFIG_SAM34_TWI1
static int twi1_interrupt(int irq, FAR void *context)
{
return twi_interrupt(&g_twi1);
}
#endif
/****************************************************************************
* Name: twi_timeout
*
@ -910,7 +893,6 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
struct i2c_master_s *sam_i2cbus_initialize(int bus)
{
struct twi_dev_s *priv;
xcpt_t handler;
irqstate_t flags;
uint32_t frequency;
unsigned int pid;
@ -938,9 +920,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
sam_configgpio(GPIO_TWI0_CK);
sam_configgpio(GPIO_TWI0_D);
/* Select the interrupt handler, TWI frequency, and peripheral ID */
/* Select the TWI frequency, and peripheral ID */
handler = twi0_interrupt;
frequency = CONFIG_SAM34_TWI0_FREQUENCY;
pid = SAM_PID_TWI0;
}
@ -965,9 +946,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
sam_configgpio(GPIO_TWI1_CK);
sam_configgpio(GPIO_TWI1_D);
/* Select the interrupt handler, TWI frequency, and peripheral ID */
/* Select the TWI frequency, and peripheral ID */
handler = twi1_interrupt;
frequency = CONFIG_SAMA5_TWI1_FREQUENCY;
pid = SAM_PID_TWI1;
}
@ -1006,7 +986,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Attach Interrupt Handler */
irq_attach(priv->irq, handler, NULL);
irq_attach(priv->irq, twi_interrupt, priv);
/* Enable Interrupts */

70
arch/arm/src/sama5/sam_can.c
View File

@ -150,7 +150,6 @@ struct sam_config_s
uint8_t port; /* CAN port number (1 or 2) */
uint8_t pid; /* CAN periperal ID/IRQ number */
uint8_t nrecvmb; /* Number of receive mailboxes */
xcpt_t handler; /* CAN interrupt handler */
uintptr_t base; /* Base address of the CAN control registers */
uint32_t baud; /* Configured baud */
pio_pinset_t rxpinset; /* RX pin configuration */
@ -225,13 +224,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
uint32_t msr);
static inline void can_txinterrupt(FAR struct can_dev_s *dev, int mbndx);
static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx);
static void can_interrupt(FAR struct can_dev_s *dev);
#ifdef CONFIG_SAMA5_CAN0
static int can0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_CAN1
static int can1_interrupt(int irq, void *context, FAR void *arg);
#endif
static void can_interrupt(int irq, void *context, FAR void *arg);
/* Hardware initialization */
@ -265,7 +258,6 @@ static const struct sam_config_s g_can0const =
.port = 0,
.pid = SAM_PID_CAN0,
.nrecvmb = CONFIG_SAMA5_CAN0_NRECVMB,
.handler = can0_interrupt,
.base = SAM_CAN0_VBASE,
.baud = CONFIG_SAMA5_CAN0_BAUD,
.rxpinset = PIO_CAN0_RX,
@ -301,7 +293,6 @@ static const struct sam_config_s g_can1const =
.port = 1,
.pid = SAM_PID_CAN1,
.nrecvmb = CONFIG_SAMA5_CAN1_NRECVMB,
.handler = can1_interrupt,
.base = SAM_CAN1_VBASE,
.baud = CONFIG_SAMA5_CAN1_BAUD,
.rxpinset = PIO_CAN1_RX,
@ -860,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev)
/* Attach the CAN interrupt handler */
ret = irq_attach(config->pid, config->handler, NULL);
ret = irq_attach(config->pid, can_interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
@ -1437,21 +1428,24 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
* Common CAN interrupt handler
*
* Input Parameters:
* priv - CAN-specific private data
* Standard interrupt handler inputs
*
* Returned Value:
* None
*
****************************************************************************/
static void can_interrupt(FAR struct can_dev_s *dev)
static void can_interrupt(int irq, void *context, FAR void *arg)
{
FAR struct sam_can_s *priv = dev->cd_priv;
FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg;
FAR struct sam_can_s *priv;
uint32_t sr;
uint32_t imr;
uint32_t pending;
DEBUGASSERT(priv && priv->config);
DEBUGASSERT(dev != NULL);
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv != NULL && priv->config != NULL);
/* Get the set of pending interrupts.
*
@ -1520,52 +1514,6 @@ static void can_interrupt(FAR struct can_dev_s *dev)
}
}
/****************************************************************************
* Name: can0_interrupt
*
* Description:
* CAN0 interrupt handler
*
* Input Parameters:
* irq - The IRQ number of the interrupt.
* context - The register state save array at the time of the interrupt.
*
* Returned Value:
* Zero on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SAMA5_CAN0
static int can0_interrupt(int irq, void *context, FAR void *arg)
{
can_interrupt(&g_can0dev);
return OK;
}
#endif
/****************************************************************************
* Name: can0_interrupt
*
* Description:
* CAN0 interrupt handler
*
* Input Parameters:
* irq - The IRQ number of the interrupt.
* context - The register state save array at the time of the interrupt.
*
* Returned Value:
* Zero on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SAMA5_CAN1
static int can1_interrupt(int irq, void *context, FAR void *arg)
{
can_interrupt(&g_can1dev);
return OK;
}
#endif
/****************************************************************************
* Name: can_bittiming
*

31
arch/arm/src/sama5/sam_dmac.c
View File

@ -1785,12 +1785,15 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result)
*
****************************************************************************/
static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
static int sam_dmac_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_dmac_s *dmac = (struct sam_dmac_s *)arg;
struct sam_dmach_s *dmach;
unsigned int chndx;
uint32_t regval;
DEBUGASSERT(dmac != NULL);
/* Get the DMAC status register value. Ignore all masked interrupt
* status bits.
*/
@ -1849,28 +1852,6 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
return OK;
}
/****************************************************************************
* Name: sam_dmac0_interrupt and sam_dmac1_interrupt
*
* Description:
* DMA interrupt handler
*
****************************************************************************/
#ifdef CONFIG_SAMA5_DMAC0
static int sam_dmac0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_dmac_interrupt(&g_dmac0);
}
#endif
#ifdef CONFIG_SAMA5_DMAC1
static int sam_dmac1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_dmac_interrupt(&g_dmac1);
}
#endif
/****************************************************************************
* Name: sam_dmainitialize
*
@ -1928,7 +1909,7 @@ void weak_function up_dmainitialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(SAM_IRQ_DMAC0, sam_dmac0_interrupt, NULL);
(void)irq_attach(SAM_IRQ_DMAC0, sam_dmac_interrupt, &g_dmac0);
/* Initialize the controller */
@ -1948,7 +1929,7 @@ void weak_function up_dmainitialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(SAM_IRQ_DMAC1, sam_dmac1_interrupt, NULL);
(void)irq_attach(SAM_IRQ_DMAC1, sam_dmac_interrupt, &g_dmac1);
/* Initialize the controller */

51
arch/arm/src/sama5/sam_emacb.c
View File

@ -349,7 +349,6 @@ struct sam_emacattr_s
/* Basic hardware information */
uint32_t base; /* EMAC Register base address */
xcpt_t handler; /* EMAC interrupt handler */
uint8_t emac; /* EMACn, n=0 or 1 */
uint8_t irq; /* EMAC interrupt number */
@ -481,13 +480,7 @@ static void sam_receive(struct sam_emac_s *priv);
static void sam_txdone(struct sam_emac_s *priv);
static void sam_interrupt_work(FAR void *arg);
static int sam_emac_interrupt(struct sam_emac_s *priv);
#ifdef CONFIG_SAMA5_EMAC0
static int sam_emac0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_EMAC1
static int sam_emac1_interrupt(int irq, void *context, FAR void *arg);
#endif
static int sam_emac_interrupt(int irq, void *context, FAR void *arg);
/* Watchdog timer expirations */
@ -633,7 +626,6 @@ static const struct sam_emacattr_s g_emac0_attr =
/* Basic hardware information */
.base = SAM_EMAC0_VBASE,
.handler = sam_emac0_interrupt,
.emac = EMAC0_INTF,
.irq = SAM_IRQ_EMAC0,
@ -714,7 +706,6 @@ static const struct sam_emacattr_s g_emac1_attr =
/* Basic hardware information */
.base = SAM_EMAC1_VBASE,
.handler = sam_emac1_interrupt,
.emac = EMAC1_INTF,
.irq = SAM_IRQ_EMAC1,
@ -2012,7 +2003,7 @@ static void sam_interrupt_work(FAR void *arg)
* Common hardware interrupt handler
*
* Parameters:
* priv - Reference to the EMAC private state structure
* Standard interrupt handler inputs
*
* Returned Value:
* OK on success
@ -2021,10 +2012,13 @@ static void sam_interrupt_work(FAR void *arg)
*
****************************************************************************/
static int sam_emac_interrupt(struct sam_emac_s *priv)
static int sam_emac_interrupt(int irq, void *context, FAR void *arg);
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
uint32_t tsr;
DEBUGASSERT(priv != NULL);
/* Disable further Ethernet interrupts. Because Ethernet interrupts are
* also disabled if the TX timeout event occurs, there can be no race
* condition here.
@ -2084,37 +2078,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv)
return OK;
}
/****************************************************************************
* Function: sam_emac0/1_interrupt
*
* Description:
* EMAC hardware interrupt handler
*
* Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (architecture-specific)
*
* Returned Value:
* OK on success
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_SAMA5_EMAC0
static int sam_emac0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_emac_interrupt(&g_emac0);
}
#endif
#ifdef CONFIG_SAMA5_EMAC1
static int sam_emac1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_emac_interrupt(&g_emac1);
}
#endif
/****************************************************************************
* Function: sam_txtimeout_work
*
@ -4485,7 +4448,7 @@ int sam_emac_initialize(int intf)
* the interface is in the 'up' state.
*/
ret = irq_attach(priv->attr->irq, priv->attr->handler, NULL);
ret = irq_attach(priv->attr->irq, sam_emac_interrupt, priv);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);

80
arch/arm/src/sama5/sam_flexcom_serial.c
View File

@ -216,7 +216,6 @@
struct flexus_dev_s
{
xcpt_t handler; /* Interrupt handler */
uint32_t usartbase; /* Base address of USART registers */
uint32_t baud; /* Configured baud */
uint32_t sr; /* Saved status bits */
@ -233,23 +232,7 @@ struct flexus_dev_s
* Private Function Prototypes
****************************************************************************/
static int flexus_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_USART0_SERIALDRIVER
static int flexus0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART1_SERIALDRIVER
static int flexus1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART2_SERIALDRIVER
static int flexus2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART3_SERIALDRIVER
static int flexus3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART4_SERIALDRIVER
static int flexus4_interrupt(int irq, void *context, FAR void *arg);
#endif
static int flexus_interrupt(int irq, void *context, FAR void *arg);
static int flexus_setup(struct uart_dev_s *dev);
static void flexus_shutdown(struct uart_dev_s *dev);
static int flexus_attach(struct uart_dev_s *dev);
@ -314,7 +297,6 @@ static char g_flexus4txbuffer[CONFIG_USART4_TXBUFSIZE];
#ifdef CONFIG_USART0_SERIALDRIVER
static struct flexus_dev_s g_flexus0priv =
{
.handler = flexus0_interrupt,
.usartbase = SAM_FLEXCOM0_VBASE,
.baud = CONFIG_USART0_BAUD,
.irq = SAM_IRQ_FLEXCOM0,
@ -348,7 +330,6 @@ static uart_dev_t g_flexus0port =
#ifdef CONFIG_USART1_SERIALDRIVER
static struct flexus_dev_s g_flexus1priv =
{
.handler = flexus1_interrupt,
.usartbase = SAM_FLEXCOM1_VBASE,
.baud = CONFIG_USART1_BAUD,
.irq = SAM_IRQ_FLEXCOM1,
@ -382,7 +363,6 @@ static uart_dev_t g_flexus1port =
#ifdef CONFIG_USART2_SERIALDRIVER
static struct flexus_dev_s g_flexus2priv =
{
.handler = flexus2_interrupt,
.usartbase = SAM_FLEXCOM2_VBASE,
.baud = CONFIG_USART2_BAUD,
.irq = SAM_IRQ_FLEXCOM2,
@ -416,7 +396,6 @@ static uart_dev_t g_flexus2port =
#ifdef CONFIG_USART3_SERIALDRIVER
static struct flexus_dev_s g_flexus3priv =
{
.handler = flexus3_interrupt,
.usartbase = SAM_FLEXCOM3_VBASE,
.baud = CONFIG_USART3_BAUD,
.irq = SAM_IRQ_FLEXCOM3,
@ -450,7 +429,6 @@ static uart_dev_t g_flexus3port =
#ifdef CONFIG_USART4_SERIALDRIVER
static struct flexus_dev_s g_flexus4priv =
{
.handler = flexus4_interrupt,
.usartbase = SAM_FLEXCOM4_VBASE,
.baud = CONFIG_USART4_BAUD,
.irq = SAM_IRQ_FLEXCOM4,
@ -549,13 +527,14 @@ static void flexus_disableallints(struct flexus_dev_s *priv, uint32_t *imr)
*
****************************************************************************/
static int flexus_interrupt(struct uart_dev_s *dev)
static int flexus_interrupt(int irq, void *context, FAR void *arg);
{
struct flexus_dev_s *priv;
uint32_t pending;
uint32_t imr;
int passes;
bool handled;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct flexus_dev_s *priv;
uint32_t pending;
uint32_t imr;
int passes;
bool handled;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct flexus_dev_s *)dev->priv;
@ -603,47 +582,6 @@ static int flexus_interrupt(struct uart_dev_s *dev)
return OK;
}
/****************************************************************************
* Name: flexus*_interrupt
*
* Description:
* This is the specific UART/USART interrupt handler. These simply map
* the interrupt to the device-specific data and passes control to the
* common interrupt handler.
*
****************************************************************************/
#ifdef CONFIG_USART0_SERIALDRIVER
static int flexus0_interrupt(int irq, void *context, FAR void *arg)
{
return flexus_interrupt(&g_flexus0port);
}
#endif
#ifdef CONFIG_USART1_SERIALDRIVER
static int flexus1_interrupt(int irq, void *context, FAR void *arg)
{
return flexus_interrupt(&g_flexus1port);
}
#endif
#ifdef CONFIG_USART2_SERIALDRIVER
static int flexus2_interrupt(int irq, void *context, FAR void *arg)
{
return flexus_interrupt(&g_flexus2port);
}
#endif
#ifdef CONFIG_USART3_SERIALDRIVER
static int flexus3_interrupt(int irq, void *context, FAR void *arg)
{
return flexus_interrupt(&g_flexus3port);
}
#endif
#ifdef CONFIG_USART4_SERIALDRIVER
static int flexus4_interrupt(int irq, void *context, FAR void *arg)
{
return flexus_interrupt(&g_flexus4port);
}
#endif
/****************************************************************************
* Name: flexus_setup
*
@ -803,7 +741,7 @@ static int flexus_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, flexus_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled

76
arch/arm/src/sama5/sam_hsmci.c
View File

@ -436,17 +436,17 @@ struct sam_dev_s
/* Debug stuff */
#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG
bool wrlast; /* Last was a write */
uint32_t addrlast; /* Last address */
uint32_t vallast; /* Last value */
int ntimes; /* Number of times */
bool wrlast; /* Last was a write */
uint32_t addrlast; /* Last address */
uint32_t vallast; /* Last value */
int ntimes; /* Number of times */
#endif
/* Register logging support */
#if defined(CONFIG_SAMA5_HSMCI_CMDDEBUG) && defined(CONFIG_SAMA5_HSMCI_XFRDEBUG)
bool xfrinitialized;
bool cmdinitialized;
bool xfrinitialized;
bool cmdinitialized;
#endif
#ifdef CONFIG_SAMA5_HSMCI_XFRDEBUG
uint8_t smplset;
@ -537,16 +537,7 @@ static void sam_notransfer(struct sam_dev_s *priv);
/* Interrupt Handling *******************************************************/
static int sam_hsmci_interrupt(struct sam_dev_s *priv);
#ifdef CONFIG_SAMA5_HSMCI0
static int sam_hsmci0_interrupt(int irq, void *context, void *arg);
#endif
#ifdef CONFIG_SAMA5_HSMCI1
static int sam_hsmci1_interrupt(int irq, void *context, void *arg);
#endif
#ifdef CONFIG_SAMA5_HSMCI2
static int sam_hsmci2_interrupt(int irq, void *context, void *arg);
#endif
static int sam_hsmci_interrupt(int irq, void *context, void *arg);
/* SDIO interface methods ***************************************************/
@ -1512,12 +1503,15 @@ static void sam_notransfer(struct sam_dev_s *priv)
*
****************************************************************************/
static int sam_hsmci_interrupt(struct sam_dev_s *priv)
static int sam_hsmci_interrupt(int irq, void *context, void *arg)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
uint32_t sr;
uint32_t enabled;
uint32_t pending;
DEBUGASSERT(priv != NULL);
/* Loop while there are pending interrupts. */
for (; ; )
@ -1661,42 +1655,6 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
return OK;
}
/****************************************************************************
* Name: sam_hsmci0_interrupt, sam_hsmci1_interrupt, and sam_hsmci2_interrupt
*
* Description:
* HSMCI interrupt handler
*
* Input Parameters:
* irq - IRQ number of the interrupts
* context - Saved machine context at the time of the interrupt
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SAMA5_HSMCI0
static int sam_hsmci0_interrupt(int irq, void *context, void *arg)
{
return sam_hsmci_interrupt(&g_hsmci0);
}
#endif
#ifdef CONFIG_SAMA5_HSMCI1
static int sam_hsmci1_interrupt(int irq, void *context, void *arg)
{
return sam_hsmci_interrupt(&g_hsmci1);
}
#endif
#ifdef CONFIG_SAMA5_HSMCI2
static int sam_hsmci2_interrupt(int irq, void *context, void *arg)
{
return sam_hsmci_interrupt(&g_hsmci2);
}
#endif
/****************************************************************************
* SDIO Interface Methods
****************************************************************************/
@ -1947,7 +1905,6 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
static int sam_attach(FAR struct sdio_dev_s *dev)
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
xcpt_t handler;
int irq;
int ret;
@ -1956,24 +1913,21 @@ static int sam_attach(FAR struct sdio_dev_s *dev)
#ifdef CONFIG_SAMA5_HSMCI0
if (priv->hsmci == 0)
{
handler = sam_hsmci0_interrupt;
irq = SAM_IRQ_HSMCI0;
irq = SAM_IRQ_HSMCI0;
}
else
#endif
#ifdef CONFIG_SAMA5_HSMCI1
if (priv->hsmci == 1)
{
handler = sam_hsmci1_interrupt;
irq = SAM_IRQ_HSMCI1;
irq = SAM_IRQ_HSMCI1;
}
else
#endif
#ifdef CONFIG_SAMA5_HSMCI2
if (priv->hsmci == 2)
{
handler = sam_hsmci2_interrupt;
irq = SAM_IRQ_HSMCI2;
irq = SAM_IRQ_HSMCI2;
}
else
#endif
@ -1984,7 +1938,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev)
/* Attach the HSMCI interrupt handler */
ret = irq_attach(irq, handler, priv);
ret = irq_attach(irq, sam_hsmci_interrupt, priv);
if (ret == OK)
{

110
arch/arm/src/sama5/sam_serial.c
View File

@ -418,7 +418,6 @@
struct up_dev_s
{
xcpt_t handler; /* Interrupt handler */
uint32_t usartbase; /* Base address of USART registers */
uint32_t baud; /* Configured baud */
uint32_t sr; /* Saved status bits */
@ -435,38 +434,7 @@ struct up_dev_s
* Private Function Prototypes
****************************************************************************/
static int up_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_SAMA5_UART0
static int up_uart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_UART1
static int up_uart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_UART2
static int up_uart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_UART3
static int up_uart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMA5_UART4
static int up_uart4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART0_SERIALDRIVER
static int up_usart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART1_SERIALDRIVER
static int up_usart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART2_SERIALDRIVER
static int up_usart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART3_SERIALDRIVER
static int up_usart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_USART4_SERIALDRIVER
static int up_usart4_interrupt(int irq, void *context, FAR void *arg);
#endif
static int up_interrupt(int irq, void *context, FAR void *arg);
static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
@ -561,7 +529,6 @@ static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
static struct up_dev_s g_uart0priv =
{
.handler = up_uart0_interrupt,
.usartbase = SAM_UART0_VBASE,
.baud = CONFIG_UART0_BAUD,
.irq = SAM_IRQ_UART0,
@ -602,7 +569,6 @@ static uart_dev_t g_uart0port =
static struct up_dev_s g_uart1priv =
{
.handler = up_uart1_interrupt,
.usartbase = SAM_UART1_VBASE,
.baud = CONFIG_UART1_BAUD,
.irq = SAM_IRQ_UART1,
@ -643,7 +609,6 @@ static uart_dev_t g_uart1port =
static struct up_dev_s g_uart2priv =
{
.handler = up_uart2_interrupt,
.usartbase = SAM_UART2_VBASE,
.baud = CONFIG_UART2_BAUD,
.irq = SAM_IRQ_UART2,
@ -684,7 +649,6 @@ static uart_dev_t g_uart2port =
static struct up_dev_s g_uart3priv =
{
.handler = up_uart3_interrupt,
.usartbase = SAM_UART3_VBASE,
.baud = CONFIG_UART3_BAUD,
.irq = SAM_IRQ_UART3,
@ -725,7 +689,6 @@ static uart_dev_t g_uart3port =
static struct up_dev_s g_uart4priv =
{
.handler = up_uart4_interrupt,
.usartbase = SAM_UART4_VBASE,
.baud = CONFIG_UART4_BAUD,
.irq = SAM_IRQ_UART4,
@ -756,7 +719,6 @@ static uart_dev_t g_uart4port =
#ifdef CONFIG_USART0_SERIALDRIVER
static struct up_dev_s g_usart0priv =
{
.handler = up_usart0_interrupt,
.usartbase = SAM_USART0_VBASE,
.baud = CONFIG_USART0_BAUD,
.irq = SAM_IRQ_USART0,
@ -790,7 +752,6 @@ static uart_dev_t g_usart0port =
#ifdef CONFIG_USART1_SERIALDRIVER
static struct up_dev_s g_usart1priv =
{
.handler = up_usart1_interrupt,
.usartbase = SAM_USART1_VBASE,
.baud = CONFIG_USART1_BAUD,
.irq = SAM_IRQ_USART1,
@ -824,7 +785,6 @@ static uart_dev_t g_usart1port =
#ifdef CONFIG_USART2_SERIALDRIVER
static struct up_dev_s g_usart2priv =
{
.handler = up_usart2_interrupt,
.usartbase = SAM_USART2_VBASE,
.baud = CONFIG_USART2_BAUD,
.irq = SAM_IRQ_USART2,
@ -858,7 +818,6 @@ static uart_dev_t g_usart2port =
#ifdef CONFIG_USART3_SERIALDRIVER
static struct up_dev_s g_usart3priv =
{
.handler = up_usart3_interrupt,
.usartbase = SAM_USART3_VBASE,
.baud = CONFIG_USART3_BAUD,
.irq = SAM_IRQ_USART3,
@ -892,7 +851,6 @@ static uart_dev_t g_usart3port =
#ifdef CONFIG_USART4_SERIALDRIVER
static struct up_dev_s g_usart4priv =
{
.handler = up_usart4_interrupt,
.usartbase = SAM_USART4_VBASE,
.baud = CONFIG_USART4_BAUD,
.irq = SAM_IRQ_USART4,
@ -989,8 +947,9 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr)
*
****************************************************************************/
static int up_interrupt(struct uart_dev_s *dev)
static int up_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
uint32_t pending;
uint32_t imr;
@ -1043,67 +1002,6 @@ static int up_interrupt(struct uart_dev_s *dev)
return OK;
}
#ifdef CONFIG_SAMA5_UART0
static int up_uart0_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_uart0port);
}
#endif
#ifdef CONFIG_SAMA5_UART1
static int up_uart1_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_uart1port);
}
#endif
#ifdef CONFIG_SAMA5_UART2
static int up_uart2_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_uart2port);
}
#endif
#ifdef CONFIG_SAMA5_UART3
static int up_uart3_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_uart3port);
}
#endif
#ifdef CONFIG_SAMA5_UART4
static int up_uart4_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_uart4port);
}
#endif
#ifdef CONFIG_USART0_SERIALDRIVER
static int up_usart0_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_usart0port);
}
#endif
#ifdef CONFIG_USART1_SERIALDRIVER
static int up_usart1_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_usart1port);
}
#endif
#ifdef CONFIG_USART2_SERIALDRIVER
static int up_usart2_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_usart2port);
}
#endif
#ifdef CONFIG_USART3_SERIALDRIVER
static int up_usart3_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_usart3port);
}
#endif
#ifdef CONFIG_USART4_SERIALDRIVER
static int up_usart4_interrupt(int irq, void *context, FAR void *arg)
{
return up_interrupt(&g_usart4port);
}
#endif
/****************************************************************************
* Name: up_setup
*
@ -1294,7 +1192,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled

55
arch/arm/src/sama5/sam_twi.c
View File

@ -199,21 +199,9 @@ static inline void twi_putrel(struct twi_dev_s *priv, unsigned int offset,
/* I2C transfer helper functions */
static int twi_wait(struct twi_dev_s *priv, unsigned int size);
static int twi_wait(struct twi_dev_s *priv, unsigned int size);
static void twi_wakeup(struct twi_dev_s *priv, int result);
static int twi_interrupt(struct twi_dev_s *priv);
#ifdef CONFIG_SAMA5_TWI0
static int twi0_interrupt(int irq, FAR void *context, FAR void * arg);
#endif
#ifdef CONFIG_SAMA5_TWI1
static int twi1_interrupt(int irq, FAR void *context, FAR void * arg);
#endif
#ifdef CONFIG_SAMA5_TWI2
static int twi2_interrupt(int irq, FAR void *context, FAR void * arg);
#endif
#ifdef CONFIG_SAMA5_TWI3
static int twi3_interrupt(int irq, FAR void *context, FAR void * arg);
#endif
static int twi_interrupt(int irq, FAR void *context, FAR void * arg);
static void twi_timeout(int argc, uint32_t arg, ...);
static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg);
@ -246,7 +234,6 @@ static const struct twi_attr_s g_twi0attr =
.sclcfg = PIO_TWI0_CK,
.sdacfg = PIO_TWI0_D,
.base = SAM_TWI0_VBASE,
.handler = twi0_interrupt,
};
static struct twi_dev_s g_twi0;
@ -261,7 +248,6 @@ static const struct twi_attr_s g_twi1attr =
.sclcfg = PIO_TWI1_CK,
.sdacfg = PIO_TWI1_D,
.base = SAM_TWI1_VBASE,
.handler = twi1_interrupt,
};
static struct twi_dev_s g_twi1;
@ -276,7 +262,6 @@ static const struct twi_attr_s g_twi2attr =
.sclcfg = PIO_TWI2_CK,
.sdacfg = PIO_TWI2_D,
.base = SAM_TWI2_VBASE,
.handler = twi2_interrupt,
};
static struct twi_dev_s g_twi2;
@ -291,7 +276,6 @@ static const struct twi_attr_s g_twi3attr =
.sclcfg = PIO_TWI3_CK,
.sdacfg = PIO_TWI3_D,
.base = SAM_TWI3_VBASE,
.handler = twi3_interrupt,
};
static struct twi_dev_s g_twi3;
@ -550,14 +534,17 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
*
****************************************************************************/
static int twi_interrupt(struct twi_dev_s *priv)
static int twi_interrupt(int irq, FAR void *context, FAR void * arg)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
struct i2c_msg_s *msg;
uint32_t sr;
uint32_t imr;
uint32_t pending;
uint32_t regval;
DEBUGASSERT(priv != NULL);
/* Retrieve masked interrupt status */
sr = twi_getrel(priv, SAM_TWI_SR_OFFSET);
@ -667,34 +654,6 @@ static int twi_interrupt(struct twi_dev_s *priv)
return OK;
}
#ifdef CONFIG_SAMA5_TWI0
static int twi0_interrupt(int irq, FAR void *context, FAR void * arg)
{
return twi_interrupt(&g_twi0);
}
#endif
#ifdef CONFIG_SAMA5_TWI1
static int twi1_interrupt(int irq, FAR void *context, FAR void * arg)
{
return twi_interrupt(&g_twi1);
}
#endif
#ifdef CONFIG_SAMA5_TWI2
static int twi2_interrupt(int irq, FAR void *context, FAR void * arg)
{
return twi_interrupt(&g_twi2);
}
#endif
#ifdef CONFIG_SAMA5_TWI3
static int twi3_interrupt(int irq, FAR void *context, FAR void * arg)
{
return twi_interrupt(&g_twi3);
}
#endif
/****************************************************************************
* Name: twi_timeout
*
@ -1296,7 +1255,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Attach Interrupt Handler */
ret = irq_attach(priv->attr->irq, priv->attr->handler, NULL);
ret = irq_attach(priv->attr->irq, twi_interrupt, priv);
if (ret < 0)
{
ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq);

31
arch/arm/src/sama5/sam_xdmac.c
View File

@ -1825,14 +1825,17 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result)
*
****************************************************************************/
static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
static int sam_xdmac_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_xdmac_s *xdmac = (struct sam_xdmac_s *)arg;
struct sam_xdmach_s *xdmach;
unsigned int chndx;
uint32_t gpending;
uint32_t chpending;
uint32_t bit;
DEBUGASSERT(xdmac != NULL);
/* Get the set of pending, unmasked global XDMAC interrupts */
gpending = sam_getdmac(xdmac, SAM_XDMAC_GIS_OFFSET) &
@ -1890,28 +1893,6 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
return OK;
}
/****************************************************************************
* Name: sam_xdmac0_interrupt and sam_xdmac1_interrupt
*
* Description:
* DMA interrupt handler
*
****************************************************************************/
#ifdef CONFIG_SAMA5_XDMAC0
static int sam_xdmac0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_xdmac_interrupt(&g_xdmac0);
}
#endif
#ifdef CONFIG_SAMA5_XDMAC1
static int sam_xdmac1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_xdmac_interrupt(&g_xdmac1);
}
#endif
/****************************************************************************
* Name: sam_dmainitialize
*
@ -1965,7 +1946,7 @@ void weak_function up_dmainitialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(SAM_IRQ_XDMAC0, sam_xdmac0_interrupt, NULL);
(void)irq_attach(SAM_IRQ_XDMAC0, sam_xdmac_interrupt, &g_xdmac0);
/* Initialize the controller */
@ -1985,7 +1966,7 @@ void weak_function up_dmainitialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(SAM_IRQ_XDMAC1, sam_xdmac1_interrupt, NULL);
(void)irq_attach(SAM_IRQ_XDMAC1, sam_xdmac_interrupt, &g_xdmac1);
/* Initialize the controller */

90
arch/arm/src/samdl/sam_serial.c
View File

@ -228,8 +228,6 @@ struct sam_dev_s
const struct sam_usart_config_s * const config;
/* Information unique to the serial driver */
xcpt_t handler; /* Interrupt handler */
};
/****************************************************************************
@ -249,26 +247,7 @@ static inline void
sam_serialout16(struct sam_dev_s *priv, int offset,
uint16_t regval);
static void sam_disableallints(struct sam_dev_s *priv);
static int sam_interrupt(struct uart_dev_s *dev);
#ifdef SAMDL_HAVE_USART0
static int sam_usart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_USART1
static int sam_usart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_USART2
static int sam_usart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_USART3
static int sam_usart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_USART4
static int sam_usart4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_USART5
static int sam_usart5_interrupt(int irq, void *context, FAR void *arg);
#endif
static int sam_interrupt(int irq, void *context, FAR void *arg);
/* UART methods */
@ -340,7 +319,6 @@ static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
static struct sam_dev_s g_usart0priv =
{
.config = &g_usart0config,
.handler = sam_usart0_interrupt,
};
static uart_dev_t g_usart0port =
@ -366,7 +344,6 @@ static uart_dev_t g_usart0port =
static struct sam_dev_s g_usart1priv =
{
.config = &g_usart1config,
.handler = sam_usart1_interrupt,
};
static uart_dev_t g_usart1port =
@ -392,7 +369,6 @@ static uart_dev_t g_usart1port =
static struct sam_dev_s g_usart2priv =
{
.config = &g_usart2config,
.handler = sam_usart2_interrupt,
};
static uart_dev_t g_usart2port =
@ -418,7 +394,6 @@ static uart_dev_t g_usart2port =
static struct sam_dev_s g_usart3priv =
{
.config = &g_usart3config,
.handler = sam_usart3_interrupt,
};
static uart_dev_t g_usart3port =
@ -444,7 +419,6 @@ static uart_dev_t g_usart3port =
static struct sam_dev_s g_usart4priv =
{
.config = &g_usart4config,
.handler = sam_usart4_interrupt,
};
static uart_dev_t g_usart4port =
@ -470,7 +444,6 @@ static uart_dev_t g_usart4port =
static struct sam_dev_s g_usart5priv =
{
.config = &g_usart5config,
.handler = sam_usart5_interrupt,
};
static uart_dev_t g_usart5port =
@ -555,13 +528,17 @@ static void sam_disableallints(struct sam_dev_s *priv)
*
****************************************************************************/
static int sam_interrupt(struct uart_dev_s *dev)
static int sam_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s )arg;
struct sam_dev_s *priv;
uint8_t pending;
uint8_t intflag;
uint8_t inten;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct sam_dev_s *)dev->priv;
/* Get the set of pending USART interrupts (we are only interested in the
* unmasked interrupts).
*/
@ -599,57 +576,6 @@ static int sam_interrupt(struct uart_dev_s *dev)
return OK;
}
/****************************************************************************
* Name: sam_usartN_interrupt
*
* Description:
* Handle each SERCOM USART interrupt by calling the common interrupt
* handling logic with the USART-specific state.
*
****************************************************************************/
#ifdef SAMDL_HAVE_USART0
static int sam_usart0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart0port);
}
#endif
#ifdef SAMDL_HAVE_USART1
static int sam_usart1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart1port);
}
#endif
#ifdef SAMDL_HAVE_USART2
static int sam_usart2_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart2port);
}
#endif
#ifdef SAMDL_HAVE_USART3
static int sam_usart3_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart3port);
}
#endif
#ifdef SAMDL_HAVE_USART4
static int sam_usart4_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart4port);
}
#endif
#ifdef SAMDL_HAVE_USART5
static int sam_usart5_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart5port);
}
#endif
/****************************************************************************
* Name: sam_setup
*
@ -726,7 +652,7 @@ static int sam_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(config->irq, priv->handler, NULL);
ret = irq_attach(config->irq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled

100
arch/arm/src/samdl/sam_spi.c
View File

@ -163,26 +163,7 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
/* Interrupt handling */
#if 0 /* Not used */
static int spi_interrupt(struct sam_spidev_s *dev);
#ifdef SAMDL_HAVE_SPI0
static int spi0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_SPI1
static int spi1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_SPI2
static int spi2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_SPI3
static int spi3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_SPI4
static int spi4_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef SAMDL_HAVE_SPI5
static int spi5_interrupt(int irq, void *context, FAR void *arg);
#endif
static int spi_interrupt(int irq, void *context, FAR void *arg);
#endif
/* SPI methods */
@ -255,9 +236,6 @@ static struct sam_spidev_s g_spi0dev =
.muxconfig = BOARD_SERCOM0_MUXCONFIG,
.srcfreq = BOARD_SERCOM0_FREQUENCY,
.base = SAM_SERCOM0_BASE,
#if 0 /* Not used */
.handler = spi0_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -304,9 +282,6 @@ static struct sam_spidev_s g_spi1dev =
.muxconfig = BOARD_SERCOM1_MUXCONFIG,
.srcfreq = BOARD_SERCOM1_FREQUENCY,
.base = SAM_SERCOM1_BASE,
#if 0 /* Not used */
.handler = spi1_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -353,9 +328,6 @@ static struct sam_spidev_s g_spi2dev =
.muxconfig = BOARD_SERCOM2_MUXCONFIG,
.srcfreq = BOARD_SERCOM2_FREQUENCY,
.base = SAM_SERCOM2_BASE,
#if 0 /* Not used */
.handler = spi2_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -402,9 +374,6 @@ static struct sam_spidev_s g_spi3dev =
.muxconfig = BOARD_SERCOM3_MUXCONFIG,
.srcfreq = BOARD_SERCOM3_FREQUENCY,
.base = SAM_SERCOM3_BASE,
#if 0 /* Not used */
.handler = spi3_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -451,9 +420,6 @@ static struct sam_spidev_s g_spi4dev =
.muxconfig = BOARD_SERCOM4_MUXCONFIG,
.srcfreq = BOARD_SERCOM4_FREQUENCY,
.base = SAM_SERCOM4_BASE,
#if 0 /* Not used */
.handler = spi4_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -500,9 +466,6 @@ static struct sam_spidev_s g_spi5dev =
.muxconfig = BOARD_SERCOM5_MUXCONFIG,
.srcfreq = BOARD_SERCOM5_FREQUENCY,
.base = SAM_SERCOM5_BASE,
#if 0 /* Not used */
.handler = spi5_interrupt,
#endif
.spilock = SEM_INITIALIZER(1),
};
#endif
@ -748,13 +711,15 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg)
****************************************************************************/
#if 0 /* Not used */
static int spi_interrupt(struct sam_spidev_s *dev)
static int spi_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;
struct sam_dev_s *priv = (struct sam_dev_s *)arg
uint8_t pending;
uint8_t intflag;
uint8_t inten;
DEBUGASSERT(priv != NULL);
/* Get the set of pending SPI interrupts (we are only interested in the
* unmasked interrupts).
*/
@ -791,59 +756,6 @@ static int spi_interrupt(struct sam_spidev_s *dev)
}
#endif
/****************************************************************************
* Name: spiN_interrupt
*
* Description:
* Handle each SERCOM SPI interrupt by calling the common interrupt
* handling logic with the SPI-specific state.
*
****************************************************************************/
#if 0 /* Not used */
#ifdef SAMDL_HAVE_SPI0
static int spi0_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi0dev);
}
#endif
#ifdef SAMDL_HAVE_SPI1
static int spi1_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi1dev);
}
#endif
#ifdef SAMDL_HAVE_SPI2
static int spi2_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi2dev);
}
#endif
#ifdef SAMDL_HAVE_SPI3
static int spi3_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi3dev);
}
#endif
#ifdef SAMDL_HAVE_SPI4
static int spi4_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi4dev);
}
#endif
#ifdef SAMDL_HAVE_SPI5
static int spi5_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi5dev);
}
#endif
#endif
/****************************************************************************
* Name: spi_lock
*
@ -1546,7 +1458,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
#if 0 /* Not used */
/* Attach and enable the SERCOM interrupt handler */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, spi_interrupt, priv);
if (ret < 0)
{
spierr("ERROR: Failed to attach interrupt: %d\n", irq);

52
arch/arm/src/samv7/sam_emac.c
View File

@ -431,7 +431,6 @@ struct sam_emacattr_s
/* Basic hardware information */
uint32_t base; /* EMAC Register base address */
xcpt_t handler; /* EMAC interrupt handler */
uint8_t emac; /* EMACn, n=0 or 1 */
uint8_t irq; /* EMAC interrupt number */
@ -583,13 +582,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid);
static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid);
static void sam_interrupt_work(FAR void *arg);
static int sam_emac_interrupt(struct sam_emac_s *priv);
#ifdef CONFIG_SAMV7_EMAC0
static int sam_emac0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_EMAC1
static int sam_emac1_interrupt(int irq, void *context, FAR void *arg);
#endif
static int sam_emac_interrupt(int irq, void *context, FAR void *arg);
/* Watchdog timer expirations */
@ -778,7 +771,6 @@ static const struct sam_emacattr_s g_emac0_attr =
/* Basic hardware information */
.base = SAM_EMAC0_BASE,
.handler = sam_emac0_interrupt,
.emac = EMAC0_INTF,
.irq = SAM_IRQ_EMAC0,
@ -859,7 +851,6 @@ static const struct sam_emacattr_s g_emac1_attr =
/* Basic hardware information */
.base = SAM_EMAC1_BASE,
.handler = sam_emac1_interrupt,
.emac = EMAC1_INTF,
.irq = SAM_IRQ_EMAC1,
@ -2467,10 +2458,13 @@ static void sam_interrupt_work(FAR void *arg)
*
****************************************************************************/
static int sam_emac_interrupt(struct sam_emac_s *priv)
static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
uint32_t tsr;
DEBUGASSERT(priv != NULL);
/* Disable further Ethernet interrupts. Because Ethernet interrupts are
* also disabled if the TX timeout event occurs, there can be no race
* condition here.
@ -2530,37 +2524,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv)
return OK;
}
/****************************************************************************
* Function: sam_emac0/1_interrupt
*
* Description:
* EMAC hardware interrupt handler
*
* Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (architecture-specific)
*
* Returned Value:
* OK on success
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_SAMV7_EMAC0
static int sam_emac0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_emac_interrupt(&g_emac0);
}
#endif
#ifdef CONFIG_SAMV7_EMAC1
static int sam_emac1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_emac_interrupt(&g_emac1);
}
#endif
/****************************************************************************
* Function: sam_txtimeout_work
*
@ -5052,10 +5015,11 @@ int sam_emac_initialize(int intf)
* the interface is in the 'up' state.
*/
ret = irq_attach(priv->attr->irq, priv->attr->handler, NULL);
ret = irq_attach(priv->attr->irq, sam_emac_interrupt, priv);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
priv->attr->irq);
goto errout_with_buffers;
}

54
arch/arm/src/samv7/sam_hsmci.c
View File

@ -472,13 +472,7 @@ static void sam_notransfer(struct sam_dev_s *priv);
/* Interrupt Handling *******************************************************/
static int sam_hsmci_interrupt(struct sam_dev_s *priv);
#ifdef CONFIG_SAMV7_HSMCI0
static int sam_hsmci0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_HSMCI1
static int sam_hsmci1_interrupt(int irq, void *context);
#endif
static int sam_hsmci_interrupt(int irq, void *context, void *arg);
/* SDIO interface methods ***************************************************/
@ -1437,20 +1431,22 @@ static void sam_notransfer(struct sam_dev_s *priv)
* HSMCI interrupt handler
*
* Input Parameters:
* irq - IRQ number of the interrupts
* context - Saved machine context at the time of the interrupt
* Standard interrupt handler arguments.
*
* Returned Value:
* None
*
****************************************************************************/
static int sam_hsmci_interrupt(struct sam_dev_s *priv)
static int sam_hsmci_interrupt(int irq, void *context, void *arg)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
uint32_t sr;
uint32_t enabled;
uint32_t pending;
DEBUGASSERT(priv != NULL);
/* Loop while there are pending interrupts. */
for (; ; )
@ -1643,35 +1639,6 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
return OK;
}
/****************************************************************************
* Name: sam_hsmci0_interrupt, sam_hsmci1_interrupt, and sam_hsmci2_interrupt
*
* Description:
* HSMCI interrupt handler
*
* Input Parameters:
* irq - IRQ number of the interrupts
* context - Saved machine context at the time of the interrupt
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SAMV7_HSMCI0
static int sam_hsmci0_interrupt(int irq, void *context)
{
return sam_hsmci_interrupt(&g_hsmci0);
}
#endif
#ifdef CONFIG_SAMV7_HSMCI1
static int sam_hsmci1_interrupt(int irq, void *context)
{
return sam_hsmci_interrupt(&g_hsmci1);
}
#endif
/****************************************************************************
* SDIO Interface Methods
****************************************************************************/
@ -1922,7 +1889,6 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
static int sam_attach(FAR struct sdio_dev_s *dev)
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
xcpt_t handler;
int irq;
int ret;
@ -1931,16 +1897,14 @@ static int sam_attach(FAR struct sdio_dev_s *dev)
#ifdef CONFIG_SAMV7_HSMCI0
if (priv->hsmci == 0)
{
handler = sam_hsmci0_interrupt;
irq = SAM_IRQ_HSMCI0;
irq = SAM_IRQ_HSMCI0;
}
else
#endif
#ifdef CONFIG_SAMV7_HSMCI1
if (priv->hsmci == 1)
{
handler = sam_hsmci1_interrupt;
irq = SAM_IRQ_HSMCI1;
irq = SAM_IRQ_HSMCI1;
}
else
#endif
@ -1951,7 +1915,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev)
/* Attach the HSMCI interrupt handler */
ret = irq_attach(irq, handler, NULL);
ret = irq_attach(irq, sam_hsmci_interrupt, priv);
if (ret == OK)
{

68
arch/arm/src/samv7/sam_mcan.c
View File

@ -841,7 +841,6 @@ struct sam_config_s
{
gpio_pinset_t rxpinset; /* RX pin configuration */
gpio_pinset_t txpinset; /* TX pin configuration */
xcpt_t handler; /* MCAN common interrupt handler */
uintptr_t base; /* Base address of the MCAN registers */
uint32_t baud; /* Configured baud */
uint32_t btp; /* Bit timing/prescaler register setting */
@ -973,13 +972,7 @@ static void mcan_error(FAR struct can_dev_s *dev, uint32_t status,
#endif
static void mcan_receive(FAR struct can_dev_s *dev,
FAR uint32_t *rxbuffer, unsigned long nwords);
static void mcan_interrupt(FAR struct can_dev_s *dev);
#ifdef CONFIG_SAMV7_MCAN0
static int mcan0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_MCAN1
static int mcan1_interrupt(int irq, void *context, FAR void *arg);
#endif
static int mcan_interrupt(int irq, void *context, FAR void *arg);
/* Hardware initialization */
@ -1019,7 +1012,6 @@ static const struct sam_config_s g_mcan0const =
{
.rxpinset = GPIO_MCAN0_RX,
.txpinset = GPIO_MCAN0_TX,
.handler = mcan0_interrupt,
.base = SAM_MCAN0_BASE,
.baud = CONFIG_SAMV7_MCAN0_BITRATE,
.btp = MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) |
@ -1096,7 +1088,6 @@ static const struct sam_config_s g_mcan1const =
{
.rxpinset = GPIO_MCAN1_RX,
.txpinset = GPIO_MCAN1_TX,
.handler = mcan1_interrupt,
.base = SAM_MCAN1_BASE,
.baud = CONFIG_SAMV7_MCAN1_BITRATE,
.btp = MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) |
@ -2340,7 +2331,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
/* Attach the MCAN interrupt handlers */
ret = irq_attach(config->irq0, config->handler, NULL);
ret = irq_attach(config->irq0, mcan_interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
@ -2348,7 +2339,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
return ret;
}
ret = irq_attach(config->irq1, config->handler, NULL);
ret = irq_attach(config->irq1, mcan_interrupt, dev);
if (ret < 0)
{
canerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
@ -3378,9 +3369,10 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
*
****************************************************************************/
static void mcan_interrupt(FAR struct can_dev_s *dev)
static int mcan_interrupt(int irq, void *context, FAR void *arg)
{
FAR struct sam_mcan_s *priv = dev->cd_priv;
FAR struct can_dev_s *dev = (FAR struct can_dev_s *)arg;
FAR struct sam_mcan_s *priv;
FAR const struct sam_config_s *config;
uint32_t ir;
uint32_t ie;
@ -3390,6 +3382,8 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
unsigned int ndx;
bool handled;
DEBUGASSERT(dev != NULL);
priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
config = priv->config;
@ -3675,52 +3669,6 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
while (handled);
}
/****************************************************************************
* Name: mcan0_interrupt
*
* Description:
* MCAN0 interrupt handler
*
* Input Parameters:
* irq - The IRQ number of the interrupt.
* context - The register state save array at the time of the interrupt.
*
* Returned Value:
* Zero on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SAMV7_MCAN0
static int mcan0_interrupt(int irq, void *context, FAR void *arg)
{
mcan_interrupt(&g_mcan0dev);
return OK;
}
#endif
/****************************************************************************
* Name: mcan1_interrupt
*
* Description:
* MCAN1 interrupt handler
*
* Input Parameters:
* irq - The IRQ number of the interrupt.
* context - The register state save array at the time of the interrupt.
*
* Returned Value:
* Zero on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SAMV7_MCAN1
static int mcan1_interrupt(int irq, void *context, FAR void *arg)
{
mcan_interrupt(&g_mcan1dev);
return OK;
}
#endif
/****************************************************************************
* Name: mcan_hw_initialize
*

116
arch/arm/src/samv7/sam_serial.c
View File

@ -333,7 +333,6 @@
struct sam_dev_s
{
const uint32_t usartbase; /* Base address of USART registers */
xcpt_t handler; /* Interrupt handler */
uint32_t baud; /* Configured baud */
uint32_t sr; /* Saved status bits */
uint8_t irq; /* IRQ associated with this USART */
@ -353,31 +352,7 @@ static int sam_setup(struct uart_dev_s *dev);
static void sam_shutdown(struct uart_dev_s *dev);
static int sam_attach(struct uart_dev_s *dev);
static void sam_detach(struct uart_dev_s *dev);
static int sam_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_SAMV7_UART0
static int sam_uart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_UART1
static int sam_uart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_UART2
static int sam_uart2_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_UART3
static int sam_uart3_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_UART4
static int sam_uart4_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_SERIALDRIVER)
static int sam_usart0_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_SERIALDRIVER)
static int sam_usart1_interrupt(int irq, void *context, FAR void *arg);
#endif
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_SERIALDRIVER)
static int sam_usart2_interrupt(int irq, void *context, FAR void *arg);
#endif
static int sam_interrupt(int irq, void *context, FAR void *arg);
static int sam_ioctl(struct file *filep, int cmd, unsigned long arg);
static int sam_receive(struct uart_dev_s *dev, uint32_t *status);
static void sam_rxint(struct uart_dev_s *dev, bool enable);
@ -451,7 +426,6 @@ static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
static struct sam_dev_s g_uart0priv =
{
.usartbase = SAM_UART0_BASE,
.handler = sam_uart0_interrupt,
.baud = CONFIG_UART0_BAUD,
.irq = SAM_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
@ -482,7 +456,6 @@ static uart_dev_t g_uart0port =
static struct sam_dev_s g_uart1priv =
{
.usartbase = SAM_UART1_BASE,
.handler = sam_uart1_interrupt,
.baud = CONFIG_UART1_BAUD,
.irq = SAM_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
@ -513,7 +486,6 @@ static uart_dev_t g_uart1port =
static struct sam_dev_s g_uart2priv =
{
.usartbase = SAM_UART2_BASE,
.handler = sam_uart2_interrupt,
.baud = CONFIG_UART2_BAUD,
.irq = SAM_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
@ -544,7 +516,6 @@ static uart_dev_t g_uart2port =
static struct sam_dev_s g_uart3priv =
{
.usartbase = SAM_UART3_BASE,
.handler = sam_uart3_interrupt,
.baud = CONFIG_UART3_BAUD,
.irq = SAM_IRQ_UART3,
.parity = CONFIG_UART3_PARITY,
@ -575,7 +546,6 @@ static uart_dev_t g_uart3port =
static struct sam_dev_s g_uart4priv =
{
.usartbase = SAM_UART4_BASE,
.handler = sam_uart4_interrupt,
.baud = CONFIG_UART4_BAUD,
.irq = SAM_IRQ_UART4,
.parity = CONFIG_UART4_PARITY,
@ -606,7 +576,6 @@ static uart_dev_t g_uart4port =
static struct sam_dev_s g_usart0priv =
{
.usartbase = SAM_USART0_BASE,
.handler = sam_usart0_interrupt,
.baud = CONFIG_USART0_BAUD,
.irq = SAM_IRQ_USART0,
.parity = CONFIG_USART0_PARITY,
@ -640,7 +609,6 @@ static uart_dev_t g_usart0port =
static struct sam_dev_s g_usart1priv =
{
.usartbase = SAM_USART1_BASE,
.handler = sam_usart1_interrupt,
.baud = CONFIG_USART1_BAUD,
.irq = SAM_IRQ_USART1,
.parity = CONFIG_USART1_PARITY,
@ -674,7 +642,6 @@ static uart_dev_t g_usart1port =
static struct sam_dev_s g_usart2priv =
{
.usartbase = SAM_USART2_BASE,
.handler = sam_usart2_interrupt,
.baud = CONFIG_USART2_BAUD,
.irq = SAM_IRQ_USART2,
.parity = CONFIG_USART2_PARITY,
@ -973,7 +940,7 @@ static int sam_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, priv->handler, NULL);
ret = irq_attach(priv->irq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -1014,15 +981,16 @@ static void sam_detach(struct uart_dev_s *dev)
*
****************************************************************************/
static int sam_interrupt(struct uart_dev_s *dev)
static int sam_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct sam_dev_s *priv;
uint32_t pending;
uint32_t imr;
int passes;
bool handled;
uint32_t pending;
uint32_t imr;
int passes;
bool handled;
DEBUGASSERT(dev && dev->priv);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct sam_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or, until we have
@ -1068,72 +1036,6 @@ static int sam_interrupt(struct uart_dev_s *dev)
return OK;
}
/****************************************************************************
* Name: sam_uart[n]_interrupt
*
* Description:
* UART interrupt handlers
*
****************************************************************************/
#ifdef CONFIG_SAMV7_UART0
static int sam_uart0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_uart0port);
}
#endif
#ifdef CONFIG_SAMV7_UART1
static int sam_uart1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_uart1port);
}
#endif
#ifdef CONFIG_SAMV7_UART2
static int sam_uart2_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_uart2port);
}
#endif
#ifdef CONFIG_SAMV7_UART3
static int sam_uart3_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_uart3port);
}
#endif
#ifdef CONFIG_SAMV7_UART4
static int sam_uart4_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_uart4port);
}
#endif
/****************************************************************************
* Name: sam_usart[n]_interrupt
*
* Description:
* USART interrupt handlers
*
****************************************************************************/
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_SERIALDRIVER)
static int sam_usart0_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart0port);
}
#endif
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_SERIALDRIVER)
static int sam_usart1_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart1port);
}
#endif
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_SERIALDRIVER)
static int sam_usart2_interrupt(int irq, void *context, FAR void *arg)
{
return sam_interrupt(&g_usart2port);
}
#endif
/****************************************************************************
* Name: sam_ioctl
*

67
arch/arm/src/samv7/sam_spi_slave.c
View File

@ -146,13 +146,7 @@ static void spi_semtake(struct sam_spidev_s *priv);
/* Interrupt Handling */
static int spi_interrupt(struct sam_spidev_s *priv);
#ifdef CONFIG_SAMV7_SPI0_SLAVE
static int spi0_interrupt(int irq, void *context, FAR void *arg);
#endif
#ifdef CONFIG_SAMV7_SPI1_SLAVE
static int spi1_interrupt(int irq, void *context, FAR void *arg);
#endif
static int spi_interrupt(int irq, void *context, FAR void *arg);
/* SPI Helpers */
@ -395,13 +389,16 @@ static void spi_semtake(struct sam_spidev_s *priv)
*
****************************************************************************/
static int spi_interrupt(struct sam_spidev_s *priv)
static int spi_interrupt(int irq, void *context, FAR void *arg)
{
struct sam_spidev_s *priv = (struct sam_spidev_s *)arg;
uint32_t sr;
uint32_t imr;
uint32_t pending;
uint32_t regval;
DEBUGASSERT(priv != NULL);
/* We loop because the TDRE interrupt will probably immediately follow the
* RDRF interrupt and we might be able to catch it in this handler
* execution.
@ -553,48 +550,6 @@ static int spi_interrupt(struct sam_spidev_s *priv)
return OK;
}
/****************************************************************************
* Name: spi0_interrupt
*
* Description:
* SPI0 interrupt handler
*
* Input Parameters:
* Standard interrupt input parameters
*
* Returned Value:
* Standard interrupt return value.
*
****************************************************************************/
#ifdef CONFIG_SAMV7_SPI0_SLAVE
static int spi0_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi0_sctrlr);
}
#endif
/****************************************************************************
* Name: spi1_interrupt
*
* Description:
* SPI1 interrupt handler
*
* Input Parameters:
* Standard interrupt input parameters
*
* Returned Value:
* Standard interrupt return value.
*
****************************************************************************/
#ifdef CONFIG_SAMV7_SPI1_SLAVE
static int spi1_interrupt(int irq, void *context, FAR void *arg)
{
return spi_interrupt(&g_spi1_sctrlr);
}
#endif
/****************************************************************************
* Name: spi_dequeue
*
@ -1177,9 +1132,8 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
{
/* Set the SPI0 register base address and interrupt information */
priv->base = SAM_SPI0_BASE,
priv->irq = SAM_IRQ_SPI0;
priv->handler = spi0_interrupt;
priv->base = SAM_SPI0_BASE,
priv->irq = SAM_IRQ_SPI0;
/* Enable peripheral clocking to SPI0 */
@ -1200,9 +1154,8 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
{
/* Set the SPI1 register base address and interrupt information */
priv->base = SAM_SPI1_BASE,
priv->irq = SAM_IRQ_SPI1;
priv->handler = spi1_interrupt;
priv->base = SAM_SPI1_BASE,
priv->irq = SAM_IRQ_SPI1;
/* Enable peripheral clocking to SPI1 */
@ -1255,7 +1208,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
/* Attach and enable interrupts at the NVIC */
DEBUGVERIFY(irq_attach(priv->irq, priv->handler, NULL));
DEBUGVERIFY(irq_attach(priv->irq, spi_interrupt, priv));
up_enable_irq(priv->irq);
spi_dumpregs(priv, "After initialization");