sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merged nuttx/arch into master

Browse Source
This commit is contained in:
Lok Tep 2015-11-09 14:24:41 +01:00
commit 7d386866af
200 changed files with 7607 additions and 2388 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/Kconfig
View File

@ -426,7 +426,8 @@ config ARMV7M_MPU
config ARMV7M_MPU_NREGIONS
int "Number of MPU regions"
default 8
default 16 if ARCH_CORTEXM7
default 8 if !ARCH_CORTEXM7
depends on ARMV7M_MPU
---help---
This is the number of protection regions supported by the MPU.

78
arch/arm/include/lpc43xx/chip.h
View File

@ -78,33 +78,33 @@
/* Get customizations for each supported chip.
*
* SRAM Resources
* --------------------- -------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* --------------------- -------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
@ -321,6 +321,32 @@
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (0) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)

38
arch/arm/include/stm32/chip.h
View File

@ -2307,6 +2307,44 @@
# define STM32_NRNG 0 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 168 /* GPIOA-K */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# error "Unsupported STM32 chip"
#endif

6
arch/arm/src/arm/up_assert.c
View File

@ -316,9 +316,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -343,7 +343,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/arm/up_doirq.c
View File

@ -74,7 +74,7 @@
void up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -130,5 +130,5 @@ void up_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
}

2
arch/arm/src/arm/up_nommuhead.S
View File

@ -125,7 +125,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
#ifdef CONFIG_STACK_COLORATION

4
arch/arm/src/arm/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv6-m/up_assert.c
View File

@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -398,7 +398,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv6-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv6-m/up_sigdeliver.c
View File

@ -98,7 +98,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -143,7 +143,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv7-a/arm_assert.c
View File

@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -397,7 +397,7 @@ void up_assert(const uint8_t *filename, int lineno)
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-a/arm_doirq.c
View File

@ -74,7 +74,7 @@
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -128,6 +128,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv7-a/arm_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

2
arch/arm/src/armv7-m/cache.h
View File

@ -76,9 +76,11 @@
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/****************************************************************************
* Inline Functions

66
arch/arm/src/armv7-m/mpu.h
View File

@ -248,14 +248,56 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
}
/****************************************************************************
* Name: mpu_userflash
* Name: mpu_priv_stronglyordered
*
* Description:
* Configure a region for privileged, strongly ordered memory
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
putreg32((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID, MPU_RBAR);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
/* Not Cacheable */
/* Not Bufferable */
MPU_RASR_S | /* Shareable */
MPU_RASR_AP_RWNO; /* P:RW U:None */
putreg32(regval, MPU_RASR);
}
#endif
/****************************************************************************
* Name: mpu_user_flash
*
* Description:
* Configure a region for user program flash
*
****************************************************************************/
static inline void mpu_userflash(uintptr_t base, size_t size)
static inline void mpu_user_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@ -286,14 +328,14 @@ static inline void mpu_userflash(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privflash
* Name: mpu_priv_flash
*
* Description:
* Configure a region for privileged program flash
*
****************************************************************************/
static inline void mpu_privflash(uintptr_t base, size_t size)
static inline void mpu_priv_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@ -324,14 +366,14 @@ static inline void mpu_privflash(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_userintsram
* Name: mpu_user_intsram
*
* Description:
* Configure a region as user internal SRAM
*
****************************************************************************/
static inline void mpu_userintsram(uintptr_t base, size_t size)
static inline void mpu_user_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@ -363,14 +405,14 @@ static inline void mpu_userintsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privintsram
* Name: mpu_priv_intsram
*
* Description:
* Configure a region as privileged internal SRAM
*
****************************************************************************/
static inline void mpu_privintsram(uintptr_t base, size_t size)
static inline void mpu_priv_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@ -402,14 +444,14 @@ static inline void mpu_privintsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_userextsram
* Name: mpu_user_extsram
*
* Description:
* Configure a region as user external SRAM
*
****************************************************************************/
static inline void mpu_userextsram(uintptr_t base, size_t size)
static inline void mpu_user_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
@ -442,14 +484,14 @@ static inline void mpu_userextsram(uintptr_t base, size_t size)
}
/****************************************************************************
* Name: mpu_privextsram
* Name: mpu_priv_extsram
*
* Description:
* Configure a region as privileged external SRAM
*
****************************************************************************/
static inline void mpu_privextsram(uintptr_t base, size_t size)
static inline void mpu_priv_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;

6
arch/arm/src/armv7-m/up_assert.c
View File

@ -380,9 +380,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -407,7 +407,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

2
arch/arm/src/armv7-m/up_lazyexception.S
View File

@ -1,5 +1,5 @@
/************************************************************************************************
* arch/arm/src/armv7-m/sam_vectors.S
* arch/arm/src/armv7-m/up_lazyexcption.S
*
* Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

4
arch/arm/src/armv7-m/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -146,7 +146,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

1
arch/arm/src/armv7-m/up_stackcheck.c
View File

@ -1,4 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_stackcheck.c
*
* Copyright (c) 2013, 2014 PX4 Development Team. All rights reserved.
*

4
arch/arm/src/common/up_allocateheap.c
View File

@ -142,14 +142,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

2
arch/arm/src/common/up_createstack.c
View File

@ -227,7 +227,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
#endif
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

2
arch/arm/src/common/up_initialize.c
View File

@ -275,5 +275,5 @@ void up_initialize(void)
/* Initialize the L2 cache if present and selected */
up_l2ccinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

2
arch/arm/src/dm320/dm320_allocateheap.c
View File

@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack;
}

3
arch/arm/src/dm320/dm320_boot.c
View File

@ -225,8 +225,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT

4
arch/arm/src/efm32/efm32_idle.c
View File

@ -61,8 +61,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

2
arch/arm/src/efm32/efm32_pwm.c
View File

@ -808,7 +808,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
*/
*/
flags = irqsave();

2
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -3949,7 +3949,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
/* If this is a connection on the root hub, then we need to go to
* little more effort to get the device speed. If it is a connection
* on an external hub, then we already have that information.
*/
*/
#ifdef CONFIG_USBHOST_HUB
if (ROOTHUB(hport))

2
arch/arm/src/imx/imx_allocateheap.c
View File

@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack;
}

3
arch/arm/src/imx/imx_boot.c
View File

@ -216,8 +216,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT

2
arch/arm/src/imx/imx_irq.c
View File

@ -87,7 +87,7 @@ void up_irqinitialize(void)
/* Set masking of normal interrupts by priority. Writing all ones
* (or -1) to the NIMASK register sets the normal interrupt mask to
* -1 and does not disable any normal interrupt priority levels.
*/
*/
#ifndef CONFIG_SUPPRESS_INTERRUPTS
putreg32(-1, IMX_AITC_NIMASK); /* -1: No priority levels masked */

4
arch/arm/src/kinetis/kinetis_allocateheap.c
View File

@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/kinetis/kinetis_idle.c
View File

@ -54,8 +54,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

8
arch/arm/src/kinetis/kinetis_mpuinit.c
View File

@ -95,10 +95,10 @@ void kinetis_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -117,7 +117,7 @@ void kinetis_mpuinitialize(void)
void kinetis_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

4
arch/arm/src/kl/kl_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/lpc11xx/lpc11_idle.c
View File

@ -53,8 +53,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/lpc17xx/lpc17_allocateheap.c
View File

@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -260,7 +260,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/lpc17xx/lpc17_idle.c
View File

@ -55,8 +55,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

8
arch/arm/src/lpc17xx/lpc17_mpuinit.c
View File

@ -95,10 +95,10 @@ void lpc17_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -117,7 +117,7 @@ void lpc17_mpuinitialize(void)
void lpc17_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

2
arch/arm/src/lpc214x/lpc214x_head.S
View File

@ -592,7 +592,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc2378/lpc23xx_head.S
View File

@ -193,7 +193,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc31xx/lpc31_allocateheap.c
View File

@ -180,7 +180,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = LPC31_HEAP_VEND - g_idle_topstack;
}

8
arch/arm/src/lpc43xx/Kconfig
View File

@ -34,6 +34,9 @@ config ARCH_CHIP_LPC4330FET180
config ARCH_CHIP_LPC4330FET256
bool "LPC4330FET256"
config ARCH_CHIP_LPC4337JBD144
bool "LPC4337JBD144"
config ARCH_CHIP_LPC4350FBD208
bool "LPC4350FBD208"
@ -81,6 +84,11 @@ config ARCH_FAMILY_LPC4330
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4337
bool
default y if ARCH_CHIP_LPC4337JBD144
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4350
bool
default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256

4
arch/arm/src/lpc43xx/chip.h
View File

@ -97,6 +97,10 @@
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"
# include "chip/lpc4310203050_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc435357_memorymap.h"
# include "chip/lpc4357fet256_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"

2
arch/arm/src/lpc43xx/lpc43_allocateheap.c
View File

@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* Start with the first SRAM region */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

4
arch/arm/src/lpc43xx/lpc43_idle.c
View File

@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

8
arch/arm/src/lpc43xx/lpc43_mpuinit.c
View File

@ -95,10 +95,10 @@ void lpc43_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -117,7 +117,7 @@ void lpc43_mpuinitialize(void)
void lpc43_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

4
arch/arm/src/nuc1xx/nuc_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

1
arch/arm/src/sam34/Kconfig
View File

@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A
config ARCH_CHIP_SAM4CM
bool
default n
select ARCH_HAVE_TICKLESS
config ARCH_CHIP_SAM4L
bool

4
arch/arm/src/sam34/sam_allocateheap.c
View File

@ -230,7 +230,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -241,7 +241,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

8
arch/arm/src/sam34/sam_mpuinit.c
View File

@ -95,10 +95,10 @@ void sam_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -117,7 +117,7 @@ void sam_mpuinitialize(void)
void sam_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

5
arch/arm/src/sam34/sam_rtc.c
View File

@ -783,9 +783,8 @@ int up_rtc_gettime(FAR struct timespec *tp)
rtt_val = getreg32(SAM_RTT_VR);
}
while (rtc_cal != getreg32(SAM_RTC_CALR) ||
rtc_tim != getreg32(SAM_RTC_TIMR));
(rtt_val != getreg32(SAM_RTT_VR)));
rtc_tim != getreg32(SAM_RTC_TIMR) ||
rtt_val != getreg32(SAM_RTT_VR));
t.tm_sec = rtc_bcd2bin((rtc_tim & RTC_TIMR_SEC_MASK) >> RTC_TIMR_SEC_SHIFT);
t.tm_min = rtc_bcd2bin((rtc_tim & RTC_TIMR_MIN_MASK) >> RTC_TIMR_MIN_SHIFT);

4
arch/arm/src/sama5/sam_allocateheap.c
View File

@ -258,7 +258,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* heap is at the end of BSS through the configured end of SDRAM.
*/
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)&_ebss;
*heap_size = SAMA5_PRIMARY_HEAP_END - (size_t)&_ebss;
@ -267,7 +267,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* IDLE stack through the configured end of ISRAM.
*/
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SAMA5_PRIMARY_HEAP_END - g_idle_topstack;
#endif

4
arch/arm/src/samdl/sam_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/samv7/Kconfig
View File

@ -223,6 +223,7 @@ config SAMV7_MCAN0
bool "CAN controller 0 (MCAN0)"
default n
select CAN
select CAN_TXREADY
select SAMV7_MCAN
config SAMV7_MCAN1
@ -230,6 +231,7 @@ config SAMV7_MCAN1
default n
depends on SAMV7_HAVE_MCAN1
select CAN
select CAN_TXREADY
select SAMV7_MCAN
config SAMV7_DAC0
@ -285,6 +287,8 @@ config SAMV7_PWM1
config SAMV7_QSPI
bool "Quad SPI (QSPI)"
default n
select ARCH_USE_MPU
select ARMV7M_MPU
config SAMV7_RTC
bool "Real Time Clock (RTC)"

12
arch/arm/src/samv7/Make.defs
View File

@ -90,13 +90,16 @@ ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_ARMV7M_MPU),y)
CMN_CSRCS += up_mpu.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
CMN_CSRCS += up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
@ -118,6 +121,13 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif
ifeq ($(CONFIG_ARMV7M_MPU),y)
CHIP_CSRCS += sam_mpuinit.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += sam_userspace.c
endif
endif
ifeq ($(CONFIG_SAMV7_GPIO_IRQ),y)
CHIP_CSRCS += sam_gpioirq.c
endif

4
arch/arm/src/samv7/chip/samv71_memorymap.h
View File

@ -159,6 +159,10 @@
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x6fffffff: EBI Chip select 3 */
#define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */
/* QSPI memory region */
#define SAM_QSPIMEM_SIZE 0x20000000 /* 0x80000000-0x9fffffff: QSPI memory */
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */

4
arch/arm/src/samv7/sam_allocateheap.c
View File

@ -237,7 +237,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

22
arch/arm/src/samv7/sam_config.h
View File

@ -109,18 +109,26 @@
#endif
/* USARTs *******************************************************************/
/* If the USART is not being used as a UART, then it really isn't enabled
* for our purposes.
/* If the USART is not being used as a UART or for SPI, then it really isn't
* enabled for our purposes.
*/
#ifndef CONFIG_USART0_ISUART
#if !defined(CONFIG_USART0_ISUART) && !defined(CONFIG_USART0_ISSPI)
# undef CONFIG_SAMV7_USART0
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART0_IFLOWCONTROL
#endif
#ifndef CONFIG_USART1_ISUART
#if !defined(CONFIG_USART1_ISUART) && !defined(CONFIG_USART1_ISSPI)
# undef CONFIG_SAMV7_USART1
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART1_IFLOWCONTROL
#endif
#ifndef CONFIG_USART2_ISUART
#if !defined(CONFIG_USART2_ISUART) && !defined(CONFIG_USART2_ISSPI)
# undef CONFIG_SAMV7_USART2
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART2_IFLOWCONTROL
#endif
/* Don't enable USARTs not supported by the chip. */
@ -153,10 +161,10 @@
#undef CONFIG_UART3_IFLOWCONTROL
#undef CONFIG_UART4_IFLOWCONTROL
/* Hardware flow control requires using DMAC channel (not yet supported) */
/* Hardware flow control requires using a DMAC channel (not yet supported) */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# warning PDC or DMAC support is required for RTS hardware flow control
# warning XDMAC support is required for RTS hardware flow control
# undef CONFIG_SERIAL_IFLOWCONTROL
# undef CONFIG_USART0_IFLOWCONTROL
# undef CONFIG_USART1_IFLOWCONTROL

8
arch/arm/src/samv7/sam_lowputc.c
View File

@ -54,6 +54,7 @@
#include "chip/sam_uart.h"
#include "chip/sam_pinmap.h"
#include "chip/sam_matrix.h"
/****************************************************************************
* Pre-processor Definitions
@ -353,6 +354,13 @@ void sam_lowsetup(void)
#ifdef CONFIG_USART1_IFLOWCONTROL
(void)sam_configgpio(GPIO_USART1_RTS);
#endif
/* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
* instead of TDI
*/
uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);
#endif
#ifdef CONFIG_SAMV7_USART2

45
arch/arm/src/samv7/sam_mcan.c
View File

@ -128,6 +128,12 @@
# endif
#endif
/* General Configuration ****************************************************/
#ifndef CONFIG_CAN_TXREADY
# warning WARNING!!! CONFIG_CAN_TXREADY is required by this driver
#endif
/* MCAN0 Configuration ******************************************************/
#ifdef CONFIG_SAMV7_MCAN0
@ -2435,8 +2441,8 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
DEBUGASSERT(bt != NULL);
DEBUGASSERT(bt->bt_baud < SAMV7_MCANCLK_FREQUENCY);
DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16);
DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16);
DEBUGASSERT(bt->bt_tseg2 > 1 && bt->bt_tseg2 <= 64);
DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64);
DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16);
/* Extract bit timing data */
@ -2642,11 +2648,11 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
DEBUGASSERT(config->ntxfifoq > 0);
/* Reserve a buffer for the transmission, waiting if necessary. When
* mcan_buffer_reserve() returns, we are guaranteed the the TX FIFOQ is
* mcan_buffer_reserve() returns, we are guaranteed that the TX FIFOQ is
* not full and cannot become full at least until we add our packet to
* the FIFO.
*
* We can't get exclusive access to MAN resource here because that
* We can't get exclusive access to MCAN resources here because that
* lock the MCAN while we wait for a free buffer. Instead, the
* scheduler is locked here momentarily. See discussion in
* mcan_buffer_reserve() for an explanation.
@ -2747,8 +2753,8 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
* course, the transfer is not complete, but this early notification
* allows the upper half logic to free resources sooner.
*
* REVISTI: Should we disable interrupts? can_txdone() was designed to
* be called from and interrupt handler and, hence, may be unsafe when
* REVISIT: Should we disable interrupts? can_txdone() was designed to
* be called from an interrupt handler and, hence, may be unsafe when
* called from the tasking level.
*/
@ -3039,10 +3045,18 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
regval = *rxbuffer++;
canregdbg("R0: %08x\n", regval);
hdr.ch_rtr = 0;
hdr.ch_error = 0;
hdr.ch_unused = 0;
if ((regval & BUFFER_R0_RTR) != 0)
{
hdr.ch_rtr = true;
}
else
{
hdr.ch_rtr = false;
}
#ifdef CONFIG_CAN_EXTID
if ((regval & BUFFER_R0_XTD) != 0)
{
@ -3190,6 +3204,14 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
mcan_buffer_release(priv);
handled = true;
#ifdef CONFIG_CAN_TXREADY
/* Inform the upper half driver that we are again ready to accept
* data in mcan_send().
*/
can_txready(dev);
#endif
}
else if ((pending & priv->txints) != 0)
{
@ -3452,14 +3474,11 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
/* Global Filter Configuration:
*
* ANFS=0: Store all rejected extended frame in RX FIFO0
* ANFE=0: Store all rejected extended frame in RX FIFO0
* FFSE=1: Reject all remote frames with 11-bit standard IDs.
* RRFE=1: Reject all remote frames with 29-bit extended IDs.
* ANFS=0: Store all non matching standard frame in RX FIFO0
* ANFE=0: Store all non matching extended frame in RX FIFO0
*/
regval = MCAN_GFC_RRFE | MCAN_GFC_RRFS | MCAN_GFC_ANFE_RX_FIFO0 |
MCAN_GFC_ANFS_RX_FIFO0;
regval = MCAN_GFC_ANFE_RX_FIFO0 | MCAN_GFC_ANFS_RX_FIFO0;
mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval);
/* Extended ID Filter AND mask */

150
arch/arm/src/samv7/sam_mpuinit.c Normal file
View File

@ -0,0 +1,150 @@
/****************************************************************************
* arch/arm/src/common/sam_mpuinit.c
*
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "cache.h"
#include "chip/sam_memorymap.h"
#include "sam_mpuinit.h"
#ifdef CONFIG_ARMV7M_MPU
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_mpu_initialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3/4
* resources.
*
****************************************************************************/
void sam_mpu_initialize(void)
{
#ifdef CONFIG_BUILD_PROTECTED
uintptr_t datastart;
uintptr_t dataend;
#endif
/* Show MPU information */
mpu_showtype();
#ifdef CONFIG_ARMV7M_DCACHE
/* Memory barrier */
ARM_DMB();
#ifdef CONFIG_SAMV7_QSPI
/* Make QSPI memory region strongly ordered */
mpu_priv_stronglyordered(SAM_QSPIMEM_BASE, SAM_QSPIMEM_SIZE);
#endif
#endif
#ifdef CONFIG_BUILD_PROTECTED
/* Configure user flash and SRAM space */
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(dataend >= datastart);
mpu_user_intsram(datastart, dataend - datastart);
#endif
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: sam_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void sam_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif
#endif /* CONFIG_ARMV7M_MPU */

22
arch/arm/src/samv7/sam_mpuinit.h
View File

@ -1,5 +1,4 @@
/****************************************************************************
* Name: sam_mpuinitialize
* arch/arm/src/samv7/sam_mpuinit.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
@ -38,7 +37,6 @@
#define __ARCH_ARM_SRC_SAMV7_SAM_MPUINIT_H
/****************************************************************************
* Name: sam_mpuinitialize
* Included Files
****************************************************************************/
@ -48,24 +46,12 @@
#include <stdint.h>
/****************************************************************************
* Name: sam_mpuinitialize
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: sam_mpuinitialize
* Public Types
****************************************************************************/
/****************************************************************************
* Name: sam_mpuinitialize
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Name: sam_mpuinitialize
* Public Data
****************************************************************************/
@ -83,7 +69,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: sam_mpuinitialize
* Name: sam_mpu_initialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted SAMV7
@ -91,10 +77,10 @@ extern "C"
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void sam_mpuinitialize(void);
#ifdef CONFIG_ARMV7M_MPU
void sam_mpu_initialize(void);
#else
# define sam_mpuinitialize()
# define sam_mpu_initialize()
#endif
/****************************************************************************

77
arch/arm/src/samv7/sam_qspi.c
View File

@ -126,16 +126,15 @@
/* QSPI memory synchronization */
#define MEMORY_SYNC() do { ARM_DSB();ARM_ISB(); } while (0)
#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0)
/* The SAMV7x QSPI driver insists that transfers be performed in multiples
* of 32-bits.
* of 32-bits. The alignment requirement only applies to RX DMA data.
*/
#define ALIGN_SHIFT 2
#define ALIGN_MASK 3
#define ALIGN_UP(n) (((n)+ALIGN_MASK) & ~ALIGN_MASK)
#define ALIGN_WORDS(n) (((n)+ALIGN_MASK) >> ALIGN_SHIFT)
#define IS_ALIGNED(n) (((uint32_t)(n) & ALIGN_MASK) == 0)
/* Debug *******************************************************************/
@ -713,7 +712,7 @@ static int qspi_memory_enable(struct sam_qspidev_s *priv,
* QSPI_ICR_OPT(0) No option
*/
regval = QSPI_ICR_INST(meminfo->cmd) | QSPI_ICR_OPT(0);
regval = QSPI_ICR_INST(meminfo->cmd) | QSPI_ICR_OPT(0);
qspi_putreg(priv, regval, SAM_QSPI_ICR_OFFSET);
/* Is memory data scrambled? */
@ -856,7 +855,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
/* Configure RX DMA */
dmaflags |= ((uint32_t)priv->rxintf << DMACH_FLAG_PERIPHPID_SHIFT) |
DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_MEMWIDTH_16BITS;
DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_MEMWIDTH_32BITS;
sam_dmaconfig(priv->dmach, dmaflags);
/* Setup the RX DMA (memory-to-peripheral) */
@ -988,11 +987,6 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv,
struct qspi_meminfo_s *meminfo)
{
uintptr_t qspimem = SAM_QSPIMEM_BASE + meminfo->addr;
size_t buflen;
/* Get the length as an even multiple of 32-bit words. */
buflen = ALIGN_UP(meminfo->buflen);
/* Enable the memory transfer */
@ -1002,13 +996,13 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv,
if (QSPIMEM_ISWRITE(meminfo->flags))
{
qspi_memcpy((uint8_t *)qspimem,
(const uint8_t *)meminfo->buffer, buflen);
qspi_memcpy((uint8_t *)qspimem, (const uint8_t *)meminfo->buffer,
meminfo->buflen);
}
else
{
qspi_memcpy((uint8_t *)meminfo->buffer,
(const uint8_t *)qspimem, buflen);
qspi_memcpy((uint8_t *)meminfo->buffer, (const uint8_t *)qspimem,
meminfo->buflen);
}
MEMORY_SYNC();
@ -1146,13 +1140,14 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
return priv->actual;
}
/* Configure QSPI to a frequency as close as possible to the requested frequency.
/* Configure QSPI to a frequency as close as possible to the requested
* frequency.
*
* QSCK frequency = QSPI_CLK / SCBR, or SCBR = QSPI_CLK / frequency
*
* Where SCBR can have the range 1 to 256 and register holds SCBR - 1. NOTE
* that a "ceiling" type of calculation is performed. 'frequency' is treated
* as a not-to-exceed value.
* Where SCBR can have the range 1 to 256 and the SCR register field holds
* SCBR - 1. NOTE that a "ceiling" type of calculation is performed.
* 'frequency' is treated as a not-to-exceed value.
*/
scbr = (frequency + SAM_QSPI_CLOCK - 1) / frequency;
@ -1336,7 +1331,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
regval |= QSPI_MR_NBBITS(nbits);
qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET);
qspivdbg("SCR%02x]=%08x\n", regval);
qspivdbg("MR=%08x\n", regval);
/* Save the selection so the subsequence re-configurations will be faster */
@ -1434,15 +1429,9 @@ static int qspi_command(struct qspi_dev_s *dev,
if (QSPICMD_ISDATA(cmdinfo->flags))
{
uint16_t buflen;
DEBUGASSERT(cmdinfo->buffer != NULL && cmdinfo->buflen > 0);
DEBUGASSERT(IS_ALIGNED(cmdinfo->buffer));
/* Get the length as an even multiple of 32-bit words. */
buflen = ALIGN_UP(cmdinfo->buflen);
/* Write Instruction Frame Register:
*
* QSPI_IFR_WIDTH_SINGLE Instruction=single bit/Data single bit
@ -1461,17 +1450,23 @@ static int qspi_command(struct qspi_dev_s *dev,
ifr |= QSPI_IFR_WIDTH_SINGLE | QSPI_IFR_INSTEN | QSPI_IFR_DATAEN |
QSPI_IFR_NBDUM(0);
/* Read or write operation? */
if (QSPICMD_ISWRITE(cmdinfo->flags))
{
/* Set write data operation */
/* Set write data operation
*
* Write the IFR to the hardware. If the instructrion frame
* includes data, writing to the IFR does not trigger the
* instruction frame transfer. Rather, the instruction frame
* is triggered by the first access to QSPI memory.
*/
ifr |= QSPI_IFR_TFRTYP_WRITE;
qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET);
/* Write the IFR to the hardware. If the instructrion frame
* includes data, writing to the IFR does not trigger the
* instruction frame transfer. Rather, the instruction frame
* is triggered by the first access to QSPI memory.
/* Read QSPI_IFR (dummy read) to synchronize APB and AHB
* accesses.
*/
(void)qspi_getreg(priv, SAM_QSPI_IFR_OFFSET);
@ -1479,19 +1474,23 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Copy the data to write to QSPI_RAM */
qspi_memcpy((uint8_t *)SAM_QSPIMEM_BASE,
(const uint8_t *)cmdinfo->buffer, buflen);
(const uint8_t *)cmdinfo->buffer, cmdinfo->buflen);
}
else
{
/* Set read data operation */
/* Set read data operation
*
* Write the IFR to the hardware. If the instructrion frame
* includes data, writing to the IFR does not trigger the
* instruction frame transfer. Rather, the instruction frame
* is triggered by the first access to QSPI memory.
*/
ifr |= QSPI_IFR_TFRTYP_READ;
qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET);
/* Write the IFR to the hardware. If the instructrion frame
* includes data, writing to the IFR does not trigger the
* instruction frame transfer. Rather, the instruction frame
* is triggered by the first access to QSPI memory.
/* Read QSPI_IFR (dummy read) to synchronize APB and AHB
* accesses.
*/
(void)qspi_getreg(priv, SAM_QSPI_IFR_OFFSET);
@ -1499,7 +1498,7 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Copy the data from QSPI memory into the user buffer */
qspi_memcpy((uint8_t *)cmdinfo->buffer,
(const uint8_t *)SAM_QSPIMEM_BASE, buflen);
(const uint8_t *)SAM_QSPIMEM_BASE, cmdinfo->buflen);
}
MEMORY_SYNC();
@ -1588,7 +1587,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
}
/****************************************************************************
* Name: QSPI_ALLOC
* Name: qspi_alloc
*
* Description:
* Allocate a buffer suitable for DMA data transfer
@ -1734,7 +1733,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
struct sam_qspidev_s *priv;
int ret;
/* The support SAM parts have only a single QSPI port */
/* The supported SAM parts have only a single QSPI port */
qspivdbg("intf: %d\n", intf);
DEBUGASSERT(intf >= 0 && intf < SAMV7_NQSPI);

90
arch/arm/src/samv7/sam_serial.c
View File

@ -123,13 +123,13 @@
# elif defined(CONFIG_SAMV7_UART4)
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART0)
# elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
# define USART0_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART1)
# elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */
# define USART1_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART2)
# elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */
# define USART2_ASSIGNED 1
# endif
@ -154,13 +154,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */
# define USART2_ASSIGNED 1
#endif
@ -182,13 +185,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */
# define USART2_ASSIGNED 1
#endif
@ -207,13 +213,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */
# define USART2_ASSIGNED 1
#endif
@ -229,13 +238,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */
# define USART2_ASSIGNED 1
#endif
@ -248,13 +260,16 @@
#if defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */
# define USART2_ASSIGNED 1
#endif
@ -264,13 +279,16 @@
* One of USART0-2 could also be the console.
*/
#if defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */
# define USART2_ASSIGNED 1
#endif
@ -280,10 +298,12 @@
* One of of USART1-2 could also be the console.
*/
#if defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */
# define USART2_ASSIGNED 1
#endif
@ -349,13 +369,13 @@ static int sam_uart3_interrupt(int irq, void *context);
#ifdef CONFIG_SAMV7_UART4
static int sam_uart4_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static int sam_usart0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static int sam_usart1_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static int sam_usart2_interrupt(int irq, void *context);
#endif
static int sam_ioctl(struct file *filep, int cmd, unsigned long arg);
@ -412,15 +432,15 @@ static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
@ -582,7 +602,7 @@ static uart_dev_t g_uart4port =
/* This describes the state of the USART0 port. */
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static struct sam_dev_s g_usart0priv =
{
.usartbase = SAM_USART0_BASE,
@ -616,7 +636,7 @@ static uart_dev_t g_usart0port =
/* This describes the state of the USART1 port. */
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static struct sam_dev_s g_usart1priv =
{
.usartbase = SAM_USART1_BASE,
@ -650,7 +670,7 @@ static uart_dev_t g_usart1port =
/* This describes the state of the USART2 port. */
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static struct sam_dev_s g_usart2priv =
{
.usartbase = SAM_USART2_BASE,
@ -1095,19 +1115,19 @@ static int sam_uart4_interrupt(int irq, void *context)
*
****************************************************************************/
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static int sam_usart0_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart0port);
}
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static int sam_usart1_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart1port);
}
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static int sam_usart2_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart2port);

30
arch/arm/src/samv7/sam_start.c
View File

@ -55,6 +55,7 @@
#endif
#include "sam_clockconfig.h"
#include "sam_mpuinit.h"
#include "sam_userspace.h"
#include "sam_start.h"
@ -366,6 +367,25 @@ void __start(void)
sam_boardinitialize();
#ifdef CONFIG_ARMV7M_MPU
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segements.
*/
#ifdef CONFIG_BUILD_PROTECTED
sam_userspace();
#endif
/* Configure the MPU to permit user-space access to its FLASH and RAM (for
* CONFIG_BUILD_PROTECTED) or to manage cache properties (for
* CONFIG_SAMV7_QSPI).
*/
sam_mpu_initialize();
#endif
/* Enable I- and D-Caches */
arch_dcache_writethrough();
@ -378,16 +398,6 @@ void __start(void)
up_earlyserialinit();
#endif
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segements.
*/
#ifdef CONFIG_BUILD_PROTECTED
sam_userspace();
#endif
/* Then start NuttX */
#ifdef CONFIG_STACK_COLORATION

105
arch/arm/src/samv7/sam_userspace.c Normal file
View File

@ -0,0 +1,105 @@
/****************************************************************************
* arch/arm/src/samv7/sam_userspace.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "sam_mpuinit.h"
#include "sam_userspace.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
* Assumptions:
* The D-Cache has not yet been enabled.
*
****************************************************************************/
void sam_userspace(void)
{
uint8_t *src;
uint8_t *dest;
uint8_t *end;
/* Clear all of user-space .bss */
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
*dest++ = 0;
}
/* Initialize all of user-space .data */
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{
*dest++ = *src++;
}
}
#endif /* CONFIG_BUILD_PROTECTED */

4
arch/arm/src/samv7/sam_xdmac.c
View File

@ -2037,7 +2037,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->gcfg = sam_getdmac(xdmac, SAM_XDMAC_GCFG_OFFSET);
regs->gwac = sam_getdmac(xdmac, SAM_XDMAC_GWAC_OFFSET);
regs->gim = sam_getdmac(xdmac, SAM_XDMAC_GIM_OFFSET);
regs->gis = sam_getdmac(xdmac, SAM_XDMAC_GIS_OFFSET);
regs->gs = sam_getdmac(xdmac, SAM_XDMAC_GS_OFFSET);
regs->grs = sam_getdmac(xdmac, SAM_XDMAC_GRS_OFFSET);
regs->gws = sam_getdmac(xdmac, SAM_XDMAC_GWS_OFFSET);
@ -2046,7 +2045,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
/* Sample channel registers */
regs->cim = sam_getdmach(xdmach, SAM_XDMACH_CIM_OFFSET);
regs->cis = sam_getdmach(xdmach, SAM_XDMACH_CIS_OFFSET);
regs->csa = sam_getdmach(xdmach, SAM_XDMACH_CSA_OFFSET);
regs->cda = sam_getdmach(xdmach, SAM_XDMACH_CDA_OFFSET);
regs->cnda = sam_getdmach(xdmach, SAM_XDMACH_CNDA_OFFSET);
@ -2085,14 +2083,12 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
dmadbg(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg);
dmadbg(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac);
dmadbg(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim);
dmadbg(" GIS[%08x]: %08x\n", SAM_XDMAC_GIS, regs->gis);
dmadbg(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs);
dmadbg(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs);
dmadbg(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws);
dmadbg(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws);
dmadbg(" DMA Channel Registers:\n");
dmadbg(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
dmadbg(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis);
dmadbg(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
dmadbg(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
dmadbg(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);

16
arch/arm/src/samv7/sam_xdmac.h
View File

@ -175,22 +175,30 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
#ifdef CONFIG_DEBUG_DMA
struct sam_dmaregs_s
{
/* Global Registers */
/* Global Registers.
*
* This includes all readable global XDMAC registers except for the global
* interrupt status register (XDMAC_GIS). Reading from the status
* register could cause loss of interrupts.
*/
uint32_t gtype; /* Global Type Register */
uint32_t gcfg; /* Global Configuration Register */
uint32_t gwac; /* Global Weighted Arbiter Configuration Register */
uint32_t gim; /* Global Interrupt Mask Register */
uint32_t gis; /* Global Interrupt Status Register */
uint32_t gs; /* Global Channel Status Register */
uint32_t grs; /* Global Channel Read Suspend Register */
uint32_t gws; /* Global Channel Write Suspend Register */
uint32_t gsws; /* Global Channel Software Request Status Register */
/* Channel Registers */
/* Channel Registers
*
* This includes all readable XDMAC channel registers except for the
* channel interrupt status register (XDMAC_CIS). Reading from the status
* register could cause loss of interrupts.
*/
uint32_t cim; /* Channel Interrupt Mask Register */
uint32_t cis; /* Channel Interrupt Status Register */
uint32_t csa; /* Channel Source Address Register */
uint32_t cda; /* Channel Destination Address Register */
uint32_t cnda; /* Channel Next Descriptor Address Register */

2017
arch/arm/src/stm32/Kconfig
View File

File diff suppressed because it is too large Load Diff

130
arch/arm/src/stm32/chip/stm32_adc.h
View File

@ -308,24 +308,37 @@
/* Bits 12-15: Reserved */
# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_T1CC4 (0x0 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event. For STM32L15XX: TIM9_CC1 event */
# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event. For STM32L15XX: TIM9_TRGO event */
# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event. For STM32L15XX: TIM2_TRGO event */
# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event. For STM32L15XX: TIM2_CC1 event */
# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event. For STM32L15XX: TIM3_CC4 event */
# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event. For STM32L15XX: TIM4_TRGO event */
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event. For STM32L15XX: TIM4_CC1 event */
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event. For STM32L15XX: TIM4_CC2 event */
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event. For STM32L15XX: TIM4_CC3 event */
# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event. For STM32L15XX: TIM10_CC1 event */
# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event. For STM32L15XX: TIM7_TRGO event */
# ifndef CONFIG_STM32_STM32L15XX
# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event. */
# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event. */
# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event. */
# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event. */
# ifdef CONFIG_STM32_STM32L15XX
# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */
# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/
# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */
# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
# else
# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */
# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */
# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */
# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */
# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */
# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */
# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
# endif
# define ADC_CR2_JEXTSEL_EXTI (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line15 */
# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
@ -338,24 +351,37 @@
/* Bit 23: Reserved, must be kept at reset value. */
# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event. For STM32L15XX: TIM9_CC2 event */
# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event. For STM32L15XX: TIM9_TRGO event */
# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event. For STM32L15XX: TIM2_CC3 event */
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event. For STM32L15XX: TIM2_CC2 event */
# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event. For STM32L15XX: TIM3_TRGO event */
# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event. For STM32L15XX: TIM4_CC4 event */
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event. For STM32L15XX: TIM2_TRGO event */
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event. For STM32L15XX: TIM3_CC1 event */
# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event. For STM32L15XX: TIM3_CC3 event */
# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event. For STM32L15XX: TIM4_TRGO event */
# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event. For STM32L15XX: TIM6_TRGO event */
# ifndef CONFIG_STM32_STM32L15XX
# ifdef CONFIG_STM32_STM32L15XX
# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */
# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */
# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
# else
# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */
# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */
# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */
# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */
# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */
# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */
# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */
# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
# endif
# define ADC_CR2_EXTSEL_EXTI (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line11 */
# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
@ -375,7 +401,7 @@
# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */
# define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
@ -387,7 +413,7 @@
# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
@ -585,6 +611,9 @@
# define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
# define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
# define ADC_SQR1_RESERVED (0xff000000)
# define ADC_SQR1_FIRST (13)
# define ADC_SQR1_LAST (16)
# define ADC_SQR1_SQ_OFFSET (0)
#else
# define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */
# define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT)
@ -597,6 +626,9 @@
# define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */
# define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT)
# define ADC_SQR1_RESERVED (0xff000000)
# define ADC_SQR1_FIRST (25)
# define ADC_SQR1_LAST (28)
# define ADC_SQR1_SQ_OFFSET (0)
#endif
/* ADC regular sequence register 2 */
@ -615,6 +647,9 @@
# define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
# define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
# define ADC_SQR2_RESERVED (0xc0000000)
# define ADC_SQR2_FIRST (7)
# define ADC_SQR2_LAST (12)
# define ADC_SQR2_SQ_OFFSET (0)
#else
# define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */
# define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT)
@ -629,6 +664,9 @@
# define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */
# define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT)
# define ADC_SQR2_RESERVED (0xc0000000)
# define ADC_SQR2_FIRST (19)
# define ADC_SQR2_LAST (24)
# define ADC_SQR2_SQ_OFFSET (0)
#endif
/* ADC regular sequence register 3 */
@ -647,6 +685,9 @@
# define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
# define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
# define ADC_SQR3_RESERVED (0xc0000000)
# define ADC_SQR3_FIRST (1)
# define ADC_SQR3_LAST (6)
# define ADC_SQR3_SQ_OFFSET (0)
#else
# define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
# define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
@ -661,6 +702,9 @@
# define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */
# define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT)
# define ADC_SQR3_RESERVED (0xc0000000)
# define ADC_SQR3_FIRST (13)
# define ADC_SQR3_LAST (18)
# define ADC_SQR3_SQ_OFFSET (0)
#endif
/* ADC regular sequence register 4 */
@ -679,6 +723,9 @@
# define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
# define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT)
# define ADC_SQR4_RESERVED (0xc0000000)
# define ADC_SQR4_FIRST (7)
# define ADC_SQR4_LAST (12)
# define ADC_SQR4_SQ_OFFSET (0)
#endif
/* ADC regular sequence register 5 */
@ -697,8 +744,15 @@
# define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
# define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT)
# define ADC_SQR5_RESERVED (0xc0000000)
# define ADC_SQR5_FIRST (1)
# define ADC_SQR5_LAST (6)
# define ADC_SQR5_SQ_OFFSET (0)
#endif
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (5)
/* ADC injected sequence register */
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
@ -714,15 +768,15 @@
/* ADC injected data register 1-4 */
#define ADC_JDR_SHIFT (0) /* Bits 15-0: Injected data */
#define ADC_JDR_MASK (0xffff << ADC_JDR_SHIFT)
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
/* ADC regular data register */
#define ADC_DR_DATA_SHIFT (0) /* Bits 15-0 Regular data */
#define ADC_DR_DATA_MASK (0xffff << ADC_DR_DATA_SHIFT)
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
#ifndef CONFIG_STM32_STM32L15XX
#ifdef CONFIG_STM32_STM32F10XX
# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */
# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT)
#endif
@ -784,7 +838,7 @@
/* Bits 5-7: Reserved, must be kept at reset value. */
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((5)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
/* Bit 12 Reserved, must be kept at reset value. */
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */

2
arch/arm/src/stm32/chip/stm32_exti.h
View File

@ -146,7 +146,7 @@
# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */
#elif defined(CONFIG_STM32_STM32F30XX)
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */

12
arch/arm/src/stm32/chip/stm32_tim.h
View File

@ -677,8 +677,8 @@
#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
#ifdef CONFIG_STM32_STM32F30XX
# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
#endif
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
@ -698,6 +698,10 @@
#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */
#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */
#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */
#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */
/* Capture/compare mode register 1 -- Input capture mode */
@ -764,8 +768,8 @@
#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
#ifdef CONFIG_STM32_STM32F30XX
# define ATIM_CCMR1_OC3M 1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
# define ATIM_CCMR1_OC4M 1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
#endif
/* Capture/compare mode register 2 - Input Capture Mode */

233
arch/arm/src/stm32/chip/stm32f30xxx_adc.h
View File

@ -210,7 +210,7 @@
#define STM32_ADC34_CDR (STM32_ADC34_BASE+STM32_ADC_CDR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
@ -242,7 +242,8 @@
/* ADC configuration register */
#define ADC_CFGR_DMACFG (1 << 1) /* Bit 0: Direct memory access configuration */
#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT)
# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */
@ -252,7 +253,34 @@
#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */
# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T4CC4 (5 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
# define ADC12_CFGR_EXTSEL_T8TRGO (7 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T3CC1 (0 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T2CC3 (1 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T8CC1 (3 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T8TRGO (4 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T20TRGO (5 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T4CC1 (6 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T2TRGO (7 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T3TRGO (11 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T7TRGO (13 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC34_CFGR_EXTSEL_T2CC1 (15 << ADC_CFGR_EXTSEL_SHIFT)
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
@ -285,7 +313,7 @@
#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */
#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */
#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */
#define ADC_SMPR_2601p5 7 /* 111: 601.5 cycles */
#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */
#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT)
@ -348,6 +376,10 @@
#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */
#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT)
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (6)
/* ADC regular sequence register 1 */
#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */
@ -360,6 +392,10 @@
#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT)
#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */
#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT)
#define ADC_SQR1_RESERVED (0xe0820830)
#define ADC_SQR1_FIRST (1)
#define ADC_SQR1_LAST (4)
#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET)
/* ADC regular sequence register 2 */
@ -372,7 +408,11 @@
#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT )
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_RESERVED (0xe0820820)
#define ADC_SQR2_FIRST (5)
#define ADC_SQR2_LAST (9)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
@ -385,18 +425,27 @@
#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */
#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT )
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT)
#define ADC_SQR3_RESERVED (0xe0820820)
#define ADC_SQR3_FIRST (10)
#define ADC_SQR3_LAST (14)
#define ADC_SQR3_SQ_OFFSET (0)
/* ADC regular sequence register 4 */
#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 14th conversion in regular sequence */
#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */
#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT)
#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 15th conversion in regular sequence */
#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */
#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT)
#define ADC_SQR4_RESERVED (0xfffff820)
#define ADC_SQR4_FIRST (15)
#define ADC_SQR4_LAST (16)
#define ADC_SQR4_SQ_OFFSET (0)
/* ADC regular data register */
#define ADC_DR_MASK (0xffff)
#define ADC_DR_RDATA_SHIFT (0)
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/* ADC injected sequence register */
@ -405,7 +454,34 @@
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT) /* Event = 0..15 */
# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT)
# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
@ -437,96 +513,97 @@
/* ADC injected data register 1, 2, 3, and 4 */
#define ADC_JDR_MASK (0xffff)
#define ADC_JDR_JDATA_SHIFT (0)
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
/* ADC analog watchdog 2 configuration register */
#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT)
# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */
#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT)
# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */
/* ADC analog watchdog 3 configuration register */
#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT)
# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */
#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT)
# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */
/* ADC differential mode selection register 2 */
#define ADC_DIFSEL_
#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT)
# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */
#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT)
# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */
/* ADC calibration factors */
#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */
#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT)
#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */
#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT)
#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */
#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT)
#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */
#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT)
/* Common status register */
#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */
#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */
#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */
#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */
#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */
#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */
#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */
#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */
#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */
#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */
#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */
#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */
#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */
#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */
#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */
#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */
#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */
#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */
#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */
#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */
#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */
#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */
#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */
#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */
#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */
#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */
#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */
#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */
#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */
#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */
#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */
#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */
#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */
#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */
#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */
#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */
#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */
#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */
#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */
#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */
#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */
#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */
#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */
#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */
/* Common control register */
#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */
#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT)
# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */
# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */
# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */
# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */
# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */
# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */
# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)
# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
# define ADC_CCR_MDMA_ 10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */
#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT)
# define ADC_CCR_CKMODE_ASYCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */
# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */
# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */
# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */
#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT)
# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */
# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */
# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */
# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */
# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */
# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */
# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)
# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */
#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT)
# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */
# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */
# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */
# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
/* Common regular data register for dual mode */
#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */
#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT)
#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */
#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */
#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT)
#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */
#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
/****************************************************************************************************
* Public Types

54
arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
View File

@ -68,6 +68,59 @@
* pins in this file.
*/
/* ADC */
#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
#define GPIO_ADC12_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC12_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC12_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC12_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC12_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2)
#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13)
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
#define GPIO_ADC3_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
#define GPIO_ADC4_IN1 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14)
#define GPIO_ADC4_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15)
#define GPIO_ADC4_IN3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
#define GPIO_ADC4_IN4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
#define GPIO_ADC4_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
#define GPIO_ADC4_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
#define GPIO_ADC4_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
#define GPIO_ADC34_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
#define GPIO_ADC34_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
#define GPIO_ADC34_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
#define GPIO_ADC34_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
#define GPIO_ADC34_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
#define GPIO_ADC34_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
/* CAN */
#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
@ -603,4 +656,3 @@
#define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H */

1
arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
View File

@ -187,6 +187,7 @@
#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIO Port G */
#define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */
#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */
#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIO Port J */
#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022Bff: GPIO Port K */
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */

4
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
View File

@ -641,9 +641,9 @@
#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9)
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN15)
#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)

2
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
View File

@ -317,6 +317,8 @@
#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */
#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */

34
arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h
View File

@ -114,6 +114,7 @@
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
@ -283,6 +284,22 @@
#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
#define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
#define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
#define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
#define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
#define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
#define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
#define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
#define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
#define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
#define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
#define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
#define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
#define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
#define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
#define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
#define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
#define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
#define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
#define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
@ -302,13 +319,20 @@
#define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
#define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
#define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
#ifdef CONFIG_STM32_STM32F429
# define GPIO_FSMC_SDCKE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FSMC_SDNE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_FSMC_SDNWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
# define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
# define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
# define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
# define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
# define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
# define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
# define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)

1802
arch/arm/src/stm32/stm32_adc.c
View File

File diff suppressed because it is too large Load Diff

1137
arch/arm/src/stm32/stm32_adc.h
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -511,7 +511,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -526,7 +526,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;

2
arch/arm/src/stm32/stm32_can.c
View File

@ -554,7 +554,7 @@ static void can_reset(FAR struct can_dev_s *dev)
/* Disable interrupts momentary to stop any ongoing CAN event processing and
* to prevent any concurrent access to the AHB1RSTR register.
*/
*/
flags = irqsave();

6
arch/arm/src/stm32/stm32_dumpgpio.c
View File

@ -58,8 +58,12 @@
#ifdef CONFIG_DEBUG
static const char g_portchar[STM32_NGPIO_PORTS] =
{
#if STM32_NGPIO_PORTS > 9
#if STM32_NGPIO_PORTS > 11
# error "Additional support required for this number of GPIOs"
#elif STM32_NGPIO_PORTS > 10
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
#elif STM32_NGPIO_PORTS > 9
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
#elif STM32_NGPIO_PORTS > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32_NGPIO_PORTS > 7

6
arch/arm/src/stm32/stm32_gpio.c
View File

@ -117,6 +117,12 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
#if STM32_NGPIO_PORTS > 8
STM32_GPIOI_BASE,
#endif
#if STM32_NGPIO_PORTS > 9
STM32_GPIOJ_BASE,
#endif
#if STM32_NGPIO_PORTS > 10
STM32_GPIOK_BASE,
#endif
#endif /* CONFIG_STM32_STM32L15XX */
};

4
arch/arm/src/stm32/stm32_idle.c
View File

@ -60,8 +60,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

8
arch/arm/src/stm32/stm32_mpuinit.c
View File

@ -95,10 +95,10 @@ void stm32_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -117,7 +117,7 @@ void stm32_mpuinitialize(void)
void stm32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

2
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -3882,7 +3882,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
/* If this is a connection on the root hub, then we need to go to
* little more effort to get the device speed. If it is a connection
* on an external hub, then we already have that information.
*/
*/
#ifdef CONFIG_USBHOST_HUB
if (ROOTHUB(hport))

2
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -3882,7 +3882,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
/* If this is a connection on the root hub, then we need to go to
* little more effort to get the device speed. If it is a connection
* on an external hub, then we already have that information.
*/
*/
#ifdef CONFIG_USBHOST_HUB
if (ROOTHUB(hport))

1183
arch/arm/src/stm32/stm32_pwm.c
View File

File diff suppressed because it is too large Load Diff

839
arch/arm/src/stm32/stm32_pwm.h
View File

@ -2,7 +2,9 @@
* arch/arm/src/stm32/stm32_pwm.h
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -96,6 +98,15 @@
#ifndef CONFIG_STM32_TIM14
# undef CONFIG_STM32_TIM14_PWM
#endif
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_PWM
#endif
#ifndef CONFIG_STM32_TIM16
# undef CONFIG_STM32_TIM16_PWM
#endif
#ifndef CONFIG_STM32_TIM17
# undef CONFIG_STM32_TIM17_PWM
#endif
/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
@ -109,11 +120,597 @@
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM)
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
#include <arch/board/board.h>
#include "chip/stm32_tim.h"
#ifdef CONFIG_PWM_MULTICHAN
#ifdef CONFIG_STM32_TIM1_CHANNEL1
# ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# else
# define PWM_TIM1_CH1CFG 0
# endif
# define PWM_TIM1_CHANNEL1 1
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL2
# ifdef CONFIG_STM32_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# else
# define PWM_TIM1_CH2CFG 0
# endif
# define PWM_TIM1_CHANNEL2 1
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL3
# ifdef CONFIG_STM32_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# else
# define PWM_TIM1_CH3CFG 0
# endif
# define PWM_TIM1_CHANNEL3 1
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL4
# ifdef CONFIG_STM32_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# define PWM_TIM1_CH4CFG 0
# endif
# define PWM_TIM1_CHANNEL4 1
#else
# define PWM_TIM1_CHANNEL4 0
#endif
#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
#ifdef CONFIG_STM32_TIM2_CHANNEL1
# ifdef CONFIG_STM32_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# else
# define PWM_TIM2_CH1CFG 0
# endif
# define PWM_TIM2_CHANNEL1 1
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL2
# ifdef CONFIG_STM32_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# else
# define PWM_TIM2_CH2CFG 0
# endif
# define PWM_TIM2_CHANNEL2 1
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL3
# ifdef CONFIG_STM32_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# else
# define PWM_TIM2_CH3CFG 0
# endif
# define PWM_TIM2_CHANNEL3 1
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL4
# ifdef CONFIG_STM32_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# define PWM_TIM2_CH4CFG 0
# endif
# define PWM_TIM2_CHANNEL4 1
#else
# define PWM_TIM2_CHANNEL4 0
#endif
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32_TIM3_CHANNEL1
# ifdef CONFIG_STM32_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# else
# define PWM_TIM3_CH1CFG 0
# endif
# define PWM_TIM3_CHANNEL1 1
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL2
# ifdef CONFIG_STM32_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# else
# define PWM_TIM3_CH2CFG 0
# endif
# define PWM_TIM3_CHANNEL2 1
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL3
# ifdef CONFIG_STM32_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# else
# define PWM_TIM3_CH3CFG 0
# endif
# define PWM_TIM3_CHANNEL3 1
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL4
# ifdef CONFIG_STM32_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# define PWM_TIM3_CH4CFG 0
# endif
# define PWM_TIM3_CHANNEL4 1
#else
# define PWM_TIM3_CHANNEL4 0
#endif
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32_TIM4_CHANNEL1
# ifdef CONFIG_STM32_TIM4_CH1OUT
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# else
# define PWM_TIM4_CH1CFG 0
# endif
# define PWM_TIM4_CHANNEL1 1
#else
# define PWM_TIM4_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL2
# ifdef CONFIG_STM32_TIM4_CH2OUT
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# else
# define PWM_TIM4_CH2CFG 0
# endif
# define PWM_TIM4_CHANNEL2 1
#else
# define PWM_TIM4_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL3
# ifdef CONFIG_STM32_TIM4_CH3OUT
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# else
# define PWM_TIM4_CH3CFG 0
# endif
# define PWM_TIM4_CHANNEL3 1
#else
# define PWM_TIM4_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL4
# ifdef CONFIG_STM32_TIM4_CH4OUT
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# define PWM_TIM4_CH4CFG 0
# endif
# define PWM_TIM4_CHANNEL4 1
#else
# define PWM_TIM4_CHANNEL4 0
#endif
#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
#ifdef CONFIG_STM32_TIM5_CHANNEL1
# ifdef CONFIG_STM32_TIM5_CH1OUT
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# else
# define PWM_TIM5_CH1CFG 0
# endif
# define PWM_TIM5_CHANNEL1 1
#else
# define PWM_TIM5_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL2
# ifdef CONFIG_STM32_TIM5_CH2OUT
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# else
# define PWM_TIM5_CH2CFG 0
# endif
# define PWM_TIM5_CHANNEL2 1
#else
# define PWM_TIM5_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL3
# ifdef CONFIG_STM32_TIM5_CH3OUT
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# else
# define PWM_TIM5_CH3CFG 0
# endif
# define PWM_TIM5_CHANNEL3 1
#else
# define PWM_TIM5_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL4
# ifdef CONFIG_STM32_TIM5_CH4OUT
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# define PWM_TIM5_CH4CFG 0
# endif
# define PWM_TIM5_CHANNEL4 1
#else
# define PWM_TIM5_CHANNEL4 0
#endif
#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
#ifdef CONFIG_STM32_TIM8_CHANNEL1
# ifdef CONFIG_STM32_TIM8_CH1OUT
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# else
# define PWM_TIM8_CH1CFG 0
# endif
# define PWM_TIM8_CHANNEL1 1
#else
# define PWM_TIM8_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL2
# ifdef CONFIG_STM32_TIM8_CH2OUT
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# else
# define PWM_TIM8_CH2CFG 0
# endif
# define PWM_TIM8_CHANNEL2 1
#else
# define PWM_TIM8_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL3
# ifdef CONFIG_STM32_TIM8_CH3OUT
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# else
# define PWM_TIM8_CH3CFG 0
# endif
# define PWM_TIM8_CHANNEL3 1
#else
# define PWM_TIM8_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL4
# ifdef CONFIG_STM32_TIM8_CH4OUT
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# define PWM_TIM8_CH4CFG 0
# endif
# define PWM_TIM8_CHANNEL4 1
#else
# define PWM_TIM8_CHANNEL4 0
#endif
#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
#ifdef CONFIG_STM32_TIM9_CHANNEL1
# ifdef CONFIG_STM32_TIM9_CH1OUT
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
# else
# define PWM_TIM9_CH1CFG 0
# endif
# define PWM_TIM9_CHANNEL1 1
#else
# define PWM_TIM9_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL2
# ifdef CONFIG_STM32_TIM9_CH2OUT
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
# else
# define PWM_TIM9_CH2CFG 0
# endif
# define PWM_TIM9_CHANNEL2 1
#else
# define PWM_TIM9_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL3
# ifdef CONFIG_STM32_TIM9_CH3OUT
# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT
# else
# define PWM_TIM9_CH3CFG 0
# endif
# define PWM_TIM9_CHANNEL3 1
#else
# define PWM_TIM9_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL4
# ifdef CONFIG_STM32_TIM9_CH4OUT
# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT
# else
# define PWM_TIM9_CH4CFG 0
# endif
# define PWM_TIM9_CHANNEL4 1
#else
# define PWM_TIM9_CHANNEL4 0
#endif
#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2 + \
PWM_TIM9_CHANNEL3 + PWM_TIM9_CHANNEL4)
#ifdef CONFIG_STM32_TIM10_CHANNEL1
# ifdef CONFIG_STM32_TIM10_CH1OUT
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
# else
# define PWM_TIM10_CH1CFG 0
# endif
# define PWM_TIM10_CHANNEL1 1
#else
# define PWM_TIM10_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL2
# ifdef CONFIG_STM32_TIM10_CH2OUT
# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT
# else
# define PWM_TIM10_CH2CFG 0
# endif
# define PWM_TIM10_CHANNEL2 1
#else
# define PWM_TIM10_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL3
# ifdef CONFIG_STM32_TIM10_CH3OUT
# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT
# else
# define PWM_TIM10_CH3CFG 0
# endif
# define PWM_TIM10_CHANNEL3 1
#else
# define PWM_TIM10_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL4
# ifdef CONFIG_STM32_TIM10_CH4OUT
# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT
# else
# define PWM_TIM10_CH4CFG 0
# endif
# define PWM_TIM10_CHANNEL4 1
#else
# define PWM_TIM10_CHANNEL4 0
#endif
#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1 + PWM_TIM10_CHANNEL2 + \
PWM_TIM10_CHANNEL3 + PWM_TIM10_CHANNEL4)
#ifdef CONFIG_STM32_TIM11_CHANNEL1
# ifdef CONFIG_STM32_TIM11_CH1OUT
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
# else
# define PWM_TIM11_CH1CFG 0
# endif
# define PWM_TIM11_CHANNEL1 1
#else
# define PWM_TIM11_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL2
# ifdef CONFIG_STM32_TIM11_CH2OUT
# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT
# else
# define PWM_TIM11_CH2CFG 0
# endif
# define PWM_TIM11_CHANNEL2 1
#else
# define PWM_TIM11_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL3
# ifdef CONFIG_STM32_TIM11_CH3OUT
# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT
# else
# define PWM_TIM11_CH3CFG 0
# endif
# define PWM_TIM11_CHANNEL3 1
#else
# define PWM_TIM11_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL4
# ifdef CONFIG_STM32_TIM11_CH4OUT
# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT
# else
# define PWM_TIM11_CH4CFG 0
# endif
# define PWM_TIM11_CHANNEL4 1
#else
# define PWM_TIM11_CHANNEL4 0
#endif
#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1 + PWM_TIM11_CHANNEL2 + \
PWM_TIM11_CHANNEL3 + PWM_TIM11_CHANNEL4)
#ifdef CONFIG_STM32_TIM12_CHANNEL1
# ifdef CONFIG_STM32_TIM12_CH1OUT
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
# else
# define PWM_TIM12_CH1CFG 0
# endif
# define PWM_TIM12_CHANNEL1 1
#else
# define PWM_TIM12_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL2
# ifdef CONFIG_STM32_TIM12_CH2OUT
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
# else
# define PWM_TIM12_CH2CFG 0
# endif
# define PWM_TIM12_CHANNEL2 1
#else
# define PWM_TIM12_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL3
# ifdef CONFIG_STM32_TIM12_CH3OUT
# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT
# else
# define PWM_TIM12_CH3CFG 0
# endif
# define PWM_TIM12_CHANNEL3 1
#else
# define PWM_TIM12_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL4
# ifdef CONFIG_STM32_TIM12_CH4OUT
# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT
# else
# define PWM_TIM12_CH4CFG 0
# endif
# define PWM_TIM12_CHANNEL4 1
#else
# define PWM_TIM12_CHANNEL4 0
#endif
#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2 + \
PWM_TIM12_CHANNEL3 + PWM_TIM12_CHANNEL4)
#ifdef CONFIG_STM32_TIM13_CHANNEL1
# ifdef CONFIG_STM32_TIM13_CH1OUT
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
# else
# define PWM_TIM13_CH1CFG 0
# endif
# define PWM_TIM13_CHANNEL1 1
#else
# define PWM_TIM13_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL2
# ifdef CONFIG_STM32_TIM13_CH2OUT
# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT
# else
# define PWM_TIM13_CH2CFG 0
# endif
# define PWM_TIM13_CHANNEL2 1
#else
# define PWM_TIM13_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL3
# ifdef CONFIG_STM32_TIM13_CH3OUT
# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT
# else
# define PWM_TIM13_CH3CFG 0
# endif
# define PWM_TIM13_CHANNEL3 1
#else
# define PWM_TIM13_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL4
# ifdef CONFIG_STM32_TIM13_CH4OUT
# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT
# else
# define PWM_TIM13_CH4CFG 0
# endif
# define PWM_TIM13_CHANNEL4 1
#else
# define PWM_TIM13_CHANNEL4 0
#endif
#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1 + PWM_TIM13_CHANNEL2 + \
PWM_TIM13_CHANNEL3 + PWM_TIM13_CHANNEL4)
#ifdef CONFIG_STM32_TIM14_CHANNEL1
# ifdef CONFIG_STM32_TIM14_CH1OUT
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# else
# define PWM_TIM14_CH1CFG 0
# endif
# define PWM_TIM14_CHANNEL1 1
#else
# define PWM_TIM14_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL2
# ifdef CONFIG_STM32_TIM14_CH2OUT
# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT
# else
# define PWM_TIM14_CH2CFG 0
# endif
# define PWM_TIM14_CHANNEL2 1
#else
# define PWM_TIM14_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL3
# ifdef CONFIG_STM32_TIM14_CH3OUT
# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT
# else
# define PWM_TIM14_CH3CFG 0
# endif
# define PWM_TIM14_CHANNEL3 1
#else
# define PWM_TIM14_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL4
# ifdef CONFIG_STM32_TIM14_CH4OUT
# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT
# else
# define PWM_TIM14_CH4CFG 0
# endif
# define PWM_TIM14_CHANNEL4 1
#else
# define PWM_TIM14_CHANNEL4 0
#endif
#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1 + PWM_TIM14_CHANNEL2 + \
PWM_TIM14_CHANNEL3 + PWM_TIM14_CHANNEL4)
#ifdef CONFIG_STM32_TIM15_CHANNEL1
# ifdef CONFIG_STM32_TIM15_CH1OUT
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# else
# define PWM_TIM15_CH1CFG 0
# endif
# define PWM_TIM15_CHANNEL1 1
#else
# define PWM_TIM15_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM15_CHANNEL2
# ifdef CONFIG_STM32_TIM15_CH2OUT
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# define PWM_TIM15_CH2CFG 0
# endif
# define PWM_TIM15_CHANNEL2 1
#else
# define PWM_TIM15_CHANNEL2 0
#endif
#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
#ifdef CONFIG_STM32_TIM16_CHANNEL1
# ifdef CONFIG_STM32_TIM16_CH1OUT
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# define PWM_TIM16_CH1CFG 0
# endif
# define PWM_TIM16_CHANNEL1 1
#else
# define PWM_TIM16_CHANNEL1 0
#endif
#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
#ifdef CONFIG_STM32_TIM17_CHANNEL1
# ifdef CONFIG_STM32_TIM17_CH1OUT
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# define PWM_TIM17_CH1CFG 0
# endif
# define PWM_TIM17_CHANNEL1 1
#else
# define PWM_TIM17_CHANNEL1 0
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b))
#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \
PWM_MAX(PWM_TIM2_NCHANNELS, \
PWM_MAX(PWM_TIM3_NCHANNELS, \
PWM_MAX(PWM_TIM4_NCHANNELS, \
PWM_MAX(PWM_TIM5_NCHANNELS, \
PWM_MAX(PWM_TIM8_NCHANNELS, \
PWM_MAX(PWM_TIM9_NCHANNELS, \
PWM_MAX(PWM_TIM10_NCHANNELS, \
PWM_MAX(PWM_TIM11_NCHANNELS, \
PWM_MAX(PWM_TIM12_NCHANNELS, \
PWM_MAX(PWM_TIM13_NCHANNELS, \
PWM_MAX(PWM_TIM14_NCHANNELS, \
PWM_MAX(PWM_TIM15_NCHANNELS, \
PWM_MAX(PWM_TIM16_NCHANNELS, \
PWM_TIM17_NCHANNELS))))))))))))))
#else
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
*
@ -131,13 +728,21 @@
# if !defined(CONFIG_STM32_TIM1_CHANNEL)
# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32_TIM1_CHANNEL == 1
# define PWM_TIM1_PINCFG GPIO_TIM1_CH1OUT
# define CONFIG_STM32_TIM1_CHANNEL1 1
# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 2
# define PWM_TIM1_PINCFG GPIO_TIM1_CH2OUT
# define CONFIG_STM32_TIM1_CHANNEL2 1
# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 3
# define PWM_TIM1_PINCFG GPIO_TIM1_CH3OUT
# define CONFIG_STM32_TIM1_CHANNEL3 1
# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 4
# define PWM_TIM1_PINCFG GPIO_TIM1_CH4OUT
# define CONFIG_STM32_TIM1_CHANNEL4 1
# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
# endif
@ -147,13 +752,21 @@
# if !defined(CONFIG_STM32_TIM2_CHANNEL)
# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32_TIM2_CHANNEL == 1
# define PWM_TIM2_PINCFG GPIO_TIM2_CH1OUT
# define CONFIG_STM32_TIM2_CHANNEL1 1
# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 2
# define PWM_TIM2_PINCFG GPIO_TIM2_CH2OUT
# define CONFIG_STM32_TIM2_CHANNEL2 1
# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 3
# define PWM_TIM2_PINCFG GPIO_TIM2_CH3OUT
# define CONFIG_STM32_TIM2_CHANNEL3 1
# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 4
# define PWM_TIM2_PINCFG GPIO_TIM2_CH4OUT
# define CONFIG_STM32_TIM2_CHANNEL4 1
# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
# endif
@ -163,13 +776,21 @@
# if !defined(CONFIG_STM32_TIM3_CHANNEL)
# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32_TIM3_CHANNEL == 1
# define PWM_TIM3_PINCFG GPIO_TIM3_CH1OUT
# define CONFIG_STM32_TIM3_CHANNEL1 1
# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 2
# define PWM_TIM3_PINCFG GPIO_TIM3_CH2OUT
# define CONFIG_STM32_TIM3_CHANNEL2 1
# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 3
# define PWM_TIM3_PINCFG GPIO_TIM3_CH3OUT
# define CONFIG_STM32_TIM3_CHANNEL3 1
# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 4
# define PWM_TIM3_PINCFG GPIO_TIM3_CH4OUT
# define CONFIG_STM32_TIM3_CHANNEL4 1
# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
# endif
@ -179,13 +800,21 @@
# if !defined(CONFIG_STM32_TIM4_CHANNEL)
# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32_TIM4_CHANNEL == 1
# define PWM_TIM4_PINCFG GPIO_TIM4_CH1OUT
# define CONFIG_STM32_TIM4_CHANNEL1 1
# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 2
# define PWM_TIM4_PINCFG GPIO_TIM4_CH2OUT
# define CONFIG_STM32_TIM4_CHANNEL2 1
# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 3
# define PWM_TIM4_PINCFG GPIO_TIM4_CH3OUT
# define CONFIG_STM32_TIM4_CHANNEL3 1
# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 4
# define PWM_TIM4_PINCFG GPIO_TIM4_CH4OUT
# define CONFIG_STM32_TIM4_CHANNEL4 1
# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
# endif
@ -195,13 +824,21 @@
# if !defined(CONFIG_STM32_TIM5_CHANNEL)
# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32_TIM5_CHANNEL == 1
# define PWM_TIM5_PINCFG GPIO_TIM5_CH1OUT
# define CONFIG_STM32_TIM5_CHANNEL1 1
# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 2
# define PWM_TIM5_PINCFG GPIO_TIM5_CH2OUT
# define CONFIG_STM32_TIM5_CHANNEL2 1
# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 3
# define PWM_TIM5_PINCFG GPIO_TIM5_CH3OUT
# define CONFIG_STM32_TIM5_CHANNEL3 1
# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 4
# define PWM_TIM5_PINCFG GPIO_TIM5_CH4OUT
# define CONFIG_STM32_TIM5_CHANNEL4 1
# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
# endif
@ -211,13 +848,21 @@
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32_TIM8_CHANNEL == 1
# define PWM_TIM8_PINCFG GPIO_TIM8_CH1OUT
# define CONFIG_STM32_TIM8_CHANNEL1 1
# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 2
# define PWM_TIM8_PINCFG GPIO_TIM8_CH2OUT
# define CONFIG_STM32_TIM8_CHANNEL2 1
# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 3
# define PWM_TIM8_PINCFG GPIO_TIM8_CH3OUT
# define CONFIG_STM32_TIM8_CHANNEL3 1
# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 4
# define PWM_TIM8_PINCFG GPIO_TIM8_CH4OUT
# define CONFIG_STM32_TIM8_CHANNEL4 1
# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
# endif
@ -227,13 +872,21 @@
# if !defined(CONFIG_STM32_TIM9_CHANNEL)
# error "CONFIG_STM32_TIM9_CHANNEL must be provided"
# elif CONFIG_STM32_TIM9_CHANNEL == 1
# define PWM_TIM9_PINCFG GPIO_TIM9_CH1OUT
# define CONFIG_STM32_TIM9_CHANNEL1 1
# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 2
# define PWM_TIM9_PINCFG GPIO_TIM9_CH2OUT
# define CONFIG_STM32_TIM9_CHANNEL2 1
# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 3
# define PWM_TIM9_PINCFG GPIO_TIM9_CH3OUT
# define CONFIG_STM32_TIM9_CHANNEL3 1
# define CONFIG_STM32_TIM9_CH3MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 4
# define PWM_TIM9_PINCFG GPIO_TIM9_CH4OUT
# define CONFIG_STM32_TIM9_CHANNEL4 1
# define CONFIG_STM32_TIM9_CH4MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL"
# endif
@ -243,13 +896,21 @@
# if !defined(CONFIG_STM32_TIM10_CHANNEL)
# error "CONFIG_STM32_TIM10_CHANNEL must be provided"
# elif CONFIG_STM32_TIM10_CHANNEL == 1
# define PWM_TIM10_PINCFG GPIO_TIM10_CH1OUT
# define CONFIG_STM32_TIM10_CHANNEL1 1
# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 2
# define PWM_TIM10_PINCFG GPIO_TIM10_CH2OUT
# define CONFIG_STM32_TIM10_CHANNEL2 1
# define CONFIG_STM32_TIM10_CH2MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 3
# define PWM_TIM10_PINCFG GPIO_TIM10_CH3OUT
# define CONFIG_STM32_TIM10_CHANNEL3 1
# define CONFIG_STM32_TIM10_CH3MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 4
# define PWM_TIM10_PINCFG GPIO_TIM10_CH4OUT
# define CONFIG_STM32_TIM10_CHANNEL4 1
# define CONFIG_STM32_TIM10_CH4MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL"
# endif
@ -259,13 +920,21 @@
# if !defined(CONFIG_STM32_TIM11_CHANNEL)
# error "CONFIG_STM32_TIM11_CHANNEL must be provided"
# elif CONFIG_STM32_TIM11_CHANNEL == 1
# define PWM_TIM11_PINCFG GPIO_TIM11_CH1OUT
# define CONFIG_STM32_TIM11_CHANNEL1 1
# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 2
# define PWM_TIM11_PINCFG GPIO_TIM11_CH2OUT
# define CONFIG_STM32_TIM11_CHANNEL2 1
# define CONFIG_STM32_TIM11_CH2MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 3
# define PWM_TIM11_PINCFG GPIO_TIM11_CH3OUT
# define CONFIG_STM32_TIM11_CHANNEL3 1
# define CONFIG_STM32_TIM11_CH3MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 4
# define PWM_TIM11_PINCFG GPIO_TIM11_CH4OUT
# define CONFIG_STM32_TIM11_CHANNEL4 1
# define CONFIG_STM32_TIM11_CH4MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL"
# endif
@ -275,13 +944,21 @@
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32_TIM12_CHANNEL == 1
# define PWM_TIM12_PINCFG GPIO_TIM12_CH1OUT
# define CONFIG_STM32_TIM12_CHANNEL1 1
# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 2
# define PWM_TIM12_PINCFG GPIO_TIM12_CH2OUT
# define CONFIG_STM32_TIM12_CHANNEL2 1
# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 3
# define PWM_TIM12_PINCFG GPIO_TIM12_CH3OUT
# define CONFIG_STM32_TIM12_CHANNEL3 1
# define CONFIG_STM32_TIM12_CH3MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 4
# define PWM_TIM12_PINCFG GPIO_TIM12_CH4OUT
# define CONFIG_STM32_TIM12_CHANNEL4 1
# define CONFIG_STM32_TIM12_CH4MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
# endif
@ -291,13 +968,21 @@
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32_TIM13_CHANNEL == 1
# define PWM_TIM13_PINCFG GPIO_TIM13_CH1OUT
# define CONFIG_STM32_TIM13_CHANNEL1 1
# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 2
# define PWM_TIM13_PINCFG GPIO_TIM13_CH2OUT
# define CONFIG_STM32_TIM13_CHANNEL2 1
# define CONFIG_STM32_TIM13_CH2MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 3
# define PWM_TIM13_PINCFG GPIO_TIM13_CH3OUT
# define CONFIG_STM32_TIM13_CHANNEL3 1
# define CONFIG_STM32_TIM13_CH3MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 4
# define PWM_TIM13_PINCFG GPIO_TIM13_CH4OUT
# define CONFIG_STM32_TIM13_CHANNEL4 1
# define CONFIG_STM32_TIM13_CH4MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
# endif
@ -307,18 +992,70 @@
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32_TIM14_CHANNEL == 1
# define PWM_TIM14_PINCFG GPIO_TIM14_CH1OUT
# define CONFIG_STM32_TIM14_CHANNEL1 1
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 2
# define PWM_TIM14_PINCFG GPIO_TIM14_CH2OUT
# define CONFIG_STM32_TIM14_CHANNEL2 1
# define CONFIG_STM32_TIM14_CH2MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 3
# define PWM_TIM14_PINCFG GPIO_TIM14_CH3OUT
# define CONFIG_STM32_TIM14_CHANNEL3 1
# define CONFIG_STM32_TIM14_CH3MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 4
# define PWM_TIM14_PINCFG GPIO_TIM14_CH4OUT
# define CONFIG_STM32_TIM14_CHANNEL4 1
# define CONFIG_STM32_TIM14_CH4MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM15_PWM
# if !defined(CONFIG_STM32_TIM15_CHANNEL)
# error "CONFIG_STM32_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32_TIM15_CHANNEL == 1
# define CONFIG_STM32_TIM15_CHANNEL1 1
# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# elif CONFIG_STM32_TIM15_CHANNEL == 2
# define CONFIG_STM32_TIM15_CHANNEL2 1
# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM16_PWM
# if !defined(CONFIG_STM32_TIM16_CHANNEL)
# error "CONFIG_STM32_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32_TIM16_CHANNEL == 1
# define CONFIG_STM32_TIM16_CHANNEL1 1
# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM17_PWM
# if !defined(CONFIG_STM32_TIM17_CHANNEL)
# error "CONFIG_STM32_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32_TIM17_CHANNEL == 1
# define CONFIG_STM32_TIM17_CHANNEL1 1
# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL"
# endif
#endif
#define PWM_NCHANNELS 1
#endif
/************************************************************************************
* Public Types
************************************************************************************/
@ -351,7 +1088,7 @@ extern "C"
* Input Parameters:
* timer - A number identifying the timer use. The number of valid timer
* IDs varies with the STM32 MCU and MCU family but is somewhere in
* the range of {1,..,14}.
* the range of {1,..,17}.
*
* Returned Value:
* On success, a pointer to the STM32 lower half PWM driver is returned.

65
arch/arm/src/stm32/stm32_qencoder.c
View File

@ -145,6 +145,65 @@
# define HAVE_MIXEDWIDTH_TIMERS 1
#endif
/* Input filter *********************************************************************/
#ifdef CONFIG_STM32_QENCODER_FILTER
# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
# endif
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
# endif
# endif
# ifndef STM32_QENCODER_ICF
# warning "Invalid encoder filter combination, filter disabled"
# endif
#endif
#ifndef STM32_QENCODER_ICF
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
#endif
/* Debug ****************************************************************************/
/* Non-standard debug that may be enabled just for testing the quadrature encoder */
@ -809,7 +868,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT;
ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC1F_SHIFT;
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT;
/* Select the Polarity=rising and set the CC1E Bit */
@ -844,7 +903,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT;
ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC2F_SHIFT;
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT;
/* Select the Polarity=rising and set the CC2E Bit */
@ -963,7 +1022,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
*/
*/
/* Disable further interrupts and stop the timer */

2
arch/arm/src/stm32/stm32_sdio.c
View File

@ -1332,7 +1332,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Is the RX FIFO half full or more? Is so then we must be
* processing a receive transaction.
*/
*/
if ((pending & SDIO_STA_RXFIFOHF) != 0)
{

47
arch/arm/src/stm32/stm32_tim.c
View File

@ -145,6 +145,49 @@
# undef CONFIG_STM32_TIM14
#endif
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
*/
@ -245,6 +288,9 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
stm32_tim_disable(dev);
}
#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
{
/* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
@ -258,6 +304,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
stm32_unconfiggpio(cfg);
}
}
#endif
/************************************************************************************
* Basic Functions

10
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -159,6 +159,12 @@ static inline void rcc_enableahb1(void)
#endif
#if STM32_NGPIO > 128
| RCC_AHB1ENR_GPIOIEN
#endif
#if STM32_NGPIO > 144
|RCC_AHB1ENR_GPIOJEN
#endif
#if STM32_NGPIO > 160
|RCC_AHB1ENR_GPIOKEN
#endif
);
#endif
@ -751,12 +757,16 @@ static void stm32_stdclockconfig(void)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIR
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
putreg32(regval, STM32_RCC_PLLSAICFGR);
regval = getreg32(STM32_RCC_DCKCFGR);
regval &= ~RCC_DCKCFGR_PLLSAIDIVR_MASK;
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
putreg32(regval, STM32_RCC_DCKCFGR);

4
arch/arm/src/stm32f7/stm32_allocateheap.c
View File

@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -255,7 +255,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;

8
arch/arm/src/stm32f7/stm32_mpuinit.c
View File

@ -87,10 +87,10 @@ void stm32_mpuinitialize(void)
/* Configure user flash and SRAM space */
mpu_userflash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_userintsram(datastart, dataend - datastart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
@ -109,7 +109,7 @@ void stm32_mpuinitialize(void)
void stm32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_userintsram(start, size);
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */

6
arch/arm/src/str71x/str71x_decodeirq.c
View File

@ -90,7 +90,7 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
lowsyslog(LOG_ERR, "Unexpected IRQ\n");
current_regs = regs;
PANIC();
@ -101,7 +101,7 @@ void up_decodeirq(uint32_t *regs)
* info from CIC register without the setup).
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
irq = getreg32(STR71X_EIC_IVR);
/* Verify that the resulting IRQ number is valid */
@ -138,6 +138,6 @@ void up_decodeirq(uint32_t *regs)
PANIC(); /* Normally never happens */
}
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
}

229
arch/arm/src/str71x/str71x_head.S
View File

@ -37,11 +37,11 @@
* Included Files
*****************************************************************************/
#include <nuttx/config.h> /* NuttX configuration settings */
#include <nuttx/config.h> /* NuttX configuration settings */
#include <arch/board/board.h> /* Board-specific settings */
#include "arm.h" /* ARM-specific settings */
#include "chip.h" /* Chip-specific settings */
#include "arm.h" /* ARM-specific settings */
#include "chip.h" /* Chip-specific settings */
#include "up_internal.h"
#include "up_arch.h"
@ -59,18 +59,18 @@
* External references
*****************************************************************************/
.globl str71x_prccuinit /* Clock initialization */
.globl up_lowsetup /* Early initialization of UART */
.globl str71x_prccuinit /* Clock initialization */
.globl up_lowsetup /* Early initialization of UART */
#ifdef USE_EARLYSERIALINIT
.globl up_earlyserialinit /* Early initialization of serial driver */
.globl up_earlyserialinit /* Early initialization of serial driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl board_led_initialize /* Boot LED setup */
.globl board_autoled_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG
.globl up_lowputc /* Low-level debug output */
.globl up_lowputc /* Low-level debug output */
#endif
.globl os_start /* NuttX entry point */
.globl os_start /* NuttX entry point */
/*****************************************************************************
* Macros
@ -87,8 +87,8 @@
.macro showprogress, code
#ifdef CONFIG_DEBUG
mov r0, #\code
bl up_lowputc
mov r0, #\code
bl up_lowputc
#endif
.endm
@ -107,32 +107,32 @@
/* In order to use the external memory, certain GPIO pins must be
* configured in the alternate function:
*
* GPIO ALT Description
* GPIO ALT Description
* P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4
* P2.4-7 A.20-23 External memory extended address bus (needed for
* address space > 1Mb)
*/
#ifdef CONFIG_STR71X_BIGEXTMEM
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
#else
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
#endif
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
/* Enable bank 0 */
ldr \base, =STR71X_EMI_BASE
ldr \base, =STR71X_EMI_BASE
#ifdef CONFIG_STR71X_BANK0
@ -156,11 +156,11 @@
# define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
/* Enable bank 1 */
@ -186,11 +186,11 @@
# define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
/* Enable bank 2 */
@ -216,11 +216,11 @@
# define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
/* Enable bank 3 */
@ -246,11 +246,11 @@
# define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
#endif
.endm
@ -277,42 +277,42 @@
.macro eicinit, eicbase, value, irqno, offset
/* Disable and clear all interrupts */
ldr \eicbase, =STR71X_EIC_BASE
ldr \eicbase, =STR71X_EIC_BASE
/* Disable FIQ and IRQ */
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
/* Disable all channel interrupts */
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
/* Clear all pending IRQs */
ldr \value, =0xffffffff
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
ldr \value, =0xffffffff
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
/* Disable FIQ channels/clear pending FIQs */
mov \value, #0x0c
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
mov \value, #0x0c
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
/* Reset the current priority register */
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
/* Zero IVR 31:16 */
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
/* Set up the loop to initialize each SIR register. Start
* with IRQ number 0 and SIR0
*/
mov \irqno, #0
ldr \offset, =STR71X_EIC_SIR_OFFSET
mov \irqno, #0
ldr \offset, =STR71X_EIC_SIR_OFFSET
/* Then loop for each EIC channel */
eicloop:
@ -325,22 +325,22 @@ eicloop:
* are all disabled.
*/
mov \value, \irqno, lsl #16
str \value, [\eicbase, \offset]
mov \value, \irqno, lsl #16
str \value, [\eicbase, \offset]
/* Increment the offset to the next SIR register and inrement
* the IRQ number.
*/
add \offset, \offset, #4
add \irqno, \irqno, #1
add \offset, \offset, #4
add \irqno, \irqno, #1
/* Continue to loop until all of the SIR registers have been
* initializeed.
*/
cmp \irqno, #STR71X_EIC_NCHANNELS
blt eicloop
cmp \irqno, #STR71X_EIC_NCHANNELS
blt eicloop
.endm
/*****************************************************************************
@ -355,25 +355,26 @@ eicloop:
#ifndef CONFIG_STR71X_DISABLE_PERIPHINIT
/* Set up APB1 and APB2 addresses */
ldr \base1, =STR71X_APB1_BASE
ldr \base2, =STR71X_APB2_BASE
ldr \base1, =STR71X_APB1_BASE
ldr \base2, =STR71X_APB2_BASE
/* Disable all APB1 peripherals */
ldr \value, =STR71X_APB1_APB1ALL
ldr \value, =STR71X_APB1_APB1ALL
strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET]
/* Disable all(or most) APB2 peripherals */
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET]
/* Allow EMI and USB */
ldr \base1, =STR71X_RCCU_BASE
ldr \base1, =STR71X_RCCU_BASE
#ifdef CONFIG_STR71X_USB
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
#else
ldr \value, =STR71X_RCCUPER_EMI
ldr \value, =STR71X_RCCUPER_EMI
#endif
strh \value, [\base1, #STR71X_RCCU_PER_OFFSET]
#endif
@ -391,15 +392,16 @@ eicloop:
*****************************************************************************/
.macro remap, base, value
/* Read the PCU BOOTCR register */
ldr \base, =STR71X_PCU_BASE
ldr \base, =STR71X_PCU_BASE
ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET]
/* Mask out the old boot mode bits and set the boot mode to FLASH */
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
/* Save the modified BOOTCR register */
@ -426,16 +428,16 @@ eicloop:
.globl _vector_table
.type _vector_table, %function
_vector_table:
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
.long 0 /* 0x14: Reserved vector */
ldr pc, .Lirqhandler /* 0x18: IRQ */
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
.long 0 /* 0x14: Reserved vector */
ldr pc, .Lirqhandler /* 0x18: IRQ */
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
.globl __start
.globl __start
.globl up_vectorundefinsn
.globl up_vectorswi
.globl up_vectorprefetch
@ -444,7 +446,7 @@ _vector_table:
.globl up_vectorfiq
.Lresethandler:
.long __start
.long __start
.Lundefinedhandler:
.long up_vectorundefinsn
.Lswihandler:
@ -478,16 +480,16 @@ __start:
* the aliased copy
*/
ldr pc, =__flashstart
ldr pc, =__flashstart
__flashstart:
.rept 9
nop /* Wait for OSC stabilization*/
nop /* Wait for OSC stabilization */
.endr
/* Setup the initial processor mode */
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Initialize the external memory interface (EMI) */
@ -499,7 +501,7 @@ __flashstart:
/* Disable all peripherals except EIC */
periphinit r0, r1, r2
periphinit r0, r1, r2
/* Map memory appropriately for configuration */
@ -507,42 +509,42 @@ __flashstart:
/* Setup system stack (and get the BSS range) */
adr r0, LC0
ldmia r0, {r4, r5, sp}
adr r0, LC0
ldmia r0, {r4, r5, sp}
/* Clear system BSS section */
mov r0, #0
1: cmp r4, r5
mov r0, #0
1: cmp r4, r5
strcc r0, [r4], #4
bcc 1b
bcc 1b
/* Copy system .data sections from FLASH to new home in RAM. */
adr r3, LC2
adr r3, LC2
ldmia r3, {r0, r1, r2}
2: ldmia r0!, {r3 - r10}
stmia r1!, {r3 - r10}
cmp r1, r2
blt 2b
cmp r1, r2
blt 2b
/* Initialize clocking */
bl str71x_prccuinit
bl str71x_prccuinit
/* Configure the uart so that we can get debug output as soon
* as possible.
*/
bl up_lowsetup
bl up_lowsetup
showprogress 'A'
/* Perform early serial initialization */
mov fp, #0
mov fp, #0
#ifdef USE_EARLYSERIALINIT
bl up_earlyserialinit
bl up_earlyserialinit
#endif
showprogress 'B'
@ -550,17 +552,17 @@ __flashstart:
/* Call C++ constructors */
#ifdef CONFIG_CPLUSPLUS
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b ctor_loop
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b ctor_loop
ctor_end:
showprogress 'C'
@ -570,27 +572,27 @@ ctor_end:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */
b os_start
b os_start
/* Call destructors -- never get here */
#if 0 /* CONFIG_CPLUSPLUS */
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
dtor_loop:
cmp r0, r1
beq dtor_end
ldr r2, [r0], #4
cmp r0, r1
beq dtor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b dtor_loop
b dtor_loop
dtor_end:
#endif
@ -626,4 +628,3 @@ g_idle_topstack:
.size g_idle_topstack, .-g_idle_topstack
.end

4
arch/arm/src/tiva/tiva_allocateheap.c
View File

@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

Some files were not shown because too many files have changed in this diff Show More