From ef5f3dcff442d1c45c5792edf57975425003e3e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Oct 2015 19:21:35 -0600 Subject: [PATCH 01/41] SAM3/4 RTC: Fix a bungled change from a recent commit --- arch/arm/src/sam34/sam_rtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 1ad734789b..aebad747bf 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -783,9 +783,8 @@ int up_rtc_gettime(FAR struct timespec *tp) rtt_val = getreg32(SAM_RTT_VR); } while (rtc_cal != getreg32(SAM_RTC_CALR) || - rtc_tim != getreg32(SAM_RTC_TIMR)); - - (rtt_val != getreg32(SAM_RTT_VR))); + rtc_tim != getreg32(SAM_RTC_TIMR) || + rtt_val != getreg32(SAM_RTT_VR)); t.tm_sec = rtc_bcd2bin((rtc_tim & RTC_TIMR_SEC_MASK) >> RTC_TIMR_SEC_SHIFT); t.tm_min = rtc_bcd2bin((rtc_tim & RTC_TIMR_MIN_MASK) >> RTC_TIMR_MIN_SHIFT); From d90f597a055816d488de884473091fc0f92cda08 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Oct 2015 09:09:26 -0600 Subject: [PATCH 02/41] More spacing/alignment issues --- arch/arm/src/efm32/efm32_pwm.c | 2 +- arch/arm/src/efm32/efm32_usbhost.c | 2 +- arch/arm/src/imx/imx_irq.c | 2 +- arch/arm/src/stm32/stm32_can.c | 2 +- arch/arm/src/stm32/stm32_otgfshost.c | 2 +- arch/arm/src/stm32/stm32_otghshost.c | 2 +- arch/arm/src/stm32/stm32_pwm.c | 2 +- arch/arm/src/stm32/stm32_qencoder.c | 2 +- arch/arm/src/stm32/stm32_sdio.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 343dba865c..3a02c14698 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -808,7 +808,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) /* Disable interrupts momentary to stop any ongoing timer processing and * to prevent any concurrent access to the reset register. - */ + */ flags = irqsave(); diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 022ccd3553..f3a116f484 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -3949,7 +3949,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn, /* If this is a connection on the root hub, then we need to go to * little more effort to get the device speed. If it is a connection * on an external hub, then we already have that information. - */ + */ #ifdef CONFIG_USBHOST_HUB if (ROOTHUB(hport)) diff --git a/arch/arm/src/imx/imx_irq.c b/arch/arm/src/imx/imx_irq.c index fbecd098c7..13c1a958c9 100644 --- a/arch/arm/src/imx/imx_irq.c +++ b/arch/arm/src/imx/imx_irq.c @@ -87,7 +87,7 @@ void up_irqinitialize(void) /* Set masking of normal interrupts by priority. Writing all ones * (or -1) to the NIMASK register sets the normal interrupt mask to * -1 and does not disable any normal interrupt priority levels. - */ + */ #ifndef CONFIG_SUPPRESS_INTERRUPTS putreg32(-1, IMX_AITC_NIMASK); /* -1: No priority levels masked */ diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index 5bc7676fac..0ff25877d2 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -554,7 +554,7 @@ static void can_reset(FAR struct can_dev_s *dev) /* Disable interrupts momentary to stop any ongoing CAN event processing and * to prevent any concurrent access to the AHB1RSTR register. - */ + */ flags = irqsave(); diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 46aba7e752..431d438ed7 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -3882,7 +3882,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn, /* If this is a connection on the root hub, then we need to go to * little more effort to get the device speed. If it is a connection * on an external hub, then we already have that information. - */ + */ #ifdef CONFIG_USBHOST_HUB if (ROOTHUB(hport)) diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index e5b1a3117c..78e9909eca 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -3882,7 +3882,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn, /* If this is a connection on the root hub, then we need to go to * little more effort to get the device speed. If it is a connection * on an external hub, then we already have that information. - */ + */ #ifdef CONFIG_USBHOST_HUB if (ROOTHUB(hport)) diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 2d914a1e8d..4f6c8e2284 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -1407,7 +1407,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) /* Disable interrupts momentary to stop any ongoing timer processing and * to prevent any concurrent access to the reset register. - */ + */ flags = irqsave(); diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index d53c10857e..e081276136 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -963,7 +963,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower) /* Disable interrupts momentary to stop any ongoing timer processing and * to prevent any concurrent access to the reset register. - */ + */ /* Disable further interrupts and stop the timer */ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index f0d42db95d..99170a7784 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -1332,7 +1332,7 @@ static int stm32_interrupt(int irq, void *context) { /* Is the RX FIFO half full or more? Is so then we must be * processing a receive transaction. - */ + */ if ((pending & SDIO_STA_RXFIFOHF) != 0) { From a20a61caef42b88b2eec4cfd3f2169e98fd901e8 Mon Sep 17 00:00:00 2001 From: Max Kriegler Date: Fri, 9 Oct 2015 10:32:46 -0600 Subject: [PATCH 03/41] STM32 F4: Correct pin mapping for TIM12 Channel 2 --- arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h index 733959fba4..92cf9a4467 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h @@ -641,9 +641,9 @@ #define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) #define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) #define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN15) +#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) #define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9) -#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN15) +#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) #define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) #define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) From 253e112b4ae51435cfc488f9e97a0119d896b698 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Fri, 9 Oct 2015 11:46:23 -0400 Subject: [PATCH 04/41] STM32: Fix some incorrect configurations in Kconfig file --- arch/arm/src/stm32/Kconfig | 339 ++++++++++++++++++++++++++++++++++--- 1 file changed, 315 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 0c95f920d7..48e01e0efa 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -190,24 +190,40 @@ config ARCH_CHIP_STM32F100C8 select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100CB bool "STM32F100CB" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100R8 bool "STM32F100R8" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100RB bool "STM32F100RB" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100RC bool "STM32F100RC" @@ -215,6 +231,10 @@ config ARCH_CHIP_STM32F100RC select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100RD bool "STM32F100RD" @@ -222,6 +242,10 @@ config ARCH_CHIP_STM32F100RD select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100RE bool "STM32F100RE" @@ -229,18 +253,30 @@ config ARCH_CHIP_STM32F100RE select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100V8 bool "STM32F100V8" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100VB bool "STM32F100VB" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_VALUELINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100VC bool "STM32F100VC" @@ -248,6 +284,10 @@ config ARCH_CHIP_STM32F100VC select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100VD bool "STM32F100VD" @@ -255,6 +295,10 @@ config ARCH_CHIP_STM32F100VD select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F100VE bool "STM32F100VE" @@ -262,6 +306,10 @@ config ARCH_CHIP_STM32F100VE select STM32_STM32F10XX select STM32_VALUELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F102CB bool "STM32F102CB" @@ -269,6 +317,8 @@ config ARCH_CHIP_STM32F102CB select STM32_STM32F10XX select STM32_USBACCESSLINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103T8 bool "STM32F103T8" @@ -276,6 +326,7 @@ config ARCH_CHIP_STM32F103T8 select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103TB bool "STM32F103TB" @@ -283,6 +334,7 @@ config ARCH_CHIP_STM32F103TB select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103C4 bool "STM32F103C4" @@ -297,6 +349,8 @@ config ARCH_CHIP_STM32F103C8 select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103CB bool "STM32F103CB" @@ -304,6 +358,8 @@ config ARCH_CHIP_STM32F103CB select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103R8 bool "STM32F103R8" @@ -311,6 +367,8 @@ config ARCH_CHIP_STM32F103R8 select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103RB bool "STM32F103RB" @@ -318,6 +376,8 @@ config ARCH_CHIP_STM32F103RB select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103RC bool "STM32F103RC" @@ -325,6 +385,10 @@ config ARCH_CHIP_STM32F103RC select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103RD bool "STM32F103RD" @@ -332,6 +396,10 @@ config ARCH_CHIP_STM32F103RD select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103RE bool "STM32F103RE" @@ -339,6 +407,10 @@ config ARCH_CHIP_STM32F103RE select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103RG bool "STM32F103RG" @@ -346,6 +418,10 @@ config ARCH_CHIP_STM32F103RG select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103V8 bool "STM32F103V8" @@ -353,6 +429,8 @@ config ARCH_CHIP_STM32F103V8 select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103VB bool "STM32F103VB" @@ -360,6 +438,8 @@ config ARCH_CHIP_STM32F103VB select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103VC bool "STM32F103VC" @@ -367,6 +447,10 @@ config ARCH_CHIP_STM32F103VC select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103VE bool "STM32F103VE" @@ -374,6 +458,10 @@ config ARCH_CHIP_STM32F103VE select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F103ZE bool "STM32F103ZE" @@ -381,18 +469,29 @@ config ARCH_CHIP_STM32F103ZE select STM32_STM32F10XX select STM32_PERFORMANCELINE select STM32_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F105VB bool "STM32F105VBT7" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F107VC bool "STM32F107VC" select ARCH_CORTEXM3 select STM32_STM32F10XX select STM32_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM4 config ARCH_CHIP_STM32F205RG bool "STM32F205RG" @@ -416,121 +515,247 @@ config ARCH_CHIP_STM32F302K6 bool "STM32F302K6" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_I2C3 config ARCH_CHIP_STM32F302K8 bool "STM32F302K8" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_I2C3 config ARCH_CHIP_STM32F302CB bool "STM32F302CB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 config ARCH_CHIP_STM32F302CC bool "STM32F302CC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 config ARCH_CHIP_STM32F302RB bool "STM32F302RB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 config ARCH_CHIP_STM32F302RC bool "STM32F302RC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 config ARCH_CHIP_STM32F302VB bool "STM32F302VB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 config ARCH_CHIP_STM32F302VC bool "STM32F302VC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F302 select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 config ARCH_CHIP_STM32F303K6 bool "STM32F303K6" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303K8 bool "STM32F303K8" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU config ARCH_CHIP_STM32F303C6 bool "STM32F303C6" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_USART3 config ARCH_CHIP_STM32F303C8 bool "STM32F303C8" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_USART3 config ARCH_CHIP_STM32F303CB bool "STM32F303CB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303CC bool "STM32F303CC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303RB bool "STM32F303RB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303RC bool "STM32F303RC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303RD bool "STM32F303RD" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303RE bool "STM32F303RE" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303VB bool "STM32F303VB" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F303VC bool "STM32F303VC" select ARCH_CORTEXM4 select STM32_STM32F30XX + select STM32_STM32F303 select ARCH_HAVE_FPU + select STM32_HAVE_ADC3 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32F372C8 bool "STM32F372C8" @@ -882,8 +1107,13 @@ endchoice config STM32_STM32L15XX bool default n + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY config STM32_ENERGYLITE @@ -904,6 +1134,7 @@ config STM32_STM32F10XX select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM3 config STM32_VALUELINE bool @@ -1025,6 +1256,8 @@ config STM32_STM32F205 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1039,6 +1272,10 @@ config STM32_STM32F205 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 select STM32_HAVE_RNG select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -1053,6 +1290,8 @@ config STM32_STM32F207 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1067,6 +1306,10 @@ config STM32_STM32F207 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 select STM32_HAVE_RNG select STM32_HAVE_ETHMAC select STM32_HAVE_SPI2 @@ -1075,25 +1318,38 @@ config STM32_STM32F207 config STM32_STM32F30XX bool default n - select STM32_HAVE_USBDEV - select STM32_HAVE_CCM + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_CAN1 + +config STM32_STM32F302 + bool + default n + select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_USBDEV + +config STM32_STM32F303 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 config STM32_STM32F37XX bool default n select STM32_HAVE_USBDEV + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1101,14 +1357,21 @@ config STM32_STM32F37XX select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 select STM32_HAVE_USART3 config STM32_STM32F40XX bool default n select STM32_HAVE_OTGFS + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 config STM32_STM32F401 bool @@ -1119,8 +1382,6 @@ config STM32_STM32F401 select STM32_HAVE_TIM9 select STM32_HAVE_TIM10 select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 config STM32_STM32F411 bool @@ -1131,8 +1392,6 @@ config STM32_STM32F411 select STM32_HAVE_TIM9 select STM32_HAVE_TIM10 select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 select STM32_HAVE_SPI4 select STM32_HAVE_SPI5 @@ -1160,6 +1419,8 @@ config STM32_STM32F405 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 select STM32_HAVE_RNG config STM32_STM32F407 @@ -1186,6 +1447,8 @@ config STM32_STM32F407 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 select STM32_HAVE_RNG select STM32_HAVE_ETHMAC @@ -1216,10 +1479,10 @@ config STM32_STM32F427 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 select STM32_HAVE_RNG select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 select STM32_HAVE_SPI4 select STM32_HAVE_SPI5 select STM32_HAVE_SPI6 @@ -1250,10 +1513,10 @@ config STM32_STM32F429 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 select STM32_HAVE_RNG select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 select STM32_HAVE_SPI4 select STM32_HAVE_SPI5 select STM32_HAVE_SPI6 @@ -1279,8 +1542,8 @@ config STM32_STM32F446 select STM32_HAVE_ADC3 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 select STM32_HAVE_SPI4 config STM32_DFU @@ -1340,6 +1603,14 @@ config STM32_HAVE_TIM1 bool default n +config STM32_HAVE_TIM3 + bool + default n + +config STM32_HAVE_TIM4 + bool + default n + config STM32_HAVE_TIM5 bool default n @@ -1428,6 +1699,14 @@ config STM32_HAVE_CAN2 bool default n +config STM32_HAVE_DAC1 + bool + default n + +config STM32_HAVE_DAC2 + bool + default n + config STM32_HAVE_RNG bool default n @@ -1436,6 +1715,14 @@ config STM32_HAVE_ETHMAC bool default n +config STM32_HAVE_I2C2 + bool + default n + +config STM32_HAVE_I2C3 + bool + default n + config STM32_HAVE_SPI2 bool default n @@ -1457,12 +1744,12 @@ config STM32_HAVE_SPI6 default n config STM32_HAVE_SAIPLL - bool - default n + bool + default n config STM32_HAVE_I2SPLL - bool - default n + bool + default n # These are the peripheral selections proper @@ -1563,11 +1850,13 @@ config STM32_DMA2 config STM32_DAC1 bool "DAC1" default n + depends on STM32_HAVE_DAC1 select STM32_DAC config STM32_DAC2 bool "DAC2" default n + depends on STM32_HAVE_DAC2 select STM32_DAC config STM32_DCMI @@ -1600,13 +1889,13 @@ config STM32_I2C1 config STM32_I2C2 bool "I2C2" default n - depends on !(STM32_STM32F10XX && STM32_LOWDENSITY) + depends on STM32_HAVE_I2C2 select STM32_I2C config STM32_I2C3 bool "I2C3" default n - depends on STM32_STM32F207 || STM32_STM32F40XX + depends on STM32_HAVE_I2C3 select STM32_I2C config STM32_LTDC @@ -1715,10 +2004,12 @@ config STM32_TIM2 config STM32_TIM3 bool "TIM3" default n + depends on STM32_HAVE_TIM3 config STM32_TIM4 bool "TIM4" default n + depends on STM32_HAVE_TIM4 config STM32_TIM5 bool "TIM5" From 08175bef589be1ee73aba66606e367748721cf6f Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Fri, 9 Oct 2015 17:20:42 -0400 Subject: [PATCH 05/41] STM32 PWM: Add ifdef for STM32F30XX --- arch/arm/src/stm32/stm32_pwm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 4f6c8e2284..a3a1645688 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -1312,8 +1312,8 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) #if defined(CONFIG_STM32_STM32F10XX) pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) pincfg |= (GPIO_INPUT | GPIO_FLOAT); #else # error "Unrecognized STM32 chip" From 4a46a872bd7827446b49680c4912094cf20efb27 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 12 Oct 2015 08:18:03 -0600 Subject: [PATCH 06/41] arch/mips: fix some spacing and alignment issues --- arch/mips/src/common/up_allocateheap.c | 2 +- arch/mips/src/common/up_createstack.c | 2 +- arch/mips/src/common/up_exit.c | 4 +- arch/mips/src/common/up_idle.c | 1 - arch/mips/src/common/up_usestack.c | 2 +- arch/mips/src/mips32/up_assert.c | 6 +- arch/mips/src/mips32/up_blocktask.c | 18 ++--- arch/mips/src/mips32/up_doirq.c | 4 +- arch/mips/src/mips32/up_dumpstate.c | 4 +- arch/mips/src/mips32/up_releasepending.c | 6 +- arch/mips/src/mips32/up_reprioritizertr.c | 6 +- arch/mips/src/mips32/up_schedulesigaction.c | 2 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/mips32/up_swint0.c | 10 +-- arch/mips/src/mips32/up_unblocktask.c | 18 ++--- arch/mips/src/pic32mx/pic32mx-decodeirq.c | 8 +- arch/mips/src/pic32mx/pic32mx-ethernet.c | 26 +++--- arch/mips/src/pic32mx/pic32mx-gpioirq.c | 10 +-- arch/mips/src/pic32mx/pic32mx-lowinit.c | 4 +- arch/mips/src/pic32mx/pic32mx-serial.c | 88 ++++++++++----------- arch/mips/src/pic32mx/pic32mx-spi.c | 8 +- arch/mips/src/pic32mx/pic32mx-timerisr.c | 2 +- arch/mips/src/pic32mx/pic32mx-usbdev.c | 40 +++++----- arch/mips/src/pic32mz/pic32mz-decodeirq.c | 8 +- arch/mips/src/pic32mz/pic32mz-ethernet.c | 23 +++--- arch/mips/src/pic32mz/pic32mz-lowinit.c | 2 +- arch/mips/src/pic32mz/pic32mz-serial.c | 88 ++++++++++----------- arch/mips/src/pic32mz/pic32mz-spi.c | 4 +- arch/mips/src/pic32mz/pic32mz-timerisr.c | 2 +- 29 files changed, 201 insertions(+), 199 deletions(-) diff --git a/arch/mips/src/common/up_allocateheap.c b/arch/mips/src/common/up_allocateheap.c index fba1c84786..1e99b86cee 100644 --- a/arch/mips/src/common/up_allocateheap.c +++ b/arch/mips/src/common/up_allocateheap.c @@ -83,6 +83,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c index 12f1da65a7..541633683b 100644 --- a/arch/mips/src/common/up_createstack.c +++ b/arch/mips/src/common/up_createstack.c @@ -203,7 +203,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) /* Save the adjusted stack values in the struct tcb_s */ - tcb->adj_stack_ptr = (uint32_t*)top_of_stack; + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; tcb->adj_stack_size = size_of_stack; board_led_on(LED_STACKCREATED); diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c index 0126aa4447..550dae0ab1 100644 --- a/arch/mips/src/common/up_exit.c +++ b/arch/mips/src/common/up_exit.c @@ -140,7 +140,7 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) void _exit(int status) { - struct tcb_s* tcb; + struct tcb_s *tcb; /* Disable interrupts. They will be restored when the next * task is started. @@ -163,7 +163,7 @@ void _exit(int status) * head of the list. */ - tcb = (struct tcb_s*)g_readytorun.head; + tcb = (struct tcb_s *)g_readytorun.head; #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously running diff --git a/arch/mips/src/common/up_idle.c b/arch/mips/src/common/up_idle.c index 4e2cc542be..0962c5b107 100644 --- a/arch/mips/src/common/up_idle.c +++ b/arch/mips/src/common/up_idle.c @@ -104,4 +104,3 @@ void up_idle(void) #endif #endif } - diff --git a/arch/mips/src/common/up_usestack.c b/arch/mips/src/common/up_usestack.c index 72721a3185..b4e3098fc4 100644 --- a/arch/mips/src/common/up_usestack.c +++ b/arch/mips/src/common/up_usestack.c @@ -145,7 +145,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) /* Save the adjusted stack values in the struct tcb_s */ - tcb->adj_stack_ptr = (uint32_t*)top_of_stack; + tcb->adj_stack_ptr = (uint32_t *)top_of_stack; tcb->adj_stack_size = size_of_stack; return OK; diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index 29cd6d737d..3ddb82a87d 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -105,10 +105,10 @@ static void _up_assert(int errorcode) { /* Are we in an interrupt handler or the idle task? */ - if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0) + if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0) { (void)irqsave(); - for (;;) + for (; ; ) { #ifdef CONFIG_ARCH_LEDS board_led_on(LED_PANIC); @@ -160,7 +160,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) void up_assert(const uint8_t *filename, int lineno) { #ifdef CONFIG_PRINT_TASKNAME - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif board_led_on(LED_ASSERTION); diff --git a/arch/mips/src/mips32/up_blocktask.c b/arch/mips/src/mips32/up_blocktask.c index d4438fd74b..1cccff6f97 100644 --- a/arch/mips/src/mips32/up_blocktask.c +++ b/arch/mips/src/mips32/up_blocktask.c @@ -77,7 +77,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; bool switch_needed; /* Verify that the context switch can be performed */ @@ -129,7 +129,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (struct tcb_s *)g_readytorun.head; /* Reset scheduler parameters */ @@ -150,16 +150,16 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) * run list. */ - struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head; #ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - */ + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ - (void)group_addrenv(nexttcb); + (void)group_addrenv(nexttcb); #endif /* Reset scheduler parameters */ diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index e81557b2d0..6c55ed9cc9 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -110,7 +110,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - up_restorefpu((uint32_t*)current_regs); + up_restorefpu((uint32_t *)current_regs); #endif #ifdef CONFIG_ARCH_ADDRENV @@ -131,7 +131,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) * switch occurred during interrupt processing. */ - regs = (uint32_t*)current_regs; + regs = (uint32_t *)current_regs; /* Set current_regs to NULL to indicate that we are no longer in an * interrupt handler. diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c index 0ed660cfa7..eaa45246e2 100644 --- a/arch/mips/src/mips32/up_dumpstate.c +++ b/arch/mips/src/mips32/up_dumpstate.c @@ -100,7 +100,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { - uint32_t *ptr = (uint32_t*)stack; + uint32_t *ptr = (uint32_t *)stack; lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); @@ -154,7 +154,7 @@ static inline void up_registerdump(void) void up_dumpstate(void) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; uint32_t sp = up_getsp(); uint32_t ustackbase; uint32_t ustacksize; diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c index 5d4d7c8240..bea7a2e904 100644 --- a/arch/mips/src/mips32/up_releasepending.c +++ b/arch/mips/src/mips32/up_releasepending.c @@ -67,7 +67,7 @@ void up_release_pending(void) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; slldbg("From TCB=%p\n", rtcb); @@ -98,7 +98,7 @@ void up_release_pending(void) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (struct tcb_s *)g_readytorun.head; /* Update scheduler parameters */ @@ -119,7 +119,7 @@ void up_release_pending(void) * ready to run list. */ - struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head; #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c index 53e2806d7a..506241b2f0 100644 --- a/arch/mips/src/mips32/up_reprioritizertr.c +++ b/arch/mips/src/mips32/up_reprioritizertr.c @@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) } else { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; bool switch_needed; slldbg("TCB=%p PRI=%d\n", tcb, priority); @@ -152,7 +152,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (struct tcb_s *)g_readytorun.head; /* Update scheduler parameters */ @@ -173,7 +173,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) * ready to run list. */ - struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head; #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously diff --git a/arch/mips/src/mips32/up_schedulesigaction.c b/arch/mips/src/mips32/up_schedulesigaction.c index f3e58a5f49..064a68ac9f 100644 --- a/arch/mips/src/mips32/up_schedulesigaction.c +++ b/arch/mips/src/mips32/up_schedulesigaction.c @@ -122,7 +122,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs); - if (tcb == (struct tcb_s*)g_readytorun.head) + if (tcb == (struct tcb_s *)g_readytorun.head) { /* CASE 1: We are not in an interrupt handler and * a task is signalling itself for some reason. diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index c2631bab32..74c2c5b170 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -83,7 +83,7 @@ void up_sigdeliver(void) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; uint32_t regs[XCPTCONTEXT_REGS]; sig_deliver_t sigdeliver; diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c index 51b8afc75b..0981ac66e8 100644 --- a/arch/mips/src/mips32/up_swint0.c +++ b/arch/mips/src/mips32/up_swint0.c @@ -157,7 +157,7 @@ static void dispatch_syscall(void) int up_swint0(int irq, FAR void *context) { - uint32_t *regs = (uint32_t*)context; + uint32_t *regs = (uint32_t *)context; uint32_t cause; DEBUGASSERT(regs && regs == current_regs); @@ -194,7 +194,7 @@ int up_swint0(int irq, FAR void *context) case SYS_restore_context: { DEBUGASSERT(regs[REG_A1] != 0); - current_regs = (uint32_t*)regs[REG_A1]; + current_regs = (uint32_t *)regs[REG_A1]; } break; @@ -217,8 +217,8 @@ int up_swint0(int irq, FAR void *context) case SYS_switch_context: { DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0); - up_copystate((uint32_t*)regs[REG_A1], regs); - current_regs = (uint32_t*)regs[REG_A2]; + up_copystate((uint32_t *)regs[REG_A1], regs); + current_regs = (uint32_t *)regs[REG_A2]; } break; @@ -301,7 +301,7 @@ int up_swint0(int irq, FAR void *context) if (regs != current_regs) { swidbg("SWInt Return: Context switch!\n"); - up_registerdump((const uint32_t*)current_regs); + up_registerdump((const uint32_t *)current_regs); } else { diff --git a/arch/mips/src/mips32/up_unblocktask.c b/arch/mips/src/mips32/up_unblocktask.c index aba3a6e43b..2fb84f4773 100644 --- a/arch/mips/src/mips32/up_unblocktask.c +++ b/arch/mips/src/mips32/up_unblocktask.c @@ -73,7 +73,7 @@ void up_unblock_task(struct tcb_s *tcb) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; /* Verify that the context switch can be performed */ @@ -112,7 +112,7 @@ void up_unblock_task(struct tcb_s *tcb) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (struct tcb_s *)g_readytorun.head; /* Update scheduler parameters */ @@ -134,16 +134,16 @@ void up_unblock_task(struct tcb_s *tcb) * g_readytorun task list. */ - struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head; #ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - */ + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ - (void)group_addrenv(nexttcb); + (void)group_addrenv(nexttcb); #endif /* Update scheduler parameters */ diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c index 8a47094800..f9cf81d467 100644 --- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c +++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c @@ -105,7 +105,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) */ #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS - savestate = (uint32_t*)current_regs; + savestate = (uint32_t *)current_regs; #else DEBUGASSERT(current_regs == NULL); #endif @@ -113,7 +113,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) /* Loop while there are pending interrupts with priority greater than zero */ - for (;;) + for (; ; ) { /* Read the INTSTAT register. This register contains both the priority * and the interrupt vector number. @@ -146,7 +146,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) * switch occurred during interrupt processing. */ - regs = (uint32_t*)current_regs; + regs = (uint32_t *)current_regs; #if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) /* Check for a context switch. If a context switch occurred, then @@ -161,7 +161,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - up_restorefpu((uint32_t*)current_regs); + up_restorefpu((uint32_t *)current_regs); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 4ba2baef78..fbc6634333 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -676,7 +676,7 @@ static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv) { /* Add the buffer to the end of the list of free buffers */ - sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); /* Get the address of the next buffer */ @@ -702,7 +702,7 @@ static uint8_t *pic32mx_allocbuffer(struct pic32mx_driver_s *priv) { /* Return the next free buffer from the head of the free buffer list */ - return (uint8_t*)sq_remfirst(&priv->pd_freebuffers); + return (uint8_t *)sq_remfirst(&priv->pd_freebuffers); } /**************************************************************************** @@ -723,7 +723,7 @@ static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, uint8_t *buffer) { /* Add the buffer to the end of the free buffer list */ - sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); } /**************************************************************************** @@ -1377,7 +1377,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) * the producer index is not equal to the consumer index. */ - for (;;) + for (; ; ) { /* Check if any RX descriptor has the EOWN bit cleared meaning that the * this descriptor is now under software control and a message was @@ -1420,14 +1420,16 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) else if (priv->pd_dev.d_len > CONFIG_NET_ETH_MTU) { - nlldbg("Too big. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); + nlldbg("Too big. packet length: %d rxdesc: %08x\n", + priv->pd_dev.d_len, rxdesc->status); EMAC_STAT(priv, rx_pktsize); pic32mx_rxreturn(rxdesc); } /* We don't have any logic here for reassembling packets from fragments. */ - else if ((rxdesc->status & (RXDESC_STATUS_EOP|RXDESC_STATUS_SOP)) != (RXDESC_STATUS_EOP|RXDESC_STATUS_SOP)) + else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) != + (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) { nlldbg("Fragment. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); EMAC_STAT(priv, rx_fragment); @@ -1439,7 +1441,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) /* Get the Rx buffer address from the Rx descriptor */ - priv->pd_dev.d_buf = (uint8_t*)VIRT_ADDR(rxdesc->address); + priv->pd_dev.d_buf = (uint8_t *)VIRT_ADDR(rxdesc->address); DEBUGASSERT(priv->pd_dev.d_buf != NULL); /* Replace the buffer in the RX descriptor with a new one */ @@ -2030,9 +2032,9 @@ static int pic32mx_ifup(struct net_driver_s *dev) pic32mx_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), PIC32MX_EMAC1_SUPPCLR); #endif - /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, - * and then clear the reset bit. - */ + /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, + * and then clear the reset bit. + */ regval = pic32mx_getreg(PIC32MX_EMAC1_MCFG); pic32mx_putreg(EMAC1_MCFG_MGMTRST, PIC32MX_EMAC1_MCFGSET); @@ -2138,7 +2140,7 @@ static int pic32mx_ifup(struct net_driver_s *dev) /* Continue Ethernet Controller Initialization ****************************/ /* If planning to turn on the flow control, update the PTV value - *(ETHCON1:16-31). + * (ETHCON1:16-31). */ /* If using the auto-flow control, set the full and empty watermarks: RXFWM @@ -3204,7 +3206,7 @@ static inline int pic32mx_ethinitialize(int intf) priv->pd_dev.d_addmac = pic32mx_addmac; /* Add multicast MAC address */ priv->pd_dev.d_rmmac = pic32mx_rmmac; /* Remove multicast MAC address */ #endif - priv->pd_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + priv->pd_dev.d_private = (void *)priv; /* Used to recover private state from dev */ #if CONFIG_PIC32MX_NINTERFACES > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" diff --git a/arch/mips/src/pic32mx/pic32mx-gpioirq.c b/arch/mips/src/pic32mx/pic32mx-gpioirq.c index 8509d2d494..f07a97ecaa 100644 --- a/arch/mips/src/pic32mx/pic32mx-gpioirq.c +++ b/arch/mips/src/pic32mx/pic32mx-gpioirq.c @@ -240,12 +240,12 @@ xcpt_t pic32mx_gpioattach(uint32_t pinset, unsigned int cn, xcpt_t handler) } else { - /* Make sure that any further interrupts are disabled. - * (disable the pull-up as well). - */ + /* Make sure that any further interrupts are disabled. + * (disable the pull-up as well). + */ - putreg32(1 << cn, PIC32MX_IOPORT_CNENCLR); - putreg32(1 << cn, PIC32MX_IOPORT_CNPUECLR); + putreg32(1 << cn, PIC32MX_IOPORT_CNENCLR); + putreg32(1 << cn, PIC32MX_IOPORT_CNPUECLR); } /* Set the new handler (perhaps NULLifying the current handler) */ diff --git a/arch/mips/src/pic32mx/pic32mx-lowinit.c b/arch/mips/src/pic32mx/pic32mx-lowinit.c index 251c52a87d..8587a20a55 100644 --- a/arch/mips/src/pic32mx/pic32mx-lowinit.c +++ b/arch/mips/src/pic32mx/pic32mx-lowinit.c @@ -162,7 +162,7 @@ static inline void pic32mx_cache(void) putreg32(regval, PIC32MX_CHE_CON); #endif - /* Enable cache on KSEG 0 in the CP0 CONFIG register*/ + /* Enable cache on KSEG 0 in the CP0 CONFIG register */ asm("\tmfc0 %0,$16,0\n" : "=r"(regval)); regval &= ~CP0_CONFIG_K23_MASK; @@ -193,7 +193,7 @@ void pic32mx_lowinit(void) /* Enable caching */ - pic32mx_cache();; + pic32mx_cache(); /* Initialize a console (probably a serial console) */ diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c index c24161ed8d..f706bace0f 100644 --- a/arch/mips/src/pic32mx/pic32mx-serial.c +++ b/arch/mips/src/pic32mx/pic32mx-serial.c @@ -329,7 +329,7 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -353,7 +353,7 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Configure the UART as an RS-232 UART */ @@ -381,7 +381,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable interrupts */ @@ -409,7 +409,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Attach the IRQ */ @@ -428,7 +428,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable interrupts */ @@ -475,7 +475,7 @@ static int up_interrupt(int irq, void *context) { PANIC(); } - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; DEBUGASSERT(priv); /* Loop until there are no characters to be transferred or, @@ -513,23 +513,23 @@ static int up_interrupt(int irq, void *context) if (up_pending_irq(priv->irqrx)) { - /* Process incoming bytes */ + /* Process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; - /* Clear the pending RX interrupt if the receive buffer is empty. - * Note that interrupts can be lost if the interrupt condition is - * still true when the interrupt is cleared. Keeping the RX - * interrupt pending too long is not a problem because the - * upper half driver will disable RX interrupts if it no - * longer has space to buffer the serial data. - */ + /* Clear the pending RX interrupt if the receive buffer is empty. + * Note that interrupts can be lost if the interrupt condition is + * still true when the interrupt is cleared. Keeping the RX + * interrupt pending too long is not a problem because the + * upper half driver will disable RX interrupts if it no + * longer has space to buffer the serial data. + */ - if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_URXDA) == 0) - { - up_clrpend_irq(priv->irqrx); - } + if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_URXDA) == 0) + { + up_clrpend_irq(priv->irqrx); + } } /* Handle outgoing, transmit bytes The RT FIFO is configured to @@ -549,23 +549,23 @@ static int up_interrupt(int irq, void *context) if (up_pending_irq(priv->irqtx)) { - /* Process outgoing bytes */ + /* Process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; - /* Clear the pending TX interrupt if the TX FIFO is empty. - * Note that interrupts can be lost if the interrupt condition is - * still true when the interrupt is cleared. Keeping the TX - * interrupt pending too long is not a problem: Upper level logic - * will disable the TX interrupt when there is no longer anything - * to be sent. - */ + /* Clear the pending TX interrupt if the TX FIFO is empty. + * Note that interrupts can be lost if the interrupt condition is + * still true when the interrupt is cleared. Keeping the TX + * interrupt pending too long is not a problem: Upper level logic + * will disable the TX interrupt when there is no longer anything + * to be sent. + */ - if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) - { - up_clrpend_irq(priv->irqtx); - } + if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) + { + up_clrpend_irq(priv->irqtx); + } } } @@ -593,7 +593,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) dev = inode->i_private; DEBUGASSERT(dev, dev->priv); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; switch (cmd) { @@ -602,7 +602,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -621,7 +621,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -663,7 +663,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return status information */ @@ -687,7 +687,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; uint8_t im; @@ -729,7 +729,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return true is data is available in the receive data buffer */ @@ -746,7 +746,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, PIC32MX_UART_TXREG_OFFSET, (uint32_t)ch); } @@ -760,7 +760,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; uint8_t im; @@ -803,7 +803,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return TRUE if the Transmit buffer register is not full */ @@ -820,7 +820,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return TRUE if the Transmit shift register is empty */ diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c index cf8f7d0b38..bcaf0b7d39 100644 --- a/arch/mips/src/pic32mx/pic32mx-spi.c +++ b/arch/mips/src/pic32mx/pic32mx-spi.c @@ -611,7 +611,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) */ regval = spi_getreg(priv, PIC32MX_SPI_CON_OFFSET); - regval &= ~(SPI_CON_CKP|SPI_CON_CKE); + regval &= ~(SPI_CON_CKP | SPI_CON_CKE); switch (mode) { @@ -627,7 +627,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CON_CKP|SPI_CON_CKE); + regval |= (SPI_CON_CKP | SPI_CON_CKE); break; default: @@ -783,7 +783,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) { FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev; - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint32_t regval; uint8_t data; @@ -840,7 +840,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) { FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev; - FAR uint8_t *ptr = (FAR uint8_t*)buffer; + FAR uint8_t *ptr = (FAR uint8_t *)buffer; spivdbg("nwords: %d\n", nwords); while (nwords) diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c index 527f7463ff..e632869e1c 100644 --- a/arch/mips/src/pic32mx/pic32mx-timerisr.c +++ b/arch/mips/src/pic32mx/pic32mx-timerisr.c @@ -173,7 +173,7 @@ void up_timer_initialize(void) * the external SOSC (TCS=1) */ - putreg32((TIMER1_CON_TCKPS|TIMER1_CON_TCS), PIC32MX_TIMER1_CON); + putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MX_TIMER1_CON); putreg32(0, PIC32MX_TIMER1_CNT); putreg32(TIMER1_MATCH-1, PIC32MX_TIMER1_PR); putreg32(TIMER_CON_ON, PIC32MX_TIMER1_CONSET); diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c index cc05aef6e9..20ba256596 100644 --- a/arch/mips/src/pic32mx/pic32mx-usbdev.c +++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c @@ -107,11 +107,11 @@ # define USB_SOF_INTERRUPT 0 #endif -#define ERROR_INTERRUPTS (USB_EINT_PID|USB_EINT_CRC5|USB_EINT_EOF|\ - USB_EINT_CRC16|USB_EINT_DFN8|USB_EINT_BTO|\ +#define ERROR_INTERRUPTS (USB_EINT_PID | USB_EINT_CRC5 | USB_EINT_EOF | \ + USB_EINT_CRC16 | USB_EINT_DFN8 | USB_EINT_BTO | \ USB_EINT_BTS) -#define NORMAL_INTERRUPTS (USB_INT_URST|USB_INT_UERR|USB_SOF_INTERRUPT|\ - USB_INT_TRN|USB_INT_IDLE|USB_INT_STALL) +#define NORMAL_INTERRUPTS (USB_INT_URST | USB_INT_UERR | USB_SOF_INTERRUPT | \ + USB_INT_TRN | USB_INT_IDLE | USB_INT_STALL) /* Endpoints ****************************************************************/ /* Endpoint identifiers. The PIC32MX supports up to 16 mono-directional or 8 @@ -401,7 +401,7 @@ struct pic32mx_ep_s uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */ uint8_t txdata1:1; /* Data0/1 of next TX transfer */ uint8_t rxdata1:1; /* Data0/1 of next RX transfer */ - volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction*/ + volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */ volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */ }; @@ -1853,11 +1853,11 @@ static void pic32mx_ep0rdcomplete(struct pic32mx_usbdev_s *priv) physaddr = PHYS_ADDR(&priv->ctrl); bdt = &g_bdt[EP0_OUT_EVEN]; - bdt->addr = (uint8_t*)physaddr; + bdt->addr = (uint8_t *)physaddr; bdt->status = (USB_BDT_UOWN | bytecount); bdt = &g_bdt[EP0_OUT_ODD]; - bdt->addr = (uint8_t*)physaddr; + bdt->addr = (uint8_t *)physaddr; bdt->status = (USB_BDT_UOWN | bytecount); priv->ep0done = 1; @@ -2058,7 +2058,7 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv) else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT) { - /* Disable HNP support*/ + /* Disable HNP support */ #warning Missing Logic } @@ -2711,7 +2711,7 @@ static int pic32mx_interrupt(int irq, void *context) /* Make sure that the USE reset and IDLE detect interrupts are enabled */ regval = pic32mx_getreg(PIC32MX_USB_IE); - regval |= (USB_INT_URST|USB_INT_IDLE); + regval |= (USB_INT_URST | USB_INT_IDLE); pic32mx_putreg(regval, PIC32MX_USB_IE); /* Now were are in the powered state */ @@ -3301,7 +3301,7 @@ static int pic32mx_epdisable(struct usbdev_ep_s *ep) * 32-bit words per BDT. */ - ptr = (uint32_t*)&g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)]; + ptr = (uint32_t *)&g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)]; for (i = 0; i < USB_BDT_WORD_SIZE * USB_NBDTS_PER_EP; i++) { *ptr++ = 0; @@ -3345,7 +3345,7 @@ static struct usbdev_req_s *pic32mx_epallocreq(struct usbdev_ep_s *ep) static void pic32mx_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct pic32mx_req_s *privreq = (struct pic32mx_req_s*)req; + struct pic32mx_req_s *privreq = (struct pic32mx_req_s *)req; #ifdef CONFIG_DEBUG if (!ep || !req) @@ -3567,12 +3567,12 @@ static int pic32mx_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) /* Configure the other BDT to receive a SETUP command. */ - otherbdt->addr = (uint8_t*)physaddr; + otherbdt->addr = (uint8_t *)physaddr; otherbdt->status = (USB_BDT_UOWN | bytecount); /* Configure the current BDT to receive a SETUP command. */ - bdt->addr = (uint8_t*)physaddr; + bdt->addr = (uint8_t *)physaddr; bdt->status = (USB_BDT_UOWN | bytecount); bdtdbg("EP0 BDT IN [%p] {%08x, %08x}\n", @@ -3812,13 +3812,13 @@ static int pic32mx_getframe(struct usbdev_s *dev) do { - /* Loop until we can be sure that there was no wrap from the FRML - * to the FRMH register. - */ + /* Loop until we can be sure that there was no wrap from the FRML + * to the FRMH register. + */ - frmh = pic32mx_getreg(PIC32MX_USB_FRMH) & USB_FRMH_MASK; - frml = pic32mx_getreg(PIC32MX_USB_FRML) & USB_FRML_MASK; - tmp = pic32mx_getreg(PIC32MX_USB_FRMH) & USB_FRMH_MASK; + frmh = pic32mx_getreg(PIC32MX_USB_FRMH) & USB_FRMH_MASK; + frml = pic32mx_getreg(PIC32MX_USB_FRML) & USB_FRML_MASK; + tmp = pic32mx_getreg(PIC32MX_USB_FRMH) & USB_FRMH_MASK; } while (frmh != tmp); @@ -4128,7 +4128,7 @@ static void pic32mx_hwreset(struct pic32mx_usbdev_s *priv) /* Clear all of the buffer descriptor table (BDT) entries */ - memset((void*)g_bdt, 0, sizeof(g_bdt)); + memset((void *)g_bdt, 0, sizeof(g_bdt)); /* Power up the USB module */ diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c index 3039c534b4..f2766ff331 100644 --- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c +++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c @@ -105,7 +105,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) */ #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS - savestate = (uint32_t*)current_regs; + savestate = (uint32_t *)current_regs; #else DEBUGASSERT(current_regs == NULL); #endif @@ -113,7 +113,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) /* Loop while there are pending interrupts with priority greater than zero */ - for (;;) + for (; ; ) { /* Read the INTSTAT register. This register contains both the priority * and the interrupt vector number. @@ -146,7 +146,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) * switch occurred during interrupt processing. */ - regs = (uint32_t*)current_regs; + regs = (uint32_t *)current_regs; #if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) /* Check for a context switch. If a context switch occurred, then @@ -161,7 +161,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - up_restorefpu((uint32_t*)current_regs); + up_restorefpu((uint32_t *)current_regs); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index c6942d7176..4445a580f8 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -694,7 +694,7 @@ static inline void pic32mz_bufferinit(struct pic32mz_driver_s *priv) { /* Add the buffer to the end of the list of free buffers */ - sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); /* Get the address of the next buffer */ @@ -720,7 +720,7 @@ static uint8_t *pic32mz_allocbuffer(struct pic32mz_driver_s *priv) { /* Return the next free buffer from the head of the free buffer list */ - return (uint8_t*)sq_remfirst(&priv->pd_freebuffers); + return (uint8_t *)sq_remfirst(&priv->pd_freebuffers); } /**************************************************************************** @@ -741,7 +741,7 @@ static void pic32mz_freebuffer(struct pic32mz_driver_s *priv, uint8_t *buffer) { /* Add the buffer to the end of the free buffer list */ - sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); } /**************************************************************************** @@ -1395,7 +1395,7 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) * the producer index is not equal to the consumer index. */ - for (;;) + for (; ; ) { /* Check if any RX descriptor has the EOWN bit cleared meaning that the * this descriptor is now under software control and a message was @@ -1445,7 +1445,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) /* We don't have any logic here for reassembling packets from fragments. */ - else if ((rxdesc->status & (RXDESC_STATUS_EOP|RXDESC_STATUS_SOP)) != (RXDESC_STATUS_EOP|RXDESC_STATUS_SOP)) + else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) != + (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) { nlldbg("Fragment. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); EMAC_STAT(priv, rx_fragment); @@ -1457,7 +1458,7 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) /* Get the Rx buffer address from the Rx descriptor */ - priv->pd_dev.d_buf = (uint8_t*)VIRT_ADDR(rxdesc->address); + priv->pd_dev.d_buf = (uint8_t *)VIRT_ADDR(rxdesc->address); DEBUGASSERT(priv->pd_dev.d_buf != NULL); /* Replace the buffer in the RX descriptor with a new one */ @@ -2048,9 +2049,9 @@ static int pic32mz_ifup(struct net_driver_s *dev) pic32mz_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), PIC32MZ_EMAC1_SUPPCLR); #endif - /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, - * and then clear the reset bit. - */ + /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, + * and then clear the reset bit. + */ regval = pic32mz_getreg(PIC32MZ_EMAC1_MCFG); pic32mz_putreg(EMAC1_MCFG_MGMTRST, PIC32MZ_EMAC1_MCFGSET); @@ -2162,7 +2163,7 @@ static int pic32mz_ifup(struct net_driver_s *dev) /* Continue Ethernet Controller Initialization ****************************/ /* If planning to turn on the flow control, update the PTV value - *(ETHCON1:16-31). + * (ETHCON1:16-31). */ /* If using the auto-flow control, set the full and empty watermarks: RXFWM @@ -3229,7 +3230,7 @@ static inline int pic32mz_ethinitialize(int intf) priv->pd_dev.d_addmac = pic32mz_addmac; /* Add multicast MAC address */ priv->pd_dev.d_rmmac = pic32mz_rmmac; /* Remove multicast MAC address */ #endif - priv->pd_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + priv->pd_dev.d_private = (void *)priv; /* Used to recover private state from dev */ #if CONFIG_PIC32MZ_NINTERFACES > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" diff --git a/arch/mips/src/pic32mz/pic32mz-lowinit.c b/arch/mips/src/pic32mz/pic32mz-lowinit.c index 18f146216b..595d085b80 100644 --- a/arch/mips/src/pic32mz/pic32mz-lowinit.c +++ b/arch/mips/src/pic32mz/pic32mz-lowinit.c @@ -248,7 +248,7 @@ static inline void pic32mz_k0cache(void) { register uint32_t regval; - /* Enable cache on KSEG 0 in the CP0 CONFIG register*/ + /* Enable cache on KSEG 0 in the CP0 CONFIG register */ asm("\tmfc0 %0,$16,0\n" : "=r"(regval)); regval &= ~CP0_CONFIG_K23_MASK; diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c index 98f95f393f..ef52ecbda9 100644 --- a/arch/mips/src/pic32mz/pic32mz-serial.c +++ b/arch/mips/src/pic32mz/pic32mz-serial.c @@ -598,7 +598,7 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -622,7 +622,7 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Configure the UART as an RS-232 UART */ @@ -644,7 +644,7 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable interrupts */ @@ -672,7 +672,7 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; int ret; /* Attach the IRQs */ @@ -703,7 +703,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Disable interrupts */ @@ -734,7 +734,7 @@ static int up_interrupt(struct uart_dev_s *dev) bool handled; DEBUGASSERT(dev && dev->priv); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. @@ -771,23 +771,23 @@ static int up_interrupt(struct uart_dev_s *dev) if (up_pending_irq(priv->irqrx)) { - /* Process incoming bytes */ + /* Process incoming bytes */ - uart_recvchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; - /* Clear the pending RX interrupt if the receive buffer is empty. - * Note that interrupts can be lost if the interrupt condition is - * still true when the interrupt is cleared. Keeping the RX - * interrupt pending too long is not a problem because the - * upper half driver will disable RX interrupts if it no - * longer has space to buffer the serial data. - */ + /* Clear the pending RX interrupt if the receive buffer is empty. + * Note that interrupts can be lost if the interrupt condition is + * still true when the interrupt is cleared. Keeping the RX + * interrupt pending too long is not a problem because the + * upper half driver will disable RX interrupts if it no + * longer has space to buffer the serial data. + */ - if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_URXDA) == 0) - { - up_clrpend_irq(priv->irqrx); - } + if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_URXDA) == 0) + { + up_clrpend_irq(priv->irqrx); + } } /* Handle outgoing, transmit bytes The RT FIFO is configured to @@ -807,23 +807,23 @@ static int up_interrupt(struct uart_dev_s *dev) if (up_pending_irq(priv->irqtx)) { - /* Process outgoing bytes */ + /* Process outgoing bytes */ - uart_xmitchars(dev); - handled = true; + uart_xmitchars(dev); + handled = true; - /* Clear the pending TX interrupt if the TX FIFO is empty. - * Note that interrupts can be lost if the interrupt condition is - * still true when the interrupt is cleared. Keeping the TX - * interrupt pending too long is not a problem: Upper level logic - * will disable the TX interrupt when there is no longer anything - * to be sent. - */ + /* Clear the pending TX interrupt if the TX FIFO is empty. + * Note that interrupts can be lost if the interrupt condition is + * still true when the interrupt is cleared. Keeping the TX + * interrupt pending too long is not a problem: Upper level logic + * will disable the TX interrupt when there is no longer anything + * to be sent. + */ - if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) - { - up_clrpend_irq(priv->irqtx); - } + if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) + { + up_clrpend_irq(priv->irqtx); + } } } @@ -901,7 +901,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) dev = inode->i_private; DEBUGASSERT(dev, dev->priv); - priv = (struct up_dev_s*)dev->priv; + priv = (struct up_dev_s *)dev->priv; switch (cmd) { @@ -910,7 +910,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCGETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -929,7 +929,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TCSETS: { - struct termios *termiosp = (struct termios*)arg; + struct termios *termiosp = (struct termios *)arg; if (!termiosp) { @@ -971,7 +971,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, uint32_t *status) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return status information */ @@ -995,7 +995,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) static void up_rxint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; uint8_t im; @@ -1037,7 +1037,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return true is data is available in the receive data buffer */ @@ -1054,7 +1054,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; up_serialout(priv, PIC32MZ_UART_TXREG_OFFSET, (uint32_t)ch); } @@ -1068,7 +1068,7 @@ static void up_send(struct uart_dev_s *dev, int ch) static void up_txint(struct uart_dev_s *dev, bool enable) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; uint8_t im; @@ -1111,7 +1111,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return TRUE if the Transmit buffer register is not full */ @@ -1128,7 +1128,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; /* Return TRUE if the Transmit shift register is empty */ diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c index 26e70ea051..075a47c30d 100644 --- a/arch/mips/src/pic32mz/pic32mz-spi.c +++ b/arch/mips/src/pic32mz/pic32mz-spi.c @@ -977,7 +977,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) */ regval = spi_getreg(priv, PIC32MZ_SPI_CON_OFFSET); - regval &= ~(SPI_CON_CKP|SPI_CON_CKE); + regval &= ~(SPI_CON_CKP | SPI_CON_CKE); switch (mode) { @@ -993,7 +993,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - regval |= (SPI_CON_CKP|SPI_CON_CKE); + regval |= (SPI_CON_CKP | SPI_CON_CKE); break; default: diff --git a/arch/mips/src/pic32mz/pic32mz-timerisr.c b/arch/mips/src/pic32mz/pic32mz-timerisr.c index 675e69543e..cbbdf886ca 100644 --- a/arch/mips/src/pic32mz/pic32mz-timerisr.c +++ b/arch/mips/src/pic32mz/pic32mz-timerisr.c @@ -172,7 +172,7 @@ void up_timer_initialize(void) * the external SOSC (TCS=1) */ - putreg32((TIMER1_CON_TCKPS|TIMER1_CON_TCS), PIC32MZ_TIMER1_CON); + putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MZ_TIMER1_CON); putreg32(0, PIC32MZ_TIMER1_CNT); putreg32(TIMER1_MATCH-1, PIC32MZ_TIMER1_PR); putreg32(TIMER_CON_ON, PIC32MZ_TIMER1_CONSET); From c340185cb325bae943298682d1ab0685b54e46b7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Oct 2015 07:14:28 -0600 Subject: [PATCH 07/41] arch/sim: Fix spacing/alignment issues --- arch/sim/src/board_lcd.c | 16 ++++---- arch/sim/src/up_blockdevice.c | 2 +- arch/sim/src/up_blocktask.c | 4 +- arch/sim/src/up_createstack.c | 2 +- arch/sim/src/up_devconsole.c | 8 ++-- arch/sim/src/up_deviceimage.c | 63 +++++++++++++++-------------- arch/sim/src/up_exit.c | 4 +- arch/sim/src/up_netdev.c | 2 +- arch/sim/src/up_netdriver.c | 21 +++++----- arch/sim/src/up_releasepending.c | 4 +- arch/sim/src/up_reprioritizertr.c | 4 +- arch/sim/src/up_schedulesigaction.c | 2 +- arch/sim/src/up_simuart.c | 4 +- arch/sim/src/up_spiflash.c | 6 +-- arch/sim/src/up_tapdev.c | 6 +-- arch/sim/src/up_touchscreen.c | 8 ++-- arch/sim/src/up_unblocktask.c | 6 +-- arch/sim/src/up_usestack.c | 2 +- arch/sim/src/up_x11framebuffer.c | 31 +++++++------- 19 files changed, 101 insertions(+), 94 deletions(-) diff --git a/arch/sim/src/board_lcd.c b/arch/sim/src/board_lcd.c index ecac19aa26..94d0d6af87 100644 --- a/arch/sim/src/board_lcd.c +++ b/arch/sim/src/board_lcd.c @@ -196,20 +196,20 @@ static uint8_t g_runbuffer[FB_STRIDE]; static const struct fb_videoinfo_s g_videoinfo = { - .fmt = FB_FMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = CONFIG_SIM_FBWIDTH, /* Horizontal resolution in pixel columns */ - .yres = CONFIG_SIM_FBHEIGHT, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ + .fmt = FB_FMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = CONFIG_SIM_FBWIDTH, /* Horizontal resolution in pixel columns */ + .yres = CONFIG_SIM_FBHEIGHT, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ }; /* This is the standard, NuttX Plane information object */ static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = sim_putrun, /* Put a run into LCD memory */ - .getrun = sim_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = CONFIG_SIM_FBBPP, /* Bits-per-pixel */ + .putrun = sim_putrun, /* Put a run into LCD memory */ + .getrun = sim_getrun, /* Get a run from LCD memory */ + .buffer = (FAR uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = CONFIG_SIM_FBBPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ diff --git a/arch/sim/src/up_blockdevice.c b/arch/sim/src/up_blockdevice.c index dc473075fe..0cf71a7df4 100644 --- a/arch/sim/src/up_blockdevice.c +++ b/arch/sim/src/up_blockdevice.c @@ -84,6 +84,6 @@ void up_registerblockdevice(void) { - ramdisk_register(0, (uint8_t*)up_deviceimage(), NSECTORS, + ramdisk_register(0, (FAR uint8_t *)up_deviceimage(), NSECTORS, LOGICAL_SECTOR_SIZE, RDFLAG_WRENABLED | RDFLAG_FUNLINK); } diff --git a/arch/sim/src/up_blocktask.c b/arch/sim/src/up_blocktask.c index 3f30a45bbe..dbd5acc9ea 100644 --- a/arch/sim/src/up_blocktask.c +++ b/arch/sim/src/up_blocktask.c @@ -75,7 +75,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + FAR struct tcb_s *rtcb = (FAR struct tcb_s *)g_readytorun.head; bool switch_needed; /* Verify that the context switch can be performed */ @@ -126,7 +126,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("New Active Task TCB=%p\n", rtcb); /* The way that we handle signals in the simulation is kind of diff --git a/arch/sim/src/up_createstack.c b/arch/sim/src/up_createstack.c index b74c04c450..72e50921be 100644 --- a/arch/sim/src/up_createstack.c +++ b/arch/sim/src/up_createstack.c @@ -107,7 +107,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) /* Allocate the memory for the stack */ - stack_alloc_ptr = (uint32_t*)kumm_malloc(adj_stack_size); + stack_alloc_ptr = (FAR uint32_t *)kumm_malloc(adj_stack_size); /* Was the allocation successful? */ diff --git a/arch/sim/src/up_devconsole.c b/arch/sim/src/up_devconsole.c index 6c4e519d0c..b1baebf063 100644 --- a/arch/sim/src/up_devconsole.c +++ b/arch/sim/src/up_devconsole.c @@ -56,11 +56,13 @@ * Private Function Prototypes ****************************************************************************/ -static ssize_t devconsole_read(struct file *, char *, size_t); -static ssize_t devconsole_write(struct file *, const char *, size_t); +static ssize_t devconsole_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t devconsole_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); #ifndef CONFIG_DISABLE_POLL static int devconsole_poll(FAR struct file *filep, FAR struct pollfd *fds, - bool setup); + bool setup); #endif /**************************************************************************** diff --git a/arch/sim/src/up_deviceimage.c b/arch/sim/src/up_deviceimage.c index 715782f8e8..f50944bd2e 100644 --- a/arch/sim/src/up_deviceimage.c +++ b/arch/sim/src/up_deviceimage.c @@ -224,7 +224,7 @@ char *up_deviceimage(void) if (ret != Z_OK) { sdbg("inflateInit FAILED: ret=%d msg=\"%s\"\n", - ret, strm.msg ? strm.msg : "No message" ); + ret, strm.msg ? strm.msg : "No message"); return NULL; } @@ -232,12 +232,12 @@ char *up_deviceimage(void) * reallocate this a few times to get the size right. */ - pbuffer = (char*)kmm_malloc(bufsize); + pbuffer = (char *)kmm_malloc(bufsize); /* Set up the input buffer */ strm.avail_in = sizeof(g_vfatdata); - strm.next_in = (Bytef*)g_vfatdata; + strm.next_in = (Bytef *)g_vfatdata; /* Run inflate() on input until output buffer not full */ @@ -246,7 +246,7 @@ char *up_deviceimage(void) /* Set up to catch the next output chunk in the output buffer */ strm.avail_out = bufsize - offset; - strm.next_out = (Bytef*)&pbuffer[offset]; + strm.next_out = (Bytef *)&pbuffer[offset]; /* inflate */ @@ -261,7 +261,7 @@ char *up_deviceimage(void) case Z_MEM_ERROR: case Z_STREAM_ERROR: sdbg("inflate FAILED: ret=%d msg=\"%s\"\n", - ret, strm.msg ? strm.msg : "No message" ); + ret, strm.msg ? strm.msg : "No message"); (void)inflateEnd(&strm); kmm_free(pbuffer); return NULL; @@ -274,7 +274,7 @@ char *up_deviceimage(void) if (strm.avail_out == 0) { - int newbufsize = bufsize + 128*1024; + int newbufsize = bufsize + 128 * 1024; char *newbuffer = kmm_realloc(pbuffer, newbufsize); if (!newbuffer) { @@ -326,42 +326,43 @@ char *up_deviceimage(void) #ifdef VFAT_STANDALONE int main(int argc, char **argv, char **envp) { - char *deviceimage; - int cmf; - int fdict; - int flg; - int check; + char *deviceimage; + int cmf; + int fdict; + int flg; + int check; - cmf = g_vfatdata[0]; - printf("CMF=%02x: CM=%d CINFO=%d\n", cmf, cmf &0x0f, cmf >> 4); + cmf = g_vfatdata[0]; + printf("CMF=%02x: CM=%d CINFO=%d\n", cmf, cmf &0x0f, cmf >> 4); - flg = g_vfatdata[1]; - fdict = (flg >> 5) & 1; + flg = g_vfatdata[1]; + fdict = (flg >> 5) & 1; - printf("FLG=%02x: FCHECK=%d FDICT=%d FLEVEL=%d\n", flg, flg &0x1f, fdict, flg >> 6); + printf("FLG=%02x: FCHECK=%d FDICT=%d FLEVEL=%d\n", + flg, flg &0x1f, fdict, flg >> 6); - /* The FCHECK value must be such that CMF and FLG, when viewed as - * a 16-bit unsigned integer stored in MSB order (CMF*256 + FLG), - * is a multiple of 31. - */ + /* The FCHECK value must be such that CMF and FLG, when viewed as + * a 16-bit unsigned integer stored in MSB order (CMF*256 + FLG), + * is a multiple of 31. + */ - check = cmf*256 + flg; - if (check % 31 != 0) + check = cmf*256 + flg; + if (check % 31 != 0) { - printf("Fails check: %04x is not a multiple of 31\n", check); + printf("Fails check: %04x is not a multiple of 31\n", check); } - deviceimage = up_deviceimage(); - if (deviceimage) + deviceimage = up_deviceimage(); + if (deviceimage) { - printf("Inflate SUCCEEDED\n"); - kmm_free(deviceimage); - return 0; + printf("Inflate SUCCEEDED\n"); + kmm_free(deviceimage); + return 0; } - else + else { - printf("Inflate FAILED\n"); - return 1; + printf("Inflate FAILED\n"); + return 1; } } #endif diff --git a/arch/sim/src/up_exit.c b/arch/sim/src/up_exit.c index f82c51caf7..3f3b8301af 100644 --- a/arch/sim/src/up_exit.c +++ b/arch/sim/src/up_exit.c @@ -77,7 +77,7 @@ void _exit(int status) { - struct tcb_s* tcb; + FAR struct tcb_s *tcb; sdbg("TCB=%p exiting\n", tcb); @@ -89,7 +89,7 @@ void _exit(int status) * head of the list. */ - tcb = (struct tcb_s*)g_readytorun.head; + tcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("New Active Task TCB=%p\n", tcb); /* The way that we handle signals in the simulation is kind of diff --git a/arch/sim/src/up_netdev.c b/arch/sim/src/up_netdev.c index 237c42a69a..222f04d2b2 100644 --- a/arch/sim/src/up_netdev.c +++ b/arch/sim/src/up_netdev.c @@ -68,7 +68,7 @@ * Public Functions ****************************************************************************/ -unsigned long up_getwalltime( void ) +unsigned long up_getwalltime(void) { struct timeval tm; (void)gettimeofday(&tm, NULL); diff --git a/arch/sim/src/up_netdriver.c b/arch/sim/src/up_netdriver.c index 304fb81859..cafa5ae4a2 100644 --- a/arch/sim/src/up_netdriver.c +++ b/arch/sim/src/up_netdriver.c @@ -166,11 +166,12 @@ static int sim_txpoll(struct net_driver_s *dev) void netdriver_loop(void) { - struct eth_hdr_s *eth; + FAR struct eth_hdr_s *eth; /* netdev_read will return 0 on a timeout event and >0 on a data received event */ - g_sim_dev.d_len = netdev_read((unsigned char*)g_sim_dev.d_buf, CONFIG_NET_ETH_MTU); + g_sim_dev.d_len = netdev_read((FAR unsigned char *)g_sim_dev.d_buf, + CONFIG_NET_ETH_MTU); /* Disable preemption through to the following so that it behaves a little more * like an interrupt (otherwise, the following logic gets pre-empted an behaves @@ -210,10 +211,10 @@ void netdriver_loop(void) arp_ipin(&g_sim_dev); ipv4_input(&g_sim_dev); - /* If the above function invocation resulted in data that - * should be sent out on the network, the global variable - * d_len is set to a value > 0. - */ + /* If the above function invocation resulted in data that + * should be sent out on the network, the global variable + * d_len is set to a value > 0. + */ if (g_sim_dev.d_len > 0) { @@ -248,10 +249,10 @@ void netdriver_loop(void) ipv6_input(&g_sim_dev); - /* If the above function invocation resulted in data that - * should be sent out on the network, the global variable - * d_len is set to a value > 0. - */ + /* If the above function invocation resulted in data that + * should be sent out on the network, the global variable + * d_len is set to a value > 0. + */ if (g_sim_dev.d_len > 0) { diff --git a/arch/sim/src/up_releasepending.c b/arch/sim/src/up_releasepending.c index a92662f9ce..0efc0106f3 100644 --- a/arch/sim/src/up_releasepending.c +++ b/arch/sim/src/up_releasepending.c @@ -64,7 +64,7 @@ void up_release_pending(void) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + FAR struct tcb_s *rtcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("From TCB=%p\n", rtcb); @@ -92,7 +92,7 @@ void up_release_pending(void) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("New Active Task TCB=%p\n", rtcb); /* The way that we handle signals in the simulation is kind of diff --git a/arch/sim/src/up_reprioritizertr.c b/arch/sim/src/up_reprioritizertr.c index e07de0ea1a..49b9e6f1e1 100644 --- a/arch/sim/src/up_reprioritizertr.c +++ b/arch/sim/src/up_reprioritizertr.c @@ -92,7 +92,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) } else { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + FAR struct tcb_s *rtcb = (FAR struct tcb_s *)g_readytorun.head; bool switch_needed; sdbg("TCB=%p PRI=%d\n", tcb, priority); @@ -147,7 +147,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) * of the g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("New Active Task TCB=%p\n", rtcb); /* The way that we handle signals in the simulation is kind of diff --git a/arch/sim/src/up_schedulesigaction.c b/arch/sim/src/up_schedulesigaction.c index c93bb6d672..686a4de22b 100644 --- a/arch/sim/src/up_schedulesigaction.c +++ b/arch/sim/src/up_schedulesigaction.c @@ -100,7 +100,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { /* We don't have to anything complex for the simulated target */ - if (tcb == (struct tcb_s*)g_readytorun.head) + if (tcb == (FAR struct tcb_s *)g_readytorun.head) { sigdeliver(tcb); } diff --git a/arch/sim/src/up_simuart.c b/arch/sim/src/up_simuart.c index fd94fada9e..248848a206 100644 --- a/arch/sim/src/up_simuart.c +++ b/arch/sim/src/up_simuart.c @@ -132,7 +132,7 @@ static void *simuart_thread(void *arg) /* Now loop, collecting a buffering data from stdin forever */ - for (;;) + for (; ; ) { /* Read one character from stdin */ @@ -280,7 +280,7 @@ int simuart_getc(void) */ sched_lock(); - for (;;) + for (; ; ) { /* Wait for a byte to become available */ diff --git a/arch/sim/src/up_spiflash.c b/arch/sim/src/up_spiflash.c index 69d80b0e72..b1e8366018 100644 --- a/arch/sim/src/up_spiflash.c +++ b/arch/sim/src/up_spiflash.c @@ -479,9 +479,9 @@ static void spiflash_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffe /* 8-bit mode */ - const uint8_t *src = (const uint8_t*)txbuffer;; - uint8_t *dest = (uint8_t*)rxbuffer; - uint8_t word; + FAR const uint8_t *src = (FAR const uint8_t *)txbuffer; + FAR uint8_t *dest = (FAR uint8_t *)rxbuffer; + uint8_t word; while (nwords-- > 0) { diff --git a/arch/sim/src/up_tapdev.c b/arch/sim/src/up_tapdev.c index 11459e15e0..0fe0d890f1 100644 --- a/arch/sim/src/up_tapdev.c +++ b/arch/sim/src/up_tapdev.c @@ -189,18 +189,18 @@ void tapdev_init(void) gtapdevfd = open(DEVTAP, O_RDWR, 0644); if (gtapdevfd < 0) { - syslog(LOG_ERR, "TAPDEV: open failed: %d\n", -gtapdevfd ); + syslog(LOG_ERR, "TAPDEV: open failed: %d\n", -gtapdevfd); return; } /* Configure the tap device */ memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP|IFF_NO_PI; + ifr.ifr_flags = IFF_TAP | IFF_NO_PI; ret = ioctl(gtapdevfd, TUNSETIFF, (unsigned long) &ifr); if (ret < 0) { - syslog(LOG_ERR, "TAPDEV: ioctl failed: %d\n", -ret ); + syslog(LOG_ERR, "TAPDEV: ioctl failed: %d\n", -ret); return; } diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c index a7f6d68fb4..182f8fc161 100644 --- a/arch/sim/src/up_touchscreen.c +++ b/arch/sim/src/up_touchscreen.c @@ -243,7 +243,7 @@ static int up_sample(FAR struct up_dev_s *priv, * sampled data. */ - memcpy(sample, &priv->sample, sizeof(struct up_sample_s )); + memcpy(sample, &priv->sample, sizeof(struct up_sample_s)); /* Now manage state transitions */ @@ -643,7 +643,7 @@ errout: int board_tsc_setup(int minor) { - FAR struct up_dev_s *priv = ( FAR struct up_dev_s *)&g_simtouchscreen; + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)&g_simtouchscreen; char devname[DEV_NAMELEN]; int ret; @@ -703,7 +703,7 @@ errout_with_priv: void board_tsc_teardown(void) { - FAR struct up_dev_s *priv = ( FAR struct up_dev_s *)&g_simtouchscreen; + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)&g_simtouchscreen; char devname[DEV_NAMELEN]; int ret; @@ -728,7 +728,7 @@ void board_tsc_teardown(void) g_eventloop = 0; - /* Un-register the device*/ + /* Un-register the device */ (void)snprintf(devname, DEV_NAMELEN, DEV_FORMAT, priv->minor); ivdbg("Un-registering %s\n", devname); diff --git a/arch/sim/src/up_unblocktask.c b/arch/sim/src/up_unblocktask.c index cf2dfa1400..09deede225 100644 --- a/arch/sim/src/up_unblocktask.c +++ b/arch/sim/src/up_unblocktask.c @@ -68,9 +68,9 @@ * ****************************************************************************/ -void up_unblock_task(struct tcb_s *tcb) +void up_unblock_task(FAR struct tcb_s *tcb) { - struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + FAR struct tcb_s *rtcb = (FAR struct tcb_s *)g_readytorun.head; /* Verify that the context switch can be performed */ @@ -110,7 +110,7 @@ void up_unblock_task(struct tcb_s *tcb) * g_readytorun task list. */ - rtcb = (struct tcb_s*)g_readytorun.head; + rtcb = (FAR struct tcb_s *)g_readytorun.head; sdbg("New Active Task TCB=%p\n", rtcb); /* The way that we handle signals in the simulation is kind of diff --git a/arch/sim/src/up_usestack.c b/arch/sim/src/up_usestack.c index 3121b59bd0..c9e660dc5b 100644 --- a/arch/sim/src/up_usestack.c +++ b/arch/sim/src/up_usestack.c @@ -96,7 +96,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) /* This is the address of the last word in the allocation */ - size_t *adj_stack_ptr = &((size_t*)stack)[adj_stack_words - 1]; + FAR size_t *adj_stack_ptr = &((FAR size_t *)stack)[adj_stack_words - 1]; /* Save the values in the TCB */ diff --git a/arch/sim/src/up_x11framebuffer.c b/arch/sim/src/up_x11framebuffer.c index bf0e3ce150..ceb7e2e8d4 100644 --- a/arch/sim/src/up_x11framebuffer.c +++ b/arch/sim/src/up_x11framebuffer.c @@ -120,9 +120,9 @@ static inline int up_x11createframe(void) XStringListToTextProperty(&winName, 1, &winprop); XStringListToTextProperty(&iconName, 1, &iconprop); - hints.flags = PSize | PMinSize | PMaxSize; - hints.width = hints.min_width = hints.max_width = g_fbpixelwidth; - hints.height= hints.min_height = hints.max_height = g_fbpixelheight; + hints.flags = PSize | PMinSize | PMaxSize; + hints.width = hints.min_width = hints.max_width = g_fbpixelwidth; + hints.height = hints.min_height = hints.max_height = g_fbpixelheight; XSetWMProperties(g_display, g_window, &winprop, &iconprop, argv, 1, &hints, NULL, NULL); @@ -133,10 +133,11 @@ static inline int up_x11createframe(void) #if defined(CONFIG_SIM_AJOYSTICK) XSelectInput(g_display, g_window, - ButtonPressMask|ButtonReleaseMask|PointerMotionMask); + ButtonPressMask | ButtonReleaseMask | PointerMotionMask); #else XSelectInput(g_display, g_window, - ButtonPressMask|ButtonReleaseMask|PointerMotionMask|KeyPressMask); + ButtonPressMask | ButtonReleaseMask | PointerMotionMask | + KeyPressMask); #endif /* Release queued events on the display */ @@ -147,7 +148,7 @@ static inline int up_x11createframe(void) /* Grab mouse button 1, enabling mouse-related events */ (void)XGrabButton(g_display, Button1, AnyModifier, g_window, 1, - ButtonPressMask|ButtonReleaseMask|ButtonMotionMask, + ButtonPressMask | ButtonReleaseMask | ButtonMotionMask, GrabModeAsync, GrabModeAsync, None, None); #endif @@ -188,7 +189,7 @@ static void up_x11traperrors(void) #ifndef CONFIG_SIM_X11NOSHM static int up_x11untraperrors(void) { - XSync(g_display,0); + XSync(g_display, 0); XSetErrorHandler(NULL); return g_xerror; } @@ -291,7 +292,7 @@ static inline int up_x11mapsharedmem(int depth, unsigned int fblen) } if (!g_image) { - fprintf(stderr,"Unable to create g_image."); + fprintf(stderr, "Unable to create g_image."); return -1; } g_shmcheckpoint++; @@ -337,10 +338,10 @@ shmerror: #endif b_useshm = 0; - g_framebuffer = (unsigned char*)malloc(fblen); + g_framebuffer = (unsigned char *)malloc(fblen); - g_image = XCreateImage(g_display, DefaultVisual(g_display,g_screen), depth, - ZPixmap, 0, (char*)g_framebuffer, g_fbpixelwidth, g_fbpixelheight, + g_image = XCreateImage(g_display, DefaultVisual(g_display, g_screen), depth, + ZPixmap, 0, (char *)g_framebuffer, g_fbpixelwidth, g_fbpixelheight, 8, 0); if (g_image == NULL) @@ -416,7 +417,7 @@ int up_x11initialize(unsigned short width, unsigned short height, g_x11initialized = 1; } - *fbmem = (void*)g_framebuffer; + *fbmem = (void *)g_framebuffer; return 0; } @@ -440,8 +441,9 @@ int up_x11cmap(unsigned short first, unsigned short len, { XColor color; - /* Convert to RGB. In the NuttX cmap, each component - * ranges from 0-255; for X11 the range is 0-65536 */ + /* Convert to RGB. In the NuttX cmap, each component + * ranges from 0-255; for X11 the range is 0-65536 + */ color.red = (short)(*red++) << 8; color.green = (short)(*green++) << 8; @@ -478,5 +480,6 @@ void up_x11update(void) XPutImage(g_display, g_window, g_gc, g_image, 0, 0, 0, 0, g_fbpixelwidth, g_fbpixelheight); } + XSync(g_display, 0); } From 78669f20f2d49be231efbbb835341f37058c3854 Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Sun, 18 Oct 2015 08:14:10 +0800 Subject: [PATCH 08/41] SAMV7 MCAN: ix switched assertion check for TSEG1 and TSEG2 in CANIOC_SET_BITTIMING --- arch/arm/src/samv7/sam_mcan.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 74f59877db..1fcefd32c7 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -2435,8 +2435,8 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) DEBUGASSERT(bt != NULL); DEBUGASSERT(bt->bt_baud < SAMV7_MCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); - DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); - DEBUGASSERT(bt->bt_tseg2 > 1 && bt->bt_tseg2 <= 64); + DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); + DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); /* Extract bit timing data */ @@ -2642,11 +2642,11 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) DEBUGASSERT(config->ntxfifoq > 0); /* Reserve a buffer for the transmission, waiting if necessary. When - * mcan_buffer_reserve() returns, we are guaranteed the the TX FIFOQ is + * mcan_buffer_reserve() returns, we are guaranteed that the TX FIFOQ is * not full and cannot become full at least until we add our packet to * the FIFO. * - * We can't get exclusive access to MAN resource here because that + * We can't get exclusive access to MCAN resources here because that * lock the MCAN while we wait for a free buffer. Instead, the * scheduler is locked here momentarily. See discussion in * mcan_buffer_reserve() for an explanation. @@ -2747,8 +2747,8 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) * course, the transfer is not complete, but this early notification * allows the upper half logic to free resources sooner. * - * REVISTI: Should we disable interrupts? can_txdone() was designed to - * be called from and interrupt handler and, hence, may be unsafe when + * REVISIT: Should we disable interrupts? can_txdone() was designed to + * be called from an interrupt handler and, hence, may be unsafe when * called from the tasking level. */ From 4ac10f53d72eae76fdb4f447620bb196a1b3618a Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Tue, 20 Oct 2015 05:58:34 +0800 Subject: [PATCH 09/41] Reconfigure System I/O when using USART1 --- arch/arm/src/samv7/sam_lowputc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 1897cd17f8..d09d8fcd8a 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -54,6 +54,7 @@ #include "chip/sam_uart.h" #include "chip/sam_pinmap.h" +#include "chip/sam_matrix.h" /**************************************************************************** * Pre-processor Definitions @@ -353,6 +354,13 @@ void sam_lowsetup(void) #ifdef CONFIG_USART1_IFLOWCONTROL (void)sam_configgpio(GPIO_USART1_RTS); #endif + /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 + * instead of TDI + */ + + uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO); + sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4; + putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO); #endif #ifdef CONFIG_SAMV7_USART2 From 54b333dcd3151f18b7c3c7dd5f0b52a51ecfd819 Mon Sep 17 00:00:00 2001 From: Marten Svanfeldt Date: Wed, 21 Oct 2015 10:22:41 +0800 Subject: [PATCH 10/41] Add EXTI definitions for STM32F373 Signed-off-by: Marten Svanfeldt --- arch/arm/src/stm32/chip/stm32_exti.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/chip/stm32_exti.h b/arch/arm/src/stm32/chip/stm32_exti.h index 03b2f141da..a3092ca0e4 100644 --- a/arch/arm/src/stm32/chip/stm32_exti.h +++ b/arch/arm/src/stm32/chip/stm32_exti.h @@ -146,7 +146,7 @@ # define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */ # define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */ -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ # define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ # define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ From 4d879a33ee596e1646141c095936b0c519fa063a Mon Sep 17 00:00:00 2001 From: Marten Svanfeldt Date: Wed, 21 Oct 2015 10:30:57 +0800 Subject: [PATCH 11/41] Add support for STM32F429N (TFBGA) chip Signed-off-by: Marten Svanfeldt --- arch/arm/include/stm32/chip.h | 38 +++++++++++++++++++ .../src/stm32/chip/stm32f40xxx_memorymap.h | 1 + arch/arm/src/stm32/chip/stm32f40xxx_rcc.h | 2 + arch/arm/src/stm32/stm32_dumpgpio.c | 6 ++- arch/arm/src/stm32/stm32_gpio.c | 6 +++ arch/arm/src/stm32/stm32f40xxx_rcc.c | 6 +++ 6 files changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index d7439f41ee..ed2aa1f227 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -2307,6 +2307,44 @@ # define STM32_NRNG 0 /* Random number generator (RNG) */ # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ +#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ +# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 168 /* GPIOA-K */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h index 12fadff5f1..8b493e916c 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h @@ -187,6 +187,7 @@ #define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIO Port G */ #define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */ #define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */ +#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIO Port J */ #define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022Bff: GPIO Port K */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ #define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h index aa3c74d0b7..6e24907f39 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h @@ -317,6 +317,8 @@ #define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */ #define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */ #define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */ +#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */ +#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */ #define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ #define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */ #define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */ diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index 89749eab4d..559e24bef2 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -58,8 +58,12 @@ #ifdef CONFIG_DEBUG static const char g_portchar[STM32_NGPIO_PORTS] = { -#if STM32_NGPIO_PORTS > 9 +#if STM32_NGPIO_PORTS > 11 # error "Additional support required for this number of GPIOs" +#elif STM32_NGPIO_PORTS > 10 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' +#elif STM32_NGPIO_PORTS > 9 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' #elif STM32_NGPIO_PORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' #elif STM32_NGPIO_PORTS > 7 diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index f383b827ef..ef517073fb 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -117,6 +117,12 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] = #if STM32_NGPIO_PORTS > 8 STM32_GPIOI_BASE, #endif +#if STM32_NGPIO_PORTS > 9 + STM32_GPIOJ_BASE, +#endif +#if STM32_NGPIO_PORTS > 10 + STM32_GPIOK_BASE, +#endif #endif /* CONFIG_STM32_STM32L15XX */ }; diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index f0e16f4079..786c7f7cd7 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -159,6 +159,12 @@ static inline void rcc_enableahb1(void) #endif #if STM32_NGPIO > 128 |RCC_AHB1ENR_GPIOIEN +#endif +#if STM32_NGPIO > 144 + |RCC_AHB1ENR_GPIOJEN +#endif +#if STM32_NGPIO > 160 + |RCC_AHB1ENR_GPIOKEN #endif ); #endif From d1c7e5b5fbf929248cbc27e9fc9a05568ed96267 Mon Sep 17 00:00:00 2001 From: Marten Svanfeldt Date: Wed, 21 Oct 2015 10:33:39 +0800 Subject: [PATCH 12/41] Fix setup of PLLSAI in STM32F4xx. To correctly setup the PLLSAI register it is required to first mask out the old PLL divisor and multiplier factors before setting new ones Signed-off-by: Marten Svanfeldt --- arch/arm/src/stm32/stm32f40xxx_rcc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index f0e16f4079..41cacf5158 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -751,12 +751,16 @@ static void stm32_stdclockconfig(void) /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIR | STM32_RCC_PLLSAICFGR_PLLSAIQ); putreg32(regval, STM32_RCC_PLLSAICFGR); regval = getreg32(STM32_RCC_DCKCFGR); + regval &= ~RCC_DCKCFGR_PLLSAIDIVR_MASK; regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; putreg32(regval, STM32_RCC_DCKCFGR); From fdb484f24e7d1ed5661489f0986d008a056ac87f Mon Sep 17 00:00:00 2001 From: Marten Svanfeldt Date: Wed, 21 Oct 2015 10:56:36 +0800 Subject: [PATCH 13/41] Add missing pin definitions on STM32F429, specifically pins available on STM32F429N chip Signed-off-by: Marten Svanfeldt --- arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h | 34 +++++++++++++++++--- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h index b51a5b135f..d0fd0be6a7 100644 --- a/arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f42xxx_pinmap.h @@ -114,6 +114,7 @@ #define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) #define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) #define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9) +#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10) #define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) #define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) #define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) @@ -283,6 +284,22 @@ #define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8) #define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9) #define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10) +#define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8) +#define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9) +#define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10) +#define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11) +#define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12) +#define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13) +#define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14) +#define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15) +#define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6) +#define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7) +#define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9) +#define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10) #define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6) #define GPIO_FSMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7) #define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10) @@ -302,13 +319,20 @@ #define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7) #define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6) #define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5) +#define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4) +#define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5) #ifdef CONFIG_STM32_STM32F429 -# define GPIO_FSMC_SDCKE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2) -# define GPIO_FSMC_SDNE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3) -# define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5) -# define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6) -# define GPIO_FSMC_SDNWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0) +# define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2) +# define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3) +# define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3) +# define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2) +# define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5) +# define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7) +# define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6) +# define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0) +# define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5) # define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11) # define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8) # define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15) From 3299a31b27a121d244d5aca9ed126b3452539801 Mon Sep 17 00:00:00 2001 From: Marten Svanfeldt Date: Wed, 21 Oct 2015 11:05:38 +0800 Subject: [PATCH 14/41] Enhance STM32 QEncoder driver with configurable input filters Current driver applies a fixed filter of f_sample=f_dts/4, N=6. This can potentially be insufficient in noisy environments, or too slow for really fast encoder sources, so let the user set it from the Kconfig file Signed-off-by: Marten Svanfeldt --- arch/arm/src/stm32/Kconfig | 68 +++++++++++++++++++++++++++++ arch/arm/src/stm32/stm32_qencoder.c | 63 +++++++++++++++++++++++++- 2 files changed, 129 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 0c95f920d7..58ac54a7ed 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -4307,3 +4307,71 @@ endmenu endmenu endif # STM32_DMA2D +menu "QEncoder Driver" + depends on QENCODER + depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + default y + +choice + depends on STM32_QENCODER_FILTER + prompt "Input channel sampling frequency" + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + depends on STM32_QENCODER_FILTER + prompt "Input channel event count" + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + depends on STM32_QENCODER_SAMPLE_FDTS + bool "1" + +config STM32_QENCODER_SAMPLE_EVENT_2 + depends on STM32_QENCODER_SAMPLE_CKINT + bool "2" + +config STM32_QENCODER_SAMPLE_EVENT_4 + depends on STM32_QENCODER_SAMPLE_CKINT + bool "4" + +config STM32_QENCODER_SAMPLE_EVENT_5 + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + bool "5" + +config STM32_QENCODER_SAMPLE_EVENT_6 + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + bool "6" + +config STM32_QENCODER_SAMPLE_EVENT_8 + depends on !STM32_QENCODER_SAMPLE_FDTS + bool "8" + +endchoice + +endmenu diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index ea1b8e0854..775955c3c0 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -145,6 +145,65 @@ # define HAVE_MIXEDWIDTH_TIMERS 1 #endif +/* Input filter *********************************************************************/ +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# endif +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# endif +# endif + +# ifndef STM32_QENCODER_ICF +# warning "Invalid encoder filter combination, filter disabled" +# endif +#endif + +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#endif + /* Debug ****************************************************************************/ /* Non-standard debug that may be enabled just for testing the quadrature encoder */ @@ -809,7 +868,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK|GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -844,7 +903,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK|GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ From 79fad2843a07fdb7edf3cd750b1f13fcf62a19bf Mon Sep 17 00:00:00 2001 From: v01d Date: Fri, 30 Oct 2015 20:15:18 -0300 Subject: [PATCH 15/41] lpc4337: WIP --- arch/arm/include/lpc43xx/chip.h | 78 ++++++++++++++++++++++----------- arch/arm/src/lpc43xx/Kconfig | 8 ++++ arch/arm/src/lpc43xx/chip.h | 4 ++ 3 files changed, 64 insertions(+), 26 deletions(-) diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h index 7272f06790..e8ce651f66 100644 --- a/arch/arm/include/lpc43xx/chip.h +++ b/arch/arm/include/lpc43xx/chip.h @@ -78,33 +78,33 @@ /* Get customizations for each supported chip. * * SRAM Resources - * --------------------- -------- ------- ------- ------- ------- ------- - * Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb - * BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb - * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 - * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb - * --------------------- -------- ------- ------- ------- ------- ------- + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb + * BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb + * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 + * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- * - * --------------------- -------- ------- ------- ------- ------- ------- - * FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 - * --------------------- -------- ------- ------- ------- ------- ------- - * BANK A (0x1a00 0000) 256Kb 512Kb - * BANK B (0x1b00 8000) 256Kb 512Kb - * --------------------- -------- ------- ------- ------- ------- ------- - * TOTAL None None None None 512Kb 1024Kb - * --------------------- -------- ------- ------- ------- ------- ------- + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337 + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * BANK A (0x1a00 0000) 256Kb 512Kb 512Kb + * BANK B (0x1b00 8000) 256Kb 512Kb 512Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- + * TOTAL None None None None 512Kb 1024Kb 1024Kb + * --------------------- -------- ------- ------- ------- ------- ------- ------- * * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM * banks but are treated as two banks of 48 an 16Kb by the NuttX memory @@ -321,6 +321,32 @@ # define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */ # define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */ # undef LPC43_NADC12 /* No 12-bit ADC controllers */ +#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144) +# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */ +# define LPC43_FLASH_BANKB_SIZE (512*1025) +# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ +# define LPC43_LOCSRAM_BANK1_SIZE (40*1024) +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK1_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) +# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ +# define LPC43_NLCD (0) /* Has LCD controller */ +# define LPC43_ETHERNET (1) /* One Ethernet controller */ +# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */ +# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */ +# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */ +# define LPC43_MCPWM (1) /* One PWM interface */ +# define LPC43_QEI (0) /* One Quadrature Encoder interface */ +# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */ +# define LPC43_NSSP (2) /* Two SSP controllers */ +# define LPC43_NTIMERS (4) /* Four Timers */ +# define LPC43_NI2C (2) /* Two I2C controllers */ +# define LPC43_NI2S (2) /* Two I2S controllers */ +# define LPC43_NCAN (2) /* Two CAN controllers */ +# define LPC43_NDAC (1) /* One 10-bit DAC */ +# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */ +# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */ +# undef LPC43_NADC12 /* No 12-bit ADC controllers */ #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208) # define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */ # define LPC43_FLASH_BANKB_SIZE (0) diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 8df9946f07..e3655a47b2 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -34,6 +34,9 @@ config ARCH_CHIP_LPC4330FET180 config ARCH_CHIP_LPC4330FET256 bool "LPC4330FET256" +config ARCH_CHIP_LPC4337JBD144 + bool "LPC4337JBD144" + config ARCH_CHIP_LPC4350FBD208 bool "LPC4350FBD208" @@ -81,6 +84,11 @@ config ARCH_FAMILY_LPC4330 default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 select ARCH_HAVE_TICKLESS +config ARCH_FAMILY_LPC4337 + bool + default y if ARCH_CHIP_LPC4337JBD144 + select ARCH_HAVE_TICKLESS + config ARCH_FAMILY_LPC4350 bool default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256 diff --git a/arch/arm/src/lpc43xx/chip.h b/arch/arm/src/lpc43xx/chip.h index 0551c55b68..08ef7217a5 100644 --- a/arch/arm/src/lpc43xx/chip.h +++ b/arch/arm/src/lpc43xx/chip.h @@ -97,6 +97,10 @@ # define ARMV7M_PERIPHERAL_INTERRUPTS 53 # include "chip/lpc4310203050_memorymap.h" # include "chip/lpc4310203050_pinconfig.h" +#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144) +# define ARMV7M_PERIPHERAL_INTERRUPTS 53 +# include "chip/lpc435357_memorymap.h" +# include "chip/lpc4357fet256_pinconfig.h" #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208) # define ARMV7M_PERIPHERAL_INTERRUPTS 53 # include "chip/lpc4310203050_memorymap.h" From 668c56b1a6a5e99090c4ffe636d337563a8cf7c2 Mon Sep 17 00:00:00 2001 From: pnb Date: Sat, 31 Oct 2015 15:33:32 +0100 Subject: [PATCH 16/41] avoid warning unsused function when GPIO_TIMxCHxOUT declared in board and CONFIG_STM32_TIMx not enable but an other CONFIG_STM32_TIMx is enabled --- arch/arm/src/stm32/stm32_tim.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 1f9d537571..2aeccd86a3 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -145,6 +145,49 @@ # undef CONFIG_STM32_TIM14 #endif +#if defined(CONFIG_STM32_TIM1) +# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ + defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) +# define HAVE_TIM1_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM2) +# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ + defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) +# define HAVE_TIM2_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM3) +# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ + defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) +# define HAVE_TIM3_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM4) +# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ + defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) +# define HAVE_TIM4_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM5) +# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ + defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) +# define HAVE_TIM5_PWM_OUTPUT 1 +#endif +#endif + +#if defined(CONFIG_STM32_TIM8) +# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ + defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) +# define HAVE_TIM8_PWM_OUTPUT 1 +#endif +#endif + + /* This module then only compiles if there are enabled timers that are not intended for * some other purpose. */ @@ -245,6 +288,9 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) stm32_tim_disable(dev); } +#if defined(HAVE_TIM1_PWM_OUTPUT)||defined(HAVE_TIM2_PWM_OUTPUT)||\ + defined(HAVE_TIM3_PWM_OUTPUT)||defined(HAVE_TIM4_PWM_OUTPUT)||\ + defined(HAVE_TIM5_PWM_OUTPUT)||defined(HAVE_TIM8_PWM_OUTPUT) static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ @@ -258,6 +304,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) stm32_unconfiggpio(cfg); } } +#endif /************************************************************************************ * Basic Functions From 0090cfe6d48993ed01a3a198f1721082177f7414 Mon Sep 17 00:00:00 2001 From: pnb Date: Sat, 31 Oct 2015 15:59:20 +0100 Subject: [PATCH 17/41] Change name of HAVE_TIMx_PWM_OUTPUT into HAVE_TIMx_GPIOCONFIG --- arch/arm/src/stm32/stm32_tim.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 2aeccd86a3..c7d3b8350c 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -148,42 +148,42 @@ #if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_PWM_OUTPUT 1 +# define HAVE_TIM1_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_PWM_OUTPUT 1 +# define HAVE_TIM2_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_PWM_OUTPUT 1 +# define HAVE_TIM3_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_PWM_OUTPUT 1 +# define HAVE_TIM4_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_PWM_OUTPUT 1 +# define HAVE_TIM5_GPIOCONFIG 1 #endif #endif #if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_PWM_OUTPUT 1 +# define HAVE_TIM8_GPIOCONFIG 1 #endif #endif @@ -288,9 +288,9 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) stm32_tim_disable(dev); } -#if defined(HAVE_TIM1_PWM_OUTPUT)||defined(HAVE_TIM2_PWM_OUTPUT)||\ - defined(HAVE_TIM3_PWM_OUTPUT)||defined(HAVE_TIM4_PWM_OUTPUT)||\ - defined(HAVE_TIM5_PWM_OUTPUT)||defined(HAVE_TIM8_PWM_OUTPUT) +#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ + defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ + defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG) static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ From d1b4d55343907a8b0a41b8892f02301d51d033e1 Mon Sep 17 00:00:00 2001 From: pnb Date: Sun, 1 Nov 2015 14:40:43 +0100 Subject: [PATCH 18/41] pwm duty can by zero --- arch/arm/src/stm32/stm32_pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index a3a1645688..a5cafce797 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -582,7 +582,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n", priv->timid, priv->channel, info->frequency, info->duty); #endif - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && + DEBUGASSERT(info->frequency > 0 && info->duty >= 0 && info->duty < uitoub16(100)); /* Disable all interrupts and DMA requests, clear all pending status */ From 9db4b4ca7e0447b6d09775588bc33e51c8ac1234 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:01:59 -0600 Subject: [PATCH 19/41] Rename board_led_initialize to board_autoled_initiaize --- arch/arm/src/arm/up_nommuhead.S | 2 +- arch/arm/src/dm320/dm320_boot.c | 3 +- arch/arm/src/imx/imx_boot.c | 3 +- arch/arm/src/lpc214x/lpc214x_head.S | 2 +- arch/arm/src/lpc2378/lpc23xx_head.S | 2 +- arch/arm/src/str71x/str71x_head.S | 229 +++++++++++----------- arch/sh/src/m16c/m16c_head.S | 72 +++---- arch/sh/src/sh1/sh1_head.S | 288 ++++++++++++++-------------- arch/z16/src/z16f/z16f_head.S | 4 +- arch/z80/src/z8/z8_head.S | 2 +- 10 files changed, 305 insertions(+), 302 deletions(-) diff --git a/arch/arm/src/arm/up_nommuhead.S b/arch/arm/src/arm/up_nommuhead.S index 69855c0b09..04c5205efe 100644 --- a/arch/arm/src/arm/up_nommuhead.S +++ b/arch/arm/src/arm/up_nommuhead.S @@ -125,7 +125,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif #ifdef CONFIG_STACK_COLORATION diff --git a/arch/arm/src/dm320/dm320_boot.c b/arch/arm/src/dm320/dm320_boot.c index 089d7b45fb..13f64b3ff7 100644 --- a/arch/arm/src/dm320/dm320_boot.c +++ b/arch/arm/src/dm320/dm320_boot.c @@ -225,8 +225,9 @@ void up_boot(void) /* Set up the board-specific LEDs */ #ifdef CONFIG_ARCH_LEDS - board_led_initialize(); + board_autoled_initialize(); #endif + /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT diff --git a/arch/arm/src/imx/imx_boot.c b/arch/arm/src/imx/imx_boot.c index 44d8bf7b05..71bf743e3f 100644 --- a/arch/arm/src/imx/imx_boot.c +++ b/arch/arm/src/imx/imx_boot.c @@ -216,8 +216,9 @@ void up_boot(void) /* Set up the board-specific LEDs */ #ifdef CONFIG_ARCH_LEDS - board_led_initialize(); + board_autoled_initialize(); #endif + /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT diff --git a/arch/arm/src/lpc214x/lpc214x_head.S b/arch/arm/src/lpc214x/lpc214x_head.S index 0679bfa2a9..8db27f29eb 100644 --- a/arch/arm/src/lpc214x/lpc214x_head.S +++ b/arch/arm/src/lpc214x/lpc214x_head.S @@ -592,7 +592,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ diff --git a/arch/arm/src/lpc2378/lpc23xx_head.S b/arch/arm/src/lpc2378/lpc23xx_head.S index d3aa33503b..637402fa88 100755 --- a/arch/arm/src/lpc2378/lpc23xx_head.S +++ b/arch/arm/src/lpc2378/lpc23xx_head.S @@ -193,7 +193,7 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ diff --git a/arch/arm/src/str71x/str71x_head.S b/arch/arm/src/str71x/str71x_head.S index b7bd53a675..6a299e8911 100644 --- a/arch/arm/src/str71x/str71x_head.S +++ b/arch/arm/src/str71x/str71x_head.S @@ -37,11 +37,11 @@ * Included Files *****************************************************************************/ -#include /* NuttX configuration settings */ +#include /* NuttX configuration settings */ #include /* Board-specific settings */ -#include "arm.h" /* ARM-specific settings */ -#include "chip.h" /* Chip-specific settings */ +#include "arm.h" /* ARM-specific settings */ +#include "chip.h" /* Chip-specific settings */ #include "up_internal.h" #include "up_arch.h" @@ -59,18 +59,18 @@ * External references *****************************************************************************/ - .globl str71x_prccuinit /* Clock initialization */ - .globl up_lowsetup /* Early initialization of UART */ + .globl str71x_prccuinit /* Clock initialization */ + .globl up_lowsetup /* Early initialization of UART */ #ifdef USE_EARLYSERIALINIT - .globl up_earlyserialinit /* Early initialization of serial driver */ + .globl up_earlyserialinit /* Early initialization of serial driver */ #endif #ifdef CONFIG_ARCH_LEDS - .globl board_led_initialize /* Boot LED setup */ + .globl board_autoled_initialize /* Boot LED setup */ #endif #ifdef CONFIG_DEBUG - .globl up_lowputc /* Low-level debug output */ + .globl up_lowputc /* Low-level debug output */ #endif - .globl os_start /* NuttX entry point */ + .globl os_start /* NuttX entry point */ /***************************************************************************** * Macros @@ -87,8 +87,8 @@ .macro showprogress, code #ifdef CONFIG_DEBUG - mov r0, #\code - bl up_lowputc + mov r0, #\code + bl up_lowputc #endif .endm @@ -107,32 +107,32 @@ /* In order to use the external memory, certain GPIO pins must be * configured in the alternate function: * - * GPIO ALT Description + * GPIO ALT Description * P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4 * P2.4-7 A.20-23 External memory extended address bus (needed for * address space > 1Mb) */ #ifdef CONFIG_STR71X_BIGEXTMEM -# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */ +# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */ #else -# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */ +# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */ #endif - ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode - ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC0_OFFSET] - ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC1_OFFSET] - ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET] - orr \value, \value, #EXTMEM_GPIO_BITSET - str \value, [\base, #STR71X_GPIO_PC2_OFFSET] + ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode + ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC0_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC1_OFFSET] + ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET] + orr \value, \value, #EXTMEM_GPIO_BITSET + str \value, [\base, #STR71X_GPIO_PC2_OFFSET] /* Enable bank 0 */ - ldr \base, =STR71X_EMI_BASE + ldr \base, =STR71X_EMI_BASE #ifdef CONFIG_STR71X_BANK0 @@ -156,11 +156,11 @@ # define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON0_OFFSET] + str \value, [\base, #STR71X_EMI_BCON0_OFFSET] /* Enable bank 1 */ @@ -186,11 +186,11 @@ # define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON1_OFFSET] + str \value, [\base, #STR71X_EMI_BCON1_OFFSET] /* Enable bank 2 */ @@ -216,11 +216,11 @@ # define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON2_OFFSET] + str \value, [\base, #STR71X_EMI_BCON2_OFFSET] /* Enable bank 3 */ @@ -246,11 +246,11 @@ # define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2) # endif - ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE) + ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE) #else - mov \value, #0 + mov \value, #0 #endif - str \value, [\base, #STR71X_EMI_BCON3_OFFSET] + str \value, [\base, #STR71X_EMI_BCON3_OFFSET] #endif .endm @@ -277,42 +277,42 @@ .macro eicinit, eicbase, value, irqno, offset /* Disable and clear all interrupts */ - ldr \eicbase, =STR71X_EIC_BASE + ldr \eicbase, =STR71X_EIC_BASE /* Disable FIQ and IRQ */ - mov \value, #0 - str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET] + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET] /* Disable all channel interrupts */ - str \value, [\eicbase, #STR71X_EIC_IER_OFFSET] + str \value, [\eicbase, #STR71X_EIC_IER_OFFSET] /* Clear all pending IRQs */ - ldr \value, =0xffffffff - str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET] + ldr \value, =0xffffffff + str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET] /* Disable FIQ channels/clear pending FIQs */ - mov \value, #0x0c - str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET] + mov \value, #0x0c + str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET] /* Reset the current priority register */ - mov \value, #0 - str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET] + mov \value, #0 + str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET] /* Zero IVR 31:16 */ - str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET] + str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET] /* Set up the loop to initialize each SIR register. Start * with IRQ number 0 and SIR0 */ - mov \irqno, #0 - ldr \offset, =STR71X_EIC_SIR_OFFSET + mov \irqno, #0 + ldr \offset, =STR71X_EIC_SIR_OFFSET /* Then loop for each EIC channel */ eicloop: @@ -325,22 +325,22 @@ eicloop: * are all disabled. */ - mov \value, \irqno, lsl #16 - str \value, [\eicbase, \offset] + mov \value, \irqno, lsl #16 + str \value, [\eicbase, \offset] /* Increment the offset to the next SIR register and inrement * the IRQ number. */ - add \offset, \offset, #4 - add \irqno, \irqno, #1 + add \offset, \offset, #4 + add \irqno, \irqno, #1 /* Continue to loop until all of the SIR registers have been * initializeed. */ - cmp \irqno, #STR71X_EIC_NCHANNELS - blt eicloop + cmp \irqno, #STR71X_EIC_NCHANNELS + blt eicloop .endm /***************************************************************************** @@ -355,25 +355,26 @@ eicloop: #ifndef CONFIG_STR71X_DISABLE_PERIPHINIT /* Set up APB1 and APB2 addresses */ - ldr \base1, =STR71X_APB1_BASE - ldr \base2, =STR71X_APB2_BASE + ldr \base1, =STR71X_APB1_BASE + ldr \base2, =STR71X_APB2_BASE /* Disable all APB1 peripherals */ - ldr \value, =STR71X_APB1_APB1ALL + ldr \value, =STR71X_APB1_APB1ALL strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET] /* Disable all(or most) APB2 peripherals */ - ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC) + + ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC) strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET] /* Allow EMI and USB */ - ldr \base1, =STR71X_RCCU_BASE + ldr \base1, =STR71X_RCCU_BASE #ifdef CONFIG_STR71X_USB - ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL) + ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL) #else - ldr \value, =STR71X_RCCUPER_EMI + ldr \value, =STR71X_RCCUPER_EMI #endif strh \value, [\base1, #STR71X_RCCU_PER_OFFSET] #endif @@ -391,15 +392,16 @@ eicloop: *****************************************************************************/ .macro remap, base, value + /* Read the PCU BOOTCR register */ - ldr \base, =STR71X_PCU_BASE + ldr \base, =STR71X_PCU_BASE ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET] /* Mask out the old boot mode bits and set the boot mode to FLASH */ - bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK - orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH + bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK + orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH /* Save the modified BOOTCR register */ @@ -426,16 +428,16 @@ eicloop: .globl _vector_table .type _vector_table, %function _vector_table: - ldr pc, .Lresethandler /* 0x00: Reset */ - ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */ - ldr pc, .Lswihandler /* 0x08: Software interrupt */ - ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */ - ldr pc, .Ldataaborthandler /* 0x10: Data abort */ - .long 0 /* 0x14: Reserved vector */ - ldr pc, .Lirqhandler /* 0x18: IRQ */ - ldr pc, .Lfiqhandler /* 0x1c: FIQ */ + ldr pc, .Lresethandler /* 0x00: Reset */ + ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */ + ldr pc, .Lswihandler /* 0x08: Software interrupt */ + ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */ + ldr pc, .Ldataaborthandler /* 0x10: Data abort */ + .long 0 /* 0x14: Reserved vector */ + ldr pc, .Lirqhandler /* 0x18: IRQ */ + ldr pc, .Lfiqhandler /* 0x1c: FIQ */ - .globl __start + .globl __start .globl up_vectorundefinsn .globl up_vectorswi .globl up_vectorprefetch @@ -444,7 +446,7 @@ _vector_table: .globl up_vectorfiq .Lresethandler: - .long __start + .long __start .Lundefinedhandler: .long up_vectorundefinsn .Lswihandler: @@ -478,16 +480,16 @@ __start: * the aliased copy */ - ldr pc, =__flashstart + ldr pc, =__flashstart __flashstart: .rept 9 - nop /* Wait for OSC stabilization*/ + nop /* Wait for OSC stabilization */ .endr /* Setup the initial processor mode */ - mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT ) - msr cpsr, r0 + mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT ) + msr cpsr, r0 /* Initialize the external memory interface (EMI) */ @@ -499,7 +501,7 @@ __flashstart: /* Disable all peripherals except EIC */ - periphinit r0, r1, r2 + periphinit r0, r1, r2 /* Map memory appropriately for configuration */ @@ -507,42 +509,42 @@ __flashstart: /* Setup system stack (and get the BSS range) */ - adr r0, LC0 - ldmia r0, {r4, r5, sp} + adr r0, LC0 + ldmia r0, {r4, r5, sp} /* Clear system BSS section */ - mov r0, #0 -1: cmp r4, r5 + mov r0, #0 +1: cmp r4, r5 strcc r0, [r4], #4 - bcc 1b + bcc 1b /* Copy system .data sections from FLASH to new home in RAM. */ - adr r3, LC2 + adr r3, LC2 ldmia r3, {r0, r1, r2} 2: ldmia r0!, {r3 - r10} stmia r1!, {r3 - r10} - cmp r1, r2 - blt 2b + cmp r1, r2 + blt 2b /* Initialize clocking */ - bl str71x_prccuinit + bl str71x_prccuinit /* Configure the uart so that we can get debug output as soon * as possible. */ - bl up_lowsetup + bl up_lowsetup showprogress 'A' /* Perform early serial initialization */ - mov fp, #0 + mov fp, #0 #ifdef USE_EARLYSERIALINIT - bl up_earlyserialinit + bl up_earlyserialinit #endif showprogress 'B' @@ -550,17 +552,17 @@ __flashstart: /* Call C++ constructors */ #ifdef CONFIG_CPLUSPLUS - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + mov pc, r2 + ldmfd sp!, {r0-r1} + b ctor_loop ctor_end: showprogress 'C' @@ -570,27 +572,27 @@ ctor_end: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - bl board_led_initialize + bl board_autoled_initialize #endif /* Then jump to OS entry */ - b os_start + b os_start /* Call destructors -- never get here */ #if 0 /* CONFIG_CPLUSPLUS */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #4 + cmp r0, r1 + beq dtor_end + ldr r2, [r0], #4 stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 + mov lr, pc + mov pc, r2 ldmfd sp!, {r0-r1} - b dtor_loop + b dtor_loop dtor_end: #endif @@ -626,4 +628,3 @@ g_idle_topstack: .size g_idle_topstack, .-g_idle_topstack .end - diff --git a/arch/sh/src/m16c/m16c_head.S b/arch/sh/src/m16c/m16c_head.S index 06f40d225c..f18da3fe3f 100644 --- a/arch/sh/src/m16c/m16c_head.S +++ b/arch/sh/src/m16c/m16c_head.S @@ -60,8 +60,8 @@ .macro showprogress, code #ifdef CONFIG_DEBUG .globl _up_lowputc - mov.b r#\code1l /* Character to print */ - jsr.a _up_lowputc /* Print it */ + mov.b r#\code1l /* Character to print */ + jsr.a _up_lowputc /* Print it */ #endif .endm @@ -71,11 +71,11 @@ /* The near RAM memory map is as follows: * - * 0x00400 - DATA Size: Determined by linker - * BSS Size: Determined by linker + * 0x00400 - DATA Size: Determined by linker + * BSS Size: Determined by linker * Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK - * Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE - * Heap Size: Everything remaining + * Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE + * Heap Size: Everything remaining * 0x00bff - (end+1) */ @@ -174,48 +174,48 @@ __start: /* Set the interrupt and user stack pointers */ mov.w #_enbss, R0 - ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */ + ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */ add.w #CONFIG_IDLETHREAD_STACKSIZE, R0 - fset U /* Set bit 7 (U) to select the user stack pointer */ - ldc R0, sp /* Set the user stack pointer */ + fset U /* Set bit 7 (U) to select the user stack pointer */ + ldc R0, sp /* Set the user stack pointer */ /* Set BCLK speed. At reset, the processor clock (BLCK) defaults to a divisor of 8. * This sets clock to F1 (divide by 1) on XIN: BCLK = XIN frequency. */ - mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */ - mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1 - * CM17 & CM16 defaults to 0 after reset and - * so we only need to reset CM06 to 0 */ - mov.b #0x00,M16C_PRCR /* protect CM0 */ + mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */ + mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1 + * CM17 & CM16 defaults to 0 after reset and + * so we only need to reset CM06 to 0 */ + mov.b #0x00,M16C_PRCR /* protect CM0 */ /* The two MS bits of the interrupt cause select register must be set to * enable the use of INT4 and INT5 */ - mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */ - ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */ + mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */ + ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */ /* Set up INTB to point to location of variable vector table */ - mov.w _g_svarvect, r0 /* R0 = lower 16-bits */ - mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */ - ldc r1, intbh - ldc r0, intbl + mov.w _g_svarvect, r0 /* R0 = lower 16-bits */ + mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */ + ldc r1, intbh + ldc r0, intbl /* Configure the uart so that we can get debug output as soon as possible. */ - .globl _up_lowsetup /* Early initialization of UART */ + .globl _up_lowsetup /* Early initialization of UART */ jsr.a _up_lowsetup showprogress 'A' /* Clear near .bss sections */ - mov.b #0x00, r0l /* r0l: 0 */ - mov.w _g_snbss, a1 /* a1: start of near .bss */ - mov.w _g_enbss, r3 /* r3: end of near .bss */ - sub.w a1, r3 /* r3: size of near .bss */ - sstr.b /* Clear near .bss */ + mov.b #0x00, r0l /* r0l: 0 */ + mov.w _g_snbss, a1 /* a1: start of near .bss */ + mov.w _g_enbss, r3 /* r3: end of near .bss */ + sub.w a1, r3 /* r3: size of near .bss */ + sstr.b /* Clear near .bss */ /* Clear far .bss sections */ @@ -227,12 +227,12 @@ __start: /* Initialize near .data sections (.rodata is not moved) */ - mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */ - mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */ - mov.w _g_sndata, a1 /* a1: start of near .data */ - mov.w _g_endata, r3 /* r3: end of near .data */ - sub.w a1, r3 /* r3: size of near .data */ - smovf.b /* Copy source to near .data */ + mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */ + mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */ + mov.w _g_sndata, a1 /* a1: start of near .data */ + mov.w _g_endata, r3 /* r3: end of near .data */ + sub.w a1, r3 /* r3: size of near .data */ + smovf.b /* Copy source to near .data */ /* Initialize far .data sections (.rodata is not moved) */ @@ -245,8 +245,8 @@ __start: /* Perform early console initialization */ #ifdef USE_EARLYSERIALINIT - .globl _up_earlyconsoleinit /* Early initialization of console driver */ - jsr.a _up_earlyconsoleinit /* Call it */ + .globl _up_earlyconsoleinit /* Early initialization of console driver */ + jsr.a _up_earlyconsoleinit /* Call it */ showprogress 'D' #endif @@ -260,8 +260,8 @@ __start: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - .globl _board_led_initialize /* Boot LED setup */ - jsr.a _board_led_initialize /* Call it */ + .globl _board_autoled_initialize /* Boot LED setup */ + jsr.a _board_autoled_initialize /* Call it */ #endif showprogress '\n' diff --git a/arch/sh/src/sh1/sh1_head.S b/arch/sh/src/sh1/sh1_head.S index f0f70de1f7..9bb4efb1f5 100644 --- a/arch/sh/src/sh1/sh1_head.S +++ b/arch/sh/src/sh1/sh1_head.S @@ -60,31 +60,32 @@ /* Called functions */ - .globl _up_lowsetup /* Early initialization of UART */ + .globl _up_lowsetup /* Early initialization of UART */ #ifdef USE_EARLYSERIALINIT - .globl _up_earlyconsoleinit /* Early initialization of console driver */ + .globl _up_earlyconsoleinit /* Early initialization of console driver */ #endif #ifdef CONFIG_ARCH_LEDS - .globl _board_led_initialize /* Boot LED setup */ + .globl _board_autoled_initialize /* Boot LED setup */ #endif #ifdef CONFIG_DEBUG - .globl _up_lowputc /* Low-level debug output */ + .globl _up_lowputc /* Low-level debug output */ #endif - .globl _os_start /* NuttX entry point */ + .globl _os_start /* NuttX entry point */ /* Variables set up by the linker script */ - .globl _sbss /* Start of BSS */ - .globl _ebss /* End of BSS */ - .globl _svect /* Start of the new vector location */ + .globl _sbss /* Start of BSS */ + .globl _ebss /* End of BSS */ + .globl _svect /* Start of the new vector location */ #ifdef CONFIG_BOOT_RUNFROMFLASH - .globl _eronly /* Where .data defaults are stored in FLASH */ - .global _sdata /* Start of .data in RAM */ - .globl _edata /* End of .data in RAM */ + .globl _eronly /* Where .data defaults are stored in FLASH */ + .global _sdata /* Start of .data in RAM */ + .globl _edata /* End of .data in RAM */ #endif /* Interrupt handlers */ + .globl _up_invalid_handler #ifdef CONFIG_SH1_DMAC0 .globl _up_dmac0_handler @@ -161,9 +162,9 @@ .macro showprogress, code #ifdef CONFIG_DEBUG - mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */ - jsr @r0 /* Call it */ - mov #\code, r4 /* Delay slot */ + mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */ + jsr @r0 /* Call it */ + mov #\code, r4 /* Delay slot */ #endif .endm @@ -191,128 +192,128 @@ __vector_table: * vectors. */ - .long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */ + .long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */ .long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 - .long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */ + .long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */ .long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 - .rept SH1_NCMN_VECTORS-4 + .rept SH1_NCMN_VECTORS-4 .long _up_invalid_handler .endr /* The remaining vectors are unique to the SH-1 703x family */ #ifdef CONFIG_SH1_DMAC0 - .long _up_dmac0_handler /* 72: DMAC0 DEI0 */ + .long _up_dmac0_handler /* 72: DMAC0 DEI0 */ #else - .long _up_invalid_handler /* 72: DMAC0 DEI0 */ + .long _up_invalid_handler /* 72: DMAC0 DEI0 */ #endif - .long _up_invalid_handler /* 73: Reserved */ + .long _up_invalid_handler /* 73: Reserved */ #ifdef CONFIG_SH1_DMAC1 - .long _up_dmac1_handler /* 74: DMAC1 DEI1 */ + .long _up_dmac1_handler /* 74: DMAC1 DEI1 */ #else - .long _up_invalid_handler /* 74: DMAC1 DEI1 */ + .long _up_invalid_handler /* 74: DMAC1 DEI1 */ #endif - .long _up_invalid_handler /* 75: Reserved */ + .long _up_invalid_handler /* 75: Reserved */ #ifdef CONFIG_SH1_DMAC2 - .long _up_dmac2_handler /* 76: DMAC2 DEI2 */ + .long _up_dmac2_handler /* 76: DMAC2 DEI2 */ #else - .long _up_invalid_handler /* 76: DMAC2 DEI2 */ + .long _up_invalid_handler /* 76: DMAC2 DEI2 */ #endif - .long _up_invalid_handler /* 77: Reserved */ + .long _up_invalid_handler /* 77: Reserved */ #ifdef CONFIG_SH1_DMAC3 - .long _up_dmac3_handler /* 78: DMAC3 DEI3 */ + .long _up_dmac3_handler /* 78: DMAC3 DEI3 */ #else - .long _up_invalid_handler /* 78: DMAC3 DEI3 */ + .long _up_invalid_handler /* 78: DMAC3 DEI3 */ #endif - .long _up_invalid_handler /* 79: Reserved */ - .long _up_imia0_handler /* 80: ITU0 IMIA0 */ - .long _up_imib0_handler /* 81: IMIB0 */ - .long _up_ovi0_handler /* 82: OVI0 */ - .long _up_invalid_handler /* 83: Reserved */ + .long _up_invalid_handler /* 79: Reserved */ + .long _up_imia0_handler /* 80: ITU0 IMIA0 */ + .long _up_imib0_handler /* 81: IMIB0 */ + .long _up_ovi0_handler /* 82: OVI0 */ + .long _up_invalid_handler /* 83: Reserved */ #ifdef CONFIG_SH1_ITU1 - .long _up_imia1_handler /* 84: ITU1 IMIA1 */ - .long _up_imib1_handler /* 85: IMIB1 */ - .long _up_ovi1_handler /* 86: OVI1 */ + .long _up_imia1_handler /* 84: ITU1 IMIA1 */ + .long _up_imib1_handler /* 85: IMIB1 */ + .long _up_ovi1_handler /* 86: OVI1 */ #else - .long _up_invalid_handler /* 84: ITU1 IMIA1 */ - .long _up_invalid_handler /* 85: IMIB1 */ - .long _up_invalid_handler /* 86: OVI1 */ + .long _up_invalid_handler /* 84: ITU1 IMIA1 */ + .long _up_invalid_handler /* 85: IMIB1 */ + .long _up_invalid_handler /* 86: OVI1 */ #endif - .long _up_invalid_handler /* 87: Reserved */ + .long _up_invalid_handler /* 87: Reserved */ #ifdef CONFIG_SH1_ITU2 - .long _up_imia2_handler /* 88: ITU2 IMIA2 */ - .long _up_imib2_handler /* 89: IMIB2 */ - .long _up_ovi2_handler /* 90: OVI2 */ + .long _up_imia2_handler /* 88: ITU2 IMIA2 */ + .long _up_imib2_handler /* 89: IMIB2 */ + .long _up_ovi2_handler /* 90: OVI2 */ #else - .long _up_invalid_handler /* 88: ITU2 IMIA2 */ - .long _up_invalid_handler /* 89: IMIB2 */ - .long _up_invalid_handler /* 90: OVI2 */ + .long _up_invalid_handler /* 88: ITU2 IMIA2 */ + .long _up_invalid_handler /* 89: IMIB2 */ + .long _up_invalid_handler /* 90: OVI2 */ #endif - .long _up_invalid_handler /* 91: Reserved */ + .long _up_invalid_handler /* 91: Reserved */ #ifdef CONFIG_SH1_ITU3 - .long _up_imia3_handler /* 92: ITU3 IMIA3 */ - .long _up_imib3_handler /* 93: IMIB3 */ - .long _up_ovi3_handler /* 94: OVI3 */ + .long _up_imia3_handler /* 92: ITU3 IMIA3 */ + .long _up_imib3_handler /* 93: IMIB3 */ + .long _up_ovi3_handler /* 94: OVI3 */ #else - .long _up_invalid_handler /* 92: ITU3 IMIA3 */ - .long _up_invalid_handler /* 93: IMIB3 */ - .long _up_invalid_handler /* 94: OVI3 */ + .long _up_invalid_handler /* 92: ITU3 IMIA3 */ + .long _up_invalid_handler /* 93: IMIB3 */ + .long _up_invalid_handler /* 94: OVI3 */ #endif - .long _up_invalid_handler /* 95: Reserved */ + .long _up_invalid_handler /* 95: Reserved */ #ifdef CONFIG_SH1_ITU4 - .long _up_imia4_handler /* 96: ITU4 IMIA4 */ - .long _up_imib4_handler /* 97: IMIB4 */ - .long _up_ovi4_handler /* 98: OVI4 */ + .long _up_imia4_handler /* 96: ITU4 IMIA4 */ + .long _up_imib4_handler /* 97: IMIB4 */ + .long _up_ovi4_handler /* 98: OVI4 */ #else - .long _up_invalid_handler /* 96: ITU4 IMIA4 */ - .long _up_invalid_handler /* 97: IMIB4 */ - .long _up_invalid_handler /* 98: OVI4 */ + .long _up_invalid_handler /* 96: ITU4 IMIA4 */ + .long _up_invalid_handler /* 97: IMIB4 */ + .long _up_invalid_handler /* 98: OVI4 */ #endif - .long _up_invalid_handler /* 99: Reserved */ + .long _up_invalid_handler /* 99: Reserved */ #ifdef CONFIG_SH1_SCI0 - .long _up_eri0_handler /* 100: SCI0 ERI0 */ - .long _up_rxi0_handler /* 101: RxI0 */ - .long _up_txi0_handler /* 102: TxI0 */ - .long _up_tei0_handler /* 103: TEI0 */ + .long _up_eri0_handler /* 100: SCI0 ERI0 */ + .long _up_rxi0_handler /* 101: RxI0 */ + .long _up_txi0_handler /* 102: TxI0 */ + .long _up_tei0_handler /* 103: TEI0 */ #else - .long _up_invalid_handler /* 100: SCI0 ERI0 */ - .long _up_invalid_handler /* 101: RxI0 */ - .long _up_invalid_handler /* 102: TxI0 */ - .long _up_invalid_handler /* 103: TEI0 */ + .long _up_invalid_handler /* 100: SCI0 ERI0 */ + .long _up_invalid_handler /* 101: RxI0 */ + .long _up_invalid_handler /* 102: TxI0 */ + .long _up_invalid_handler /* 103: TEI0 */ #endif #ifdef CONFIG_SH1_SCI1 - .long _up_eri1_handler /* 104: SCI1 ERI1 */ - .long _up_rxi1_handler /* 105: RxI1 */ - .long _up_txi1_handler /* 106: TxI1 */ - .long _up_tei1_handler /* 107: TEI1 */ + .long _up_eri1_handler /* 104: SCI1 ERI1 */ + .long _up_rxi1_handler /* 105: RxI1 */ + .long _up_txi1_handler /* 106: TxI1 */ + .long _up_tei1_handler /* 107: TEI1 */ #else - .long _up_invalid_handler /* 104: SCI1 ERI1 */ - .long _up_invalid_handler /* 105: RxI1 */ - .long _up_invalid_handler /* 106: TxI1 */ - .long _up_invalid_handler /* 107: TEI1 */ + .long _up_invalid_handler /* 104: SCI1 ERI1 */ + .long _up_invalid_handler /* 105: RxI1 */ + .long _up_invalid_handler /* 106: TxI1 */ + .long _up_invalid_handler /* 107: TEI1 */ #endif #ifdef CONFIG_SH1_PCU - .long _up_pei_handler /* 108: Parity control unit PEI */ + .long _up_pei_handler /* 108: Parity control unit PEI */ #else - .long _up_invalid_handler /* 108: Parity control unit PEI */ + .long _up_invalid_handler /* 108: Parity control unit PEI */ #endif #ifdef CONFIG_SH1_AD - .long _up_aditi_handler /* 109: A/D ITI */ + .long _up_aditi_handler /* 109: A/D ITI */ #else - .long _up_invalid_handler /* 109: A/D ITI */ + .long _up_invalid_handler /* 109: A/D ITI */ #endif - .long _up_invalid_handler /* 110: Reserved */ - .long _up_invalid_handler /* 111: Reserved */ + .long _up_invalid_handler /* 110: Reserved */ + .long _up_invalid_handler /* 111: Reserved */ #ifdef CONFIG_SH1_WDT - .long _up_wdt_handler /* 112: WDT ITI */ + .long _up_wdt_handler /* 112: WDT ITI */ #else - .long _up_invalid_handler /* 112: WDT ITI */ + .long _up_invalid_handler /* 112: WDT ITI */ #endif #ifdef CONFIG_SH1_CMI - .long _up_cmi_handler /* 113: REF CMI */ + .long _up_cmi_handler /* 113: REF CMI */ #else - .long _up_invalid_handler /* 113: REF CMI */ + .long _up_invalid_handler /* 113: REF CMI */ #endif .rept (SH1_LAST_VNDX-SH1_CMI_VNDX) /* 114-255: Reserved */ .long _up_invalid_handler @@ -346,15 +347,15 @@ __start: /* set up the bus controller for the EVB */ mov.l .Lwcr1, r0 - sub r1,r1 + sub r1,r1 mov.w r1, @r0 /* Configure the BSR to use /LBS, /HBS, /WR */ - mov.l .Lbcr, r0 - mov.w .Lbas, r1 - bra __start0 - mov.w r1, @r0 + mov.l .Lbcr, r0 + mov.w .Lbas, r1 + bra __start0 + mov.w r1, @r0 .align 2 .Lstack: @@ -369,67 +370,67 @@ __start: __start0: /* Copy the monitor vectors to a002000-a00211f */ - mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */ - mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */ - mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */ + mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */ + mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */ + mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */ 1: - mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */ - mov.l r2, @r1 /* Write into SRAM vector table */ - add #4, r0 /* R0: Address of next vector to read from monitor vector table */ - add #4, r1 /* R1: Address of next vector to write to SRAM vector table */ - cmp/gt r0, r3 /* Copy only only up to external interrupts at */ - bt 1b /* Continue looping until all copied */ - nop /* Delay slot */ + mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */ + mov.l r2, @r1 /* Write into SRAM vector table */ + add #4, r0 /* R0: Address of next vector to read from monitor vector table */ + add #4, r1 /* R1: Address of next vector to write to SRAM vector table */ + cmp/gt r0, r3 /* Copy only only up to external interrupts at */ + bt 1b /* Continue looping until all copied */ + nop /* Delay slot */ /* Update the VBR to show new adddress of vector table */ - mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */ - ldc r0, vbr /* Set VBR to start of SRAM vector table */ + mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */ + ldc r0, vbr /* Set VBR to start of SRAM vector table */ /* Initialize data segement */ #ifdef CONFIG_BOOT_RUNFROMFLASH - mov.l .Lsdata, r0 /* R0: Start of .data segment */ - mov.l .Ledata, r1 /* R1: End+1 of .data segment */ - mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */ + mov.l .Lsdata, r0 /* R0: Start of .data segment */ + mov.l .Ledata, r1 /* R1: End+1 of .data segment */ + mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */ 2: - mov.l @r2, r3 /* R3: Next byte from FLASH copy */ - mov.l r3, @r0 /* Copy to .data */ - add #4, r2 /* R2: Address of next byte to read from FLASH */ - add #4, r0 /* R0: Address to write next byte to .data */ - cmp/gt r0, r1 /* End of .data? */ - bt 2b /* Loop until end of data */ - nop /* Delay slot */ + mov.l @r2, r3 /* R3: Next byte from FLASH copy */ + mov.l r3, @r0 /* Copy to .data */ + add #4, r2 /* R2: Address of next byte to read from FLASH */ + add #4, r0 /* R0: Address to write next byte to .data */ + cmp/gt r0, r1 /* End of .data? */ + bt 2b /* Loop until end of data */ + nop /* Delay slot */ #endif /* Clear BSS */ - mov.l .Lsbss, r0 /* R0: Start of BSS segment */ - mov.l .Lebss, r1 /* R1: End+1 of BSS segment */ - mov #0, r2 /* R2: Value = 0 */ + mov.l .Lsbss, r0 /* R0: Start of BSS segment */ + mov.l .Lebss, r1 /* R1: End+1 of BSS segment */ + mov #0, r2 /* R2: Value = 0 */ 3: - mov.l r2, @r0 /* Clear the next word in BSS */ - add #4, r0 /* R0: Address of next byte to clear in BSS */ - cmp/ge r0, r1 /* End of BSS? */ - bt 3b /* Loop until the end of BSS */ - nop /* Delay slot */ + mov.l r2, @r0 /* Clear the next word in BSS */ + add #4, r0 /* R0: Address of next byte to clear in BSS */ + cmp/ge r0, r1 /* End of BSS? */ + bt 3b /* Loop until the end of BSS */ + nop /* Delay slot */ /* Configure the uart so that we can get debug output as soon * as possible. */ - mov.l .Llowsetup, r0 /* Address of up_lowsetup */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Llowsetup, r0 /* Address of up_lowsetup */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ showprogress 'A' /* Perform early console initialization */ #ifdef USE_EARLYSERIALINIT - mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ #endif showprogress 'B' @@ -445,16 +446,16 @@ __start0: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - mov.l .Lledinit, r0 /* Address of board_led_initialize */ - jsr @r0 /* Call it */ - or r0, r0 /* Delay slot */ + mov.l .Lledinit, r0 /* Address of board_autoled_initialize */ + jsr @r0 /* Call it */ + or r0, r0 /* Delay slot */ #endif /* Then jump to NuttX entry */ - mov.l .Losstart,r0 - jsr @r0 - or r0, r0 + mov.l .Losstart,r0 + jsr @r0 + or r0, r0 /* Shouldn't get here */ @@ -471,16 +472,16 @@ __start0: .align 2 #ifdef CONFIG_BOOT_RUNFROMFLASH .Leronly: - .long _eronly + .long _eronly .Lsdata: - .long _sdata + .long _sdata .Ledata: - .long _edata + .long _edata #endif .Lsbss: - .long _sbss + .long _sbss .Lebss: - .long _ebss + .long _ebss #ifdef USE_EARLYSERIALINIT .Learlyconsole: .long _up_earlyconsoleinit @@ -492,13 +493,13 @@ __start0: .long _up_lowputc #endif .Lledinit: - .long _board_led_initialize + .long _board_autoled_initialize .Losstart: - .long _os_start + .long _os_start .Lsvect: - .long _svect + .long _svect .Lvectend: - .long ((4*SH1_NCMN_VECTORS)-1) + .long ((4*SH1_NCMN_VECTORS)-1) .size __start, .-__start /***************************************************************************** @@ -521,4 +522,3 @@ _g_idle_topstack: .size _g_idle_topstack, .-_g_idle_topstack .end - diff --git a/arch/z16/src/z16f/z16f_head.S b/arch/z16/src/z16f/z16f_head.S index 511940c8a6..1ceccf9333 100755 --- a/arch/z16/src/z16f/z16f_head.S +++ b/arch/z16/src/z16f/z16f_head.S @@ -54,7 +54,7 @@ xref _z16f_clkinit:EROM xref _z16f_lowinit:EROM #ifdef CONFIG_ARCH_LEDS - xref _board_led_initialize:EROM + xref _board_autoled_initialize:EROM #endif #if defined(USE_LOWUARTINIT) xref _z16f_lowuartinit:EROM @@ -158,7 +158,7 @@ _z16f_reset: /* Initialize onboard LEDs */ #ifdef CONFIG_ARCH_LEDS - call _board_led_initialize + call _board_autoled_initialize #endif /* Perform VERY early UART initialization so that we can use it here */ diff --git a/arch/z80/src/z8/z8_head.S b/arch/z80/src/z8/z8_head.S index 9ad7e4f160..a211e27021 100755 --- a/arch/z80/src/z8/z8_head.S +++ b/arch/z80/src/z8/z8_head.S @@ -68,7 +68,7 @@ xref _z16f_clkinit:ROM xref _z16f_lowinit:ROM #ifdef CONFIG_ARCH_LEDS - xref _board_led_initialize:ROM + xref _board_autoled_initialize:ROM #endif xref _os_start:ROM xref _up_doirq:ROM From b28e32e3d317d64d49d05b86bccb235f9402017c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:07:06 -0600 Subject: [PATCH 20/41] Rename board_led_on to board_autoled_on --- arch/arm/src/arm/up_assert.c | 4 ++-- arch/arm/src/arm/up_doirq.c | 2 +- arch/arm/src/arm/up_sigdeliver.c | 2 +- arch/arm/src/armv6-m/up_assert.c | 4 ++-- arch/arm/src/armv6-m/up_doirq.c | 2 +- arch/arm/src/armv6-m/up_sigdeliver.c | 2 +- arch/arm/src/armv7-a/arm_assert.c | 4 ++-- arch/arm/src/armv7-a/arm_doirq.c | 2 +- arch/arm/src/armv7-a/arm_sigdeliver.c | 2 +- arch/arm/src/armv7-m/up_assert.c | 4 ++-- arch/arm/src/armv7-m/up_doirq.c | 2 +- arch/arm/src/armv7-m/up_sigdeliver.c | 2 +- arch/arm/src/common/up_allocateheap.c | 4 ++-- arch/arm/src/common/up_createstack.c | 2 +- arch/arm/src/common/up_initialize.c | 2 +- arch/arm/src/dm320/dm320_allocateheap.c | 2 +- arch/arm/src/efm32/efm32_idle.c | 2 +- arch/arm/src/imx/imx_allocateheap.c | 2 +- arch/arm/src/kinetis/kinetis_allocateheap.c | 4 ++-- arch/arm/src/kinetis/kinetis_idle.c | 2 +- arch/arm/src/kl/kl_idle.c | 2 +- arch/arm/src/lpc11xx/lpc11_idle.c | 2 +- arch/arm/src/lpc17xx/lpc17_allocateheap.c | 4 ++-- arch/arm/src/lpc17xx/lpc17_idle.c | 2 +- arch/arm/src/lpc31xx/lpc31_allocateheap.c | 2 +- arch/arm/src/lpc43xx/lpc43_allocateheap.c | 2 +- arch/arm/src/lpc43xx/lpc43_idle.c | 2 +- arch/arm/src/nuc1xx/nuc_idle.c | 2 +- arch/arm/src/sam34/sam_allocateheap.c | 4 ++-- arch/arm/src/sama5/sam_allocateheap.c | 4 ++-- arch/arm/src/samdl/sam_idle.c | 2 +- arch/arm/src/samv7/sam_allocateheap.c | 4 ++-- arch/arm/src/stm32/stm32_allocateheap.c | 4 ++-- arch/arm/src/stm32/stm32_idle.c | 2 +- arch/arm/src/stm32f7/stm32_allocateheap.c | 4 ++-- arch/arm/src/str71x/str71x_decodeirq.c | 4 ++-- arch/arm/src/tiva/tiva_allocateheap.c | 4 ++-- arch/avr/src/avr/up_createstack.c | 2 +- arch/avr/src/avr/up_doirq.c | 2 +- arch/avr/src/avr/up_sigdeliver.c | 2 +- arch/avr/src/avr32/up_createstack.c | 2 +- arch/avr/src/avr32/up_doirq.c | 2 +- arch/avr/src/avr32/up_sigdeliver.c | 2 +- arch/avr/src/common/up_allocateheap.c | 2 +- arch/avr/src/common/up_assert.c | 4 ++-- arch/avr/src/common/up_initialize.c | 2 +- arch/hc/src/common/up_allocateheap.c | 2 +- arch/hc/src/common/up_createstack.c | 2 +- arch/hc/src/common/up_doirq.c | 2 +- arch/hc/src/common/up_initialize.c | 2 +- arch/hc/src/m9s12/m9s12_assert.c | 4 ++-- arch/mips/src/common/up_allocateheap.c | 2 +- arch/mips/src/common/up_createstack.c | 2 +- arch/mips/src/common/up_initialize.c | 2 +- arch/mips/src/mips32/up_assert.c | 4 ++-- arch/mips/src/mips32/up_doirq.c | 2 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/pic32mx/pic32mx-decodeirq.c | 2 +- arch/mips/src/pic32mx/pic32mx-exception.c | 2 +- arch/mips/src/pic32mz/pic32mz-decodeirq.c | 2 +- arch/mips/src/pic32mz/pic32mz-exception.c | 2 +- arch/sh/src/common/up_allocateheap.c | 2 +- arch/sh/src/common/up_assert.c | 4 ++-- arch/sh/src/common/up_createstack.c | 2 +- arch/sh/src/common/up_doirq.c | 2 +- arch/sh/src/common/up_initialize.c | 2 +- arch/sh/src/m16c/m16c_sigdeliver.c | 2 +- arch/sh/src/sh1/sh1_sigdeliver.c | 2 +- arch/x86/src/common/up_allocateheap.c | 2 +- arch/x86/src/common/up_assert.c | 4 ++-- arch/x86/src/common/up_initialize.c | 2 +- arch/x86/src/i486/up_createstack.c | 2 +- arch/x86/src/i486/up_sigdeliver.c | 2 +- arch/x86/src/qemu/qemu_handlers.c | 10 +++++----- arch/z16/src/common/up_allocateheap.c | 2 +- arch/z16/src/common/up_assert.c | 4 ++-- arch/z16/src/common/up_createstack.c | 2 +- arch/z16/src/common/up_doirq.c | 2 +- arch/z16/src/common/up_idle.c | 2 +- arch/z16/src/common/up_initialize.c | 2 +- arch/z16/src/common/up_sigdeliver.c | 2 +- arch/z80/src/common/up_allocateheap.c | 2 +- arch/z80/src/common/up_assert.c | 4 ++-- arch/z80/src/common/up_createstack.c | 2 +- arch/z80/src/common/up_doirq.c | 2 +- arch/z80/src/common/up_idle.c | 2 +- arch/z80/src/common/up_initialize.c | 2 +- arch/z80/src/ez80/ez80_sigdeliver.c | 2 +- arch/z80/src/z180/z180_sigdeliver.c | 2 +- arch/z80/src/z8/z8_sigdeliver.c | 2 +- arch/z80/src/z80/z80_sigdeliver.c | 2 +- 91 files changed, 116 insertions(+), 116 deletions(-) diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index f8cd706fa5..c9ed3cff3b 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -316,7 +316,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -343,7 +343,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c index 35ba735cdb..7df75a436d 100644 --- a/arch/arm/src/arm/up_doirq.c +++ b/arch/arm/src/arm/up_doirq.c @@ -74,7 +74,7 @@ void up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index 625a0993ae..38127a706a 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index 4c570637a5..9f196926a3 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -371,7 +371,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -398,7 +398,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv6-m/up_doirq.c b/arch/arm/src/armv6-m/up_doirq.c index 54557585f2..4be88b4c08 100644 --- a/arch/arm/src/armv6-m/up_doirq.c +++ b/arch/arm/src/armv6-m/up_doirq.c @@ -72,7 +72,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c index f0f4dd54bf..153c9bd4d0 100644 --- a/arch/arm/src/armv6-m/up_sigdeliver.c +++ b/arch/arm/src/armv6-m/up_sigdeliver.c @@ -98,7 +98,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 19630740eb..166de067ac 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -371,7 +371,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -397,7 +397,7 @@ void up_assert(const uint8_t *filename, int lineno) #ifdef CONFIG_PRINT_TASKNAME struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index d126f565db..f62fc7f60c 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -74,7 +74,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 0ea2b4c13e..1cfa888421 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index 0a264cb8cb..74ac5e30e5 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -380,7 +380,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -407,7 +407,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 0582000c58..27740d2704 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -72,7 +72,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index df5c17fbcf..085380fb5a 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/arm/src/common/up_allocateheap.c b/arch/arm/src/common/up_allocateheap.c index f1f219ebc8..b4aa3d05d0 100644 --- a/arch/arm/src/common/up_allocateheap.c +++ b/arch/arm/src/common/up_allocateheap.c @@ -142,14 +142,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; #else /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c index 7cec83a18f..5d03ee4556 100644 --- a/arch/arm/src/common/up_createstack.c +++ b/arch/arm/src/common/up_createstack.c @@ -227,7 +227,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size); #endif - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 21b5ea2d6e..2cb332671b 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -275,5 +275,5 @@ void up_initialize(void) /* Initialize the L2 cache if present and selected */ up_l2ccinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/arm/src/dm320/dm320_allocateheap.c b/arch/arm/src/dm320/dm320_allocateheap.c index c6802c4c5c..d1a96f8020 100644 --- a/arch/arm/src/dm320/dm320_allocateheap.c +++ b/arch/arm/src/dm320/dm320_allocateheap.c @@ -85,7 +85,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack; } diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c index 5740d14f6a..75c9905c1b 100644 --- a/arch/arm/src/efm32/efm32_idle.c +++ b/arch/arm/src/efm32/efm32_idle.c @@ -61,7 +61,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/imx/imx_allocateheap.c b/arch/arm/src/imx/imx_allocateheap.c index 2447d6a2b2..179c4751ed 100644 --- a/arch/arm/src/imx/imx_allocateheap.c +++ b/arch/arm/src/imx/imx_allocateheap.c @@ -85,7 +85,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack; } diff --git a/arch/arm/src/kinetis/kinetis_allocateheap.c b/arch/arm/src/kinetis/kinetis_allocateheap.c index ac96b2d455..1eb21eeb4d 100644 --- a/arch/arm/src/kinetis/kinetis_allocateheap.c +++ b/arch/arm/src/kinetis/kinetis_allocateheap.c @@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/kinetis/kinetis_idle.c b/arch/arm/src/kinetis/kinetis_idle.c index 8e58beb884..b47e56a668 100644 --- a/arch/arm/src/kinetis/kinetis_idle.c +++ b/arch/arm/src/kinetis/kinetis_idle.c @@ -54,7 +54,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index a198ad8b27..8e34a7a1a4 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c index f258c2b0c9..e45cf3068b 100644 --- a/arch/arm/src/lpc11xx/lpc11_idle.c +++ b/arch/arm/src/lpc11xx/lpc11_idle.c @@ -53,7 +53,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c index e6969326b6..20568f0457 100644 --- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -260,7 +260,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/lpc17xx/lpc17_idle.c b/arch/arm/src/lpc17xx/lpc17_idle.c index baf62b0155..db90892e44 100644 --- a/arch/arm/src/lpc17xx/lpc17_idle.c +++ b/arch/arm/src/lpc17xx/lpc17_idle.c @@ -55,7 +55,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/arch/arm/src/lpc31xx/lpc31_allocateheap.c index b6d77b190a..9c54871eaf 100644 --- a/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -180,7 +180,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = LPC31_HEAP_VEND - g_idle_topstack; } diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c index b914b4d8bb..243ea98b61 100644 --- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c +++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { /* Start with the first SRAM region */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index 029a55f1f8..476c36c91f 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -57,7 +57,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index 3236b572c8..d656767e7e 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index 0f0b981ee4..3e1d5e6efe 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -230,7 +230,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -241,7 +241,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index 33e4fe1c6a..14388795f9 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -258,7 +258,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * heap is at the end of BSS through the configured end of SDRAM. */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)&_ebss; *heap_size = SAMA5_PRIMARY_HEAP_END - (size_t)&_ebss; @@ -267,7 +267,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * IDLE stack through the configured end of ISRAM. */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SAMA5_PRIMARY_HEAP_END - g_idle_topstack; #endif diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c index f0baac5f9b..743b26a4f7 100644 --- a/arch/arm/src/samdl/sam_idle.c +++ b/arch/arm/src/samdl/sam_idle.c @@ -58,7 +58,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index 65ba3f425f..1e8dc08796 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -237,7 +237,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 8350b859e1..8a844b6d22 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -511,7 +511,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -526,7 +526,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SRAM1_END - g_idle_topstack; diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c index 7108956cae..2934cc3e4c 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/stm32/stm32_idle.c @@ -60,7 +60,7 @@ */ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) # define END_IDLE() board_led_off(LED_IDLE) #else # define BEGIN_IDLE() diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 628a83ff4f..919890b833 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -255,7 +255,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = SRAM1_END - g_idle_topstack; diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c index 363590f266..72e4da677c 100644 --- a/arch/arm/src/str71x/str71x_decodeirq.c +++ b/arch/arm/src/str71x/str71x_decodeirq.c @@ -90,7 +90,7 @@ void up_decodeirq(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); lowsyslog(LOG_ERR, "Unexpected IRQ\n"); current_regs = regs; PANIC(); @@ -101,7 +101,7 @@ void up_decodeirq(uint32_t *regs) * info from CIC register without the setup). */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); irq = getreg32(STR71X_EIC_IVR); /* Verify that the resulting IRQ number is valid */ diff --git a/arch/arm/src/tiva/tiva_allocateheap.c b/arch/arm/src/tiva/tiva_allocateheap.c index 4bca5ff2bd..06df87bb31 100644 --- a/arch/arm/src/tiva/tiva_allocateheap.c +++ b/arch/arm/src/tiva/tiva_allocateheap.c @@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)ubase; *heap_size = usize; @@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif diff --git a/arch/avr/src/avr/up_createstack.c b/arch/avr/src/avr/up_createstack.c index 3a30888ab6..781258e702 100644 --- a/arch/avr/src/avr/up_createstack.c +++ b/arch/avr/src/avr/up_createstack.c @@ -160,7 +160,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR void *)top_of_stack; tcb->adj_stack_size = stack_size; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/avr/src/avr/up_doirq.c b/arch/avr/src/avr/up_doirq.c index a6768cf199..b692420a4d 100644 --- a/arch/avr/src/avr/up_doirq.c +++ b/arch/avr/src/avr/up_doirq.c @@ -72,7 +72,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index ae2d70f8e3..92604bcf14 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/avr/src/avr32/up_createstack.c b/arch/avr/src/avr32/up_createstack.c index f4ad76a679..db76abc38d 100644 --- a/arch/avr/src/avr32/up_createstack.c +++ b/arch/avr/src/avr32/up_createstack.c @@ -186,7 +186,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR void *)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/avr/src/avr32/up_doirq.c b/arch/avr/src/avr32/up_doirq.c index ba0dfe4cca..6acf3c9f09 100644 --- a/arch/avr/src/avr32/up_doirq.c +++ b/arch/avr/src/avr32/up_doirq.c @@ -74,7 +74,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index 691fe8cc8f..e4be7e7d16 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -96,7 +96,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/avr/src/common/up_allocateheap.c b/arch/avr/src/common/up_allocateheap.c index 7e2c03022a..052876f674 100644 --- a/arch/avr/src/common/up_allocateheap.c +++ b/arch/avr/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index a1a2295685..cddb4a7c86 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -111,7 +111,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index fdd05dd72f..f44b421c6d 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -286,6 +286,6 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/hc/src/common/up_allocateheap.c b/arch/hc/src/common/up_allocateheap.c index fb1a24f177..946fbf69ec 100644 --- a/arch/hc/src/common/up_allocateheap.c +++ b/arch/hc/src/common/up_allocateheap.c @@ -81,7 +81,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/hc/src/common/up_createstack.c b/arch/hc/src/common/up_createstack.c index 278a643f7b..9afb471e47 100644 --- a/arch/hc/src/common/up_createstack.c +++ b/arch/hc/src/common/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index 1a81731dc0..a0cb7998aa 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -74,7 +74,7 @@ uint8_t *up_doirq(int irq, uint8_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index 315064354f..5628c3aaec 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -210,5 +210,5 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index efc5d6492a..a99da66185 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -299,7 +299,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -326,7 +326,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/mips/src/common/up_allocateheap.c b/arch/mips/src/common/up_allocateheap.c index 1e99b86cee..7bcb04de73 100644 --- a/arch/mips/src/common/up_allocateheap.c +++ b/arch/mips/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c index 541633683b..5540b8bc4f 100644 --- a/arch/mips/src/common/up_createstack.c +++ b/arch/mips/src/common/up_createstack.c @@ -206,7 +206,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index 4ee09a2aca..1274772249 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -211,5 +211,5 @@ void up_initialize(void) /* Initialize USB -- device and/or host */ up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index 3ddb82a87d..a02750874e 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -111,7 +111,7 @@ static void _up_assert(int errorcode) for (; ; ) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index 6c55ed9cc9..debc56b642 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -74,7 +74,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index 74c2c5b170..d255b2b820 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -94,7 +94,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c index f9cf81d467..24b1321765 100644 --- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c +++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c @@ -97,7 +97,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Save the current value of current_regs (to support nested interrupt * handling). Then set current_regs to regs, indicating that this is diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c index aaf7b4805f..0ca9bdfa3e 100644 --- a/arch/mips/src/pic32mx/pic32mx-exception.c +++ b/arch/mips/src/pic32mx/pic32mx-exception.c @@ -94,7 +94,7 @@ uint32_t *pic32mx_exception(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_DEBUG /* Get the cause of the exception from the CAUSE register */ diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c index f2766ff331..bcf35488f8 100644 --- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c +++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c @@ -97,7 +97,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Save the current value of current_regs (to support nested interrupt * handling). Then set current_regs to regs, indicating that this is diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c index 81766676ac..3b6b3bb3f4 100644 --- a/arch/mips/src/pic32mz/pic32mz-exception.c +++ b/arch/mips/src/pic32mz/pic32mz-exception.c @@ -94,7 +94,7 @@ uint32_t *pic32mz_exception(uint32_t *regs) * processing an interrupt. */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_DEBUG /* Get the cause of the exception from the CAUSE register */ diff --git a/arch/sh/src/common/up_allocateheap.c b/arch/sh/src/common/up_allocateheap.c index b1a2c818b6..ddf287983a 100644 --- a/arch/sh/src/common/up_allocateheap.c +++ b/arch/sh/src/common/up_allocateheap.c @@ -81,7 +81,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 9568b33ae0..2a3b89eaeb 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -99,7 +99,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -151,7 +151,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/sh/src/common/up_createstack.c b/arch/sh/src/common/up_createstack.c index 825efb8cf3..f52f03386e 100644 --- a/arch/sh/src/common/up_createstack.c +++ b/arch/sh/src/common/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/sh/src/common/up_doirq.c b/arch/sh/src/common/up_doirq.c index 6c9854ba75..530a6e41af 100644 --- a/arch/sh/src/common/up_doirq.c +++ b/arch/sh/src/common/up_doirq.c @@ -73,7 +73,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/sh/src/common/up_initialize.c b/arch/sh/src/common/up_initialize.c index fb38f4a828..f4e067489f 100644 --- a/arch/sh/src/common/up_initialize.c +++ b/arch/sh/src/common/up_initialize.c @@ -200,5 +200,5 @@ void up_initialize(void) up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/sh/src/m16c/m16c_sigdeliver.c index 817d3bc02d..e27ef79452 100644 --- a/arch/sh/src/m16c/m16c_sigdeliver.c +++ b/arch/sh/src/m16c/m16c_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/sh/src/sh1/sh1_sigdeliver.c index c395d49c6a..7d53f29c65 100644 --- a/arch/sh/src/sh1/sh1_sigdeliver.c +++ b/arch/sh/src/sh1/sh1_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/x86/src/common/up_allocateheap.c b/arch/x86/src/common/up_allocateheap.c index 22b1ed5ba3..5fb0a9f288 100644 --- a/arch/x86/src/common/up_allocateheap.c +++ b/arch/x86/src/common/up_allocateheap.c @@ -82,7 +82,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index a3b82d3b7f..025f121f12 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -261,7 +261,7 @@ static void _up_assert(int errorcode) for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -288,7 +288,7 @@ void up_assert(const uint8_t *filename, int lineno) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_PRINT_TASKNAME lldbg("Assertion failed at file:%s line: %d task: %s\n", diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c index f720c2ae10..21d4eba7cb 100644 --- a/arch/x86/src/common/up_initialize.c +++ b/arch/x86/src/common/up_initialize.c @@ -211,5 +211,5 @@ void up_initialize(void) /* Initialize USB -- device and/or host */ up_usbinitialize(); - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/x86/src/i486/up_createstack.c b/arch/x86/src/i486/up_createstack.c index 8a7146f32a..1d9b1008d0 100644 --- a/arch/x86/src/i486/up_createstack.c +++ b/arch/x86/src/i486/up_createstack.c @@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 0996e7eb92..4824bbb473 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index fce1969faa..26a2de452a 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -88,7 +88,7 @@ static void idt_outb(uint8_t val, uint16_t addr) #ifndef CONFIG_SUPPRESS_INTERRUPTS static uint32_t *common_handler(int irq, uint32_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Current regs non-zero indicates that we are processing an interrupt; * current_regs is also used to manage interrupt level context switches. @@ -163,7 +163,7 @@ static uint32_t *common_handler(int irq, uint32_t *regs) uint32_t *isr_handler(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); PANIC(); /* Doesn't return */ return regs; /* To keep the compiler happy */ #else @@ -171,7 +171,7 @@ uint32_t *isr_handler(uint32_t *regs) /* Dispatch the interrupt */ - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); ret = common_handler((int)regs[REG_IRQNO], regs); board_led_off(LED_INIRQ); return ret; @@ -189,14 +189,14 @@ uint32_t *isr_handler(uint32_t *regs) uint32_t *irq_handler(uint32_t *regs) { #ifdef CONFIG_SUPPRESS_INTERRUPTS - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); PANIC(); /* Doesn't return */ return regs; /* To keep the compiler happy */ #else uint32_t *ret; int irq; - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); /* Get the IRQ number */ diff --git a/arch/z16/src/common/up_allocateheap.c b/arch/z16/src/common/up_allocateheap.c index 57a4ade72e..f307a8a73e 100644 --- a/arch/z16/src/common/up_allocateheap.c +++ b/arch/z16/src/common/up_allocateheap.c @@ -92,7 +92,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { *heap_start = (FAR void*)CONFIG_HEAP1_BASE; *heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE; - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); } /**************************************************************************** diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index 55d9853578..cf55172dca 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -98,7 +98,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -154,7 +154,7 @@ void up_assert(void) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 diff --git a/arch/z16/src/common/up_createstack.c b/arch/z16/src/common/up_createstack.c index e395bae436..c4d5537040 100644 --- a/arch/z16/src/common/up_createstack.c +++ b/arch/z16/src/common/up_createstack.c @@ -166,7 +166,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c index 9d9a38361d..38f89c49e0 100644 --- a/arch/z16/src/common/up_doirq.c +++ b/arch/z16/src/common/up_doirq.c @@ -82,7 +82,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) { FAR chipreg_t *ret = regs; - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS PANIC(); #else diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c index 8bbbc7c04b..364fd615e9 100644 --- a/arch/z16/src/common/up_idle.c +++ b/arch/z16/src/common/up_idle.c @@ -88,7 +88,7 @@ void up_idle(void) g_ledtoggle++; if (g_ledtoggle == 0x80) { - board_led_on(LED_IDLE); + board_autoled_on(LED_IDLE); } else if (g_ledtoggle == 0x00) { diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c index 79cf4617ed..747d448b0c 100644 --- a/arch/z16/src/common/up_initialize.c +++ b/arch/z16/src/common/up_initialize.c @@ -212,5 +212,5 @@ void up_initialize(void) (void)tun_initialize(); #endif - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c index d1113addc5..893a766121 100644 --- a/arch/z16/src/common/up_sigdeliver.c +++ b/arch/z16/src/common/up_sigdeliver.c @@ -94,7 +94,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/common/up_allocateheap.c b/arch/z80/src/common/up_allocateheap.c index 4cb3b02ff6..7ea677c5f9 100644 --- a/arch/z80/src/common/up_allocateheap.c +++ b/arch/z80/src/common/up_allocateheap.c @@ -101,7 +101,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { *heap_start = (FAR void*)CONFIG_HEAP1_BASE; *heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE; - board_led_on(LED_HEAPALLOCATE); + board_autoled_on(LED_HEAPALLOCATE); } /**************************************************************************** diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index be886dc44d..f6d92719a5 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -97,7 +97,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ for (;;) { #ifdef CONFIG_ARCH_LEDS - board_led_on(LED_PANIC); + board_autoled_on(LED_PANIC); up_mdelay(250); board_led_off(LED_PANIC); up_mdelay(250); @@ -153,7 +153,7 @@ void up_assert(void) struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; #endif - board_led_on(LED_ASSERTION); + board_autoled_on(LED_ASSERTION); #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 diff --git a/arch/z80/src/common/up_createstack.c b/arch/z80/src/common/up_createstack.c index e3880a0c61..60c4733d99 100644 --- a/arch/z80/src/common/up_createstack.c +++ b/arch/z80/src/common/up_createstack.c @@ -184,7 +184,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (uint32_t*)top_of_stack; tcb->adj_stack_size = size_of_stack; - board_led_on(LED_STACKCREATED); + board_autoled_on(LED_STACKCREATED); return OK; } diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c index f123782c2c..bd9d0adbc3 100644 --- a/arch/z80/src/common/up_doirq.c +++ b/arch/z80/src/common/up_doirq.c @@ -74,7 +74,7 @@ FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs) { - board_led_on(LED_INIRQ); + board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/z80/src/common/up_idle.c b/arch/z80/src/common/up_idle.c index 29ac104df0..bb6c028a79 100644 --- a/arch/z80/src/common/up_idle.c +++ b/arch/z80/src/common/up_idle.c @@ -88,7 +88,7 @@ void up_idle(void) g_ledtoggle++; if (g_ledtoggle == 0x80) { - board_led_on(LED_IDLE); + board_autoled_on(LED_IDLE); } else if (g_ledtoggle == 0x00) { diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index 12e5cff6d8..2bc7420c39 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -195,5 +195,5 @@ void up_initialize(void) (void)tun_initialize(); #endif - board_led_on(LED_IRQSENABLED); + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index 3b3f5ec860..a9a2e3f3c6 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -93,7 +93,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c index 484508e831..35b1647f21 100644 --- a/arch/z80/src/z180/z180_sigdeliver.c +++ b/arch/z80/src/z180/z180_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index fed589ef77..ea2a589d30 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -107,7 +107,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index 60058879b5..0e19072b5f 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -92,7 +92,7 @@ void up_sigdeliver(void) int saved_errno = rtcb->pterrno; - board_led_on(LED_SIGNAL); + board_autoled_on(LED_SIGNAL); sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); From 79df5616694665f8a9944a3537e6888ffe1e0e02 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 1 Nov 2015 09:09:36 -0600 Subject: [PATCH 21/41] Rename board_led_off to board_autoled_off --- arch/arm/src/arm/up_assert.c | 2 +- arch/arm/src/arm/up_doirq.c | 2 +- arch/arm/src/arm/up_sigdeliver.c | 2 +- arch/arm/src/armv6-m/up_assert.c | 2 +- arch/arm/src/armv6-m/up_doirq.c | 2 +- arch/arm/src/armv6-m/up_sigdeliver.c | 2 +- arch/arm/src/armv7-a/arm_assert.c | 2 +- arch/arm/src/armv7-a/arm_doirq.c | 2 +- arch/arm/src/armv7-a/arm_sigdeliver.c | 2 +- arch/arm/src/armv7-m/up_assert.c | 2 +- arch/arm/src/armv7-m/up_doirq.c | 2 +- arch/arm/src/armv7-m/up_sigdeliver.c | 2 +- arch/arm/src/efm32/efm32_idle.c | 2 +- arch/arm/src/kinetis/kinetis_idle.c | 2 +- arch/arm/src/kl/kl_idle.c | 2 +- arch/arm/src/lpc11xx/lpc11_idle.c | 2 +- arch/arm/src/lpc17xx/lpc17_idle.c | 2 +- arch/arm/src/lpc43xx/lpc43_idle.c | 2 +- arch/arm/src/nuc1xx/nuc_idle.c | 2 +- arch/arm/src/samdl/sam_idle.c | 2 +- arch/arm/src/stm32/stm32_idle.c | 2 +- arch/arm/src/str71x/str71x_decodeirq.c | 2 +- arch/avr/src/avr/up_doirq.c | 2 +- arch/avr/src/avr/up_sigdeliver.c | 2 +- arch/avr/src/avr32/up_doirq.c | 2 +- arch/avr/src/avr32/up_sigdeliver.c | 2 +- arch/avr/src/common/up_assert.c | 2 +- arch/hc/src/common/up_doirq.c | 2 +- arch/hc/src/m9s12/m9s12_assert.c | 2 +- arch/mips/src/mips32/up_assert.c | 2 +- arch/mips/src/mips32/up_doirq.c | 2 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/pic32mx/pic32mx-decodeirq.c | 4 ++-- arch/mips/src/pic32mz/pic32mz-decodeirq.c | 4 ++-- arch/sh/src/common/up_assert.c | 2 +- arch/sh/src/common/up_doirq.c | 2 +- arch/sh/src/m16c/m16c_sigdeliver.c | 2 +- arch/sh/src/sh1/sh1_sigdeliver.c | 2 +- arch/x86/src/common/up_assert.c | 2 +- arch/x86/src/i486/up_sigdeliver.c | 2 +- arch/x86/src/qemu/qemu_handlers.c | 4 ++-- arch/z16/src/common/up_assert.c | 2 +- arch/z16/src/common/up_doirq.c | 2 +- arch/z16/src/common/up_idle.c | 2 +- arch/z16/src/common/up_sigdeliver.c | 2 +- arch/z80/src/common/up_assert.c | 2 +- arch/z80/src/common/up_doirq.c | 2 +- arch/z80/src/common/up_idle.c | 2 +- arch/z80/src/ez80/ez80_sigdeliver.c | 2 +- arch/z80/src/z180/z180_sigdeliver.c | 2 +- arch/z80/src/z8/z8_sigdeliver.c | 2 +- arch/z80/src/z80/z80_sigdeliver.c | 2 +- 52 files changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index c9ed3cff3b..28b7776f97 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -318,7 +318,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c index 7df75a436d..52603f435d 100644 --- a/arch/arm/src/arm/up_doirq.c +++ b/arch/arm/src/arm/up_doirq.c @@ -130,5 +130,5 @@ void up_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index 38127a706a..eab3193bf0 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index 9f196926a3..0e05acdd4a 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -373,7 +373,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv6-m/up_doirq.c b/arch/arm/src/armv6-m/up_doirq.c index 4be88b4c08..3edc9d3b82 100644 --- a/arch/arm/src/armv6-m/up_doirq.c +++ b/arch/arm/src/armv6-m/up_doirq.c @@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c index 153c9bd4d0..b563062502 100644 --- a/arch/arm/src/armv6-m/up_sigdeliver.c +++ b/arch/arm/src/armv6-m/up_sigdeliver.c @@ -143,7 +143,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 166de067ac..a814a80bb0 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -373,7 +373,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index f62fc7f60c..79a5ed5f55 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -128,6 +128,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 1cfa888421..1f52b5ec91 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index 74ac5e30e5..b18bc1e265 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -382,7 +382,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 27740d2704..71c1fc7d11 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index 085380fb5a..8d24cf9e46 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -146,7 +146,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c index 75c9905c1b..9e0c218e0e 100644 --- a/arch/arm/src/efm32/efm32_idle.c +++ b/arch/arm/src/efm32/efm32_idle.c @@ -62,7 +62,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/kinetis/kinetis_idle.c b/arch/arm/src/kinetis/kinetis_idle.c index b47e56a668..71ee037c14 100644 --- a/arch/arm/src/kinetis/kinetis_idle.c +++ b/arch/arm/src/kinetis/kinetis_idle.c @@ -55,7 +55,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index 8e34a7a1a4..ce7ec7ff35 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c index e45cf3068b..802105dbc1 100644 --- a/arch/arm/src/lpc11xx/lpc11_idle.c +++ b/arch/arm/src/lpc11xx/lpc11_idle.c @@ -54,7 +54,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc17xx/lpc17_idle.c b/arch/arm/src/lpc17xx/lpc17_idle.c index db90892e44..71d940a6ab 100644 --- a/arch/arm/src/lpc17xx/lpc17_idle.c +++ b/arch/arm/src/lpc17xx/lpc17_idle.c @@ -56,7 +56,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index 476c36c91f..8b15bb079a 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -58,7 +58,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index d656767e7e..5414c70e74 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c index 743b26a4f7..b661733d74 100644 --- a/arch/arm/src/samdl/sam_idle.c +++ b/arch/arm/src/samdl/sam_idle.c @@ -59,7 +59,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c index 2934cc3e4c..ce95c861ee 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/stm32/stm32_idle.c @@ -61,7 +61,7 @@ #if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) # define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_led_off(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) #else # define BEGIN_IDLE() # define END_IDLE() diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c index 72e4da677c..9e28a1b4ae 100644 --- a/arch/arm/src/str71x/str71x_decodeirq.c +++ b/arch/arm/src/str71x/str71x_decodeirq.c @@ -138,6 +138,6 @@ void up_decodeirq(uint32_t *regs) PANIC(); /* Normally never happens */ } #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif } diff --git a/arch/avr/src/avr/up_doirq.c b/arch/avr/src/avr/up_doirq.c index b692420a4d..88cbcce870 100644 --- a/arch/avr/src/avr/up_doirq.c +++ b/arch/avr/src/avr/up_doirq.c @@ -112,7 +112,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs) current_regs = savestate; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index 92604bcf14..0db6a03344 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -147,7 +147,7 @@ void up_sigdeliver(void) * to the size of register save structure size will protect its contents. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/avr/src/avr32/up_doirq.c b/arch/avr/src/avr32/up_doirq.c index 6acf3c9f09..14b4d6a7ae 100644 --- a/arch/avr/src/avr32/up_doirq.c +++ b/arch/avr/src/avr32/up_doirq.c @@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index e4be7e7d16..6038771485 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -150,7 +150,7 @@ void up_sigdeliver(void) * to the size of register save structure size will protect its contents. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index cddb4a7c86..04c2809052 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -113,7 +113,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index a0cb7998aa..99e7ba6a64 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -133,6 +133,6 @@ uint8_t *up_doirq(int irq, uint8_t *regs) current_regs = NULL; #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index a99da66185..7f48615c9a 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -301,7 +301,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index a02750874e..c392bf5386 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -113,7 +113,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index debc56b642..5cb7fbdbb3 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -143,6 +143,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs) up_enable_irq(irq); #endif - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; } diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index d255b2b820..060298010c 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -136,7 +136,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); /* up_fullcontextrestore() should not return but could if the software diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c index 24b1321765..13144eb67e 100644 --- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c +++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c @@ -189,11 +189,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs) current_regs = savestate; if (current_regs == NULL) { - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } #else current_regs = NULL; - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c index bcf35488f8..632af96b46 100644 --- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c +++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c @@ -189,11 +189,11 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs) current_regs = savestate; if (current_regs == NULL) { - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); } #else current_regs = NULL; - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 2a3b89eaeb..3499e9404d 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -101,7 +101,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/sh/src/common/up_doirq.c b/arch/sh/src/common/up_doirq.c index 530a6e41af..dd0edc42db 100644 --- a/arch/sh/src/common/up_doirq.c +++ b/arch/sh/src/common/up_doirq.c @@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs) current_regs = NULL; } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return regs; } diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/sh/src/m16c/m16c_sigdeliver.c index e27ef79452..220e8e2c28 100644 --- a/arch/sh/src/m16c/m16c_sigdeliver.c +++ b/arch/sh/src/m16c/m16c_sigdeliver.c @@ -136,7 +136,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); #endif } diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/sh/src/sh1/sh1_sigdeliver.c index 7d53f29c65..69f5446df5 100644 --- a/arch/sh/src/sh1/sh1_sigdeliver.c +++ b/arch/sh/src/sh1/sh1_sigdeliver.c @@ -133,7 +133,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); #endif } diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index 025f121f12..0e4761c2bc 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -263,7 +263,7 @@ static void _up_assert(int errorcode) #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 4824bbb473..ddc87e08d8 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); up_fullcontextrestore(regs); } diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index 26a2de452a..0a22d7346f 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -173,7 +173,7 @@ uint32_t *isr_handler(uint32_t *regs) board_autoled_on(LED_INIRQ); ret = common_handler((int)regs[REG_IRQNO], regs); - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return ret; #endif } @@ -220,7 +220,7 @@ uint32_t *irq_handler(uint32_t *regs) /* Dispatch the interrupt */ ret = common_handler(irq, regs); - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return ret; #endif } diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index cf55172dca..45537de599 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -100,7 +100,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c index 38f89c49e0..98983538bf 100644 --- a/arch/z16/src/common/up_doirq.c +++ b/arch/z16/src/common/up_doirq.c @@ -124,7 +124,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) current_regs = savestate; } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); #endif return ret; diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c index 364fd615e9..01aa0f8d6d 100644 --- a/arch/z16/src/common/up_idle.c +++ b/arch/z16/src/common/up_idle.c @@ -92,7 +92,7 @@ void up_idle(void) } else if (g_ledtoggle == 0x00) { - board_led_off(LED_IDLE); + board_autoled_off(LED_IDLE); } #endif diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c index 893a766121..0fc5226273 100644 --- a/arch/z16/src/common/up_sigdeliver.c +++ b/arch/z16/src/common/up_sigdeliver.c @@ -137,7 +137,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); SIGNAL_RETURN(regs); #endif } diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index f6d92719a5..a848172b24 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -99,7 +99,7 @@ static void _up_assert(int errorcode) /* noreturn_function */ #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); - board_led_off(LED_PANIC); + board_autoled_off(LED_PANIC); up_mdelay(250); #endif } diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c index bd9d0adbc3..30e2caf9fd 100644 --- a/arch/z80/src/common/up_doirq.c +++ b/arch/z80/src/common/up_doirq.c @@ -129,7 +129,7 @@ FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs) IRQ_LEAVE(irq); } - board_led_off(LED_INIRQ); + board_autoled_off(LED_INIRQ); return regs; #endif } diff --git a/arch/z80/src/common/up_idle.c b/arch/z80/src/common/up_idle.c index bb6c028a79..43deca5aa0 100644 --- a/arch/z80/src/common/up_idle.c +++ b/arch/z80/src/common/up_idle.c @@ -92,7 +92,7 @@ void up_idle(void) } else if (g_ledtoggle == 0x00) { - board_led_off(LED_IDLE); + board_autoled_off(LED_IDLE); } #endif diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index a9a2e3f3c6..12db8846aa 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -135,7 +135,7 @@ void up_sigdeliver(void) * execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); ez80_restorecontext(regs); #endif } diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c index 35b1647f21..58e9aa9c94 100644 --- a/arch/z80/src/z180/z180_sigdeliver.c +++ b/arch/z80/src/z180/z180_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z180_restoreusercontext(regs); #endif } diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index ea2a589d30..6605bba7d5 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -147,7 +147,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z8_restorecontext(regs); #endif } diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index 0e19072b5f..4e6dafc0bd 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -132,7 +132,7 @@ void up_sigdeliver(void) /* Then restore the correct state for this thread of execution. */ - board_led_off(LED_SIGNAL); + board_autoled_off(LED_SIGNAL); z80_restoreusercontext(regs); #endif } From 4c2c9898382e93a52cfd0f039e20797a07aeeab0 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Sun, 1 Nov 2015 17:09:11 -0500 Subject: [PATCH 22/41] STM32 PWM: Add support for multiple output channels --- arch/arm/src/stm32/Kconfig | 1610 ++++++++++++++++++++++++++- arch/arm/src/stm32/chip/stm32_tim.h | 12 +- arch/arm/src/stm32/stm32_pwm.c | 1182 ++++++++++++++++---- arch/arm/src/stm32/stm32_pwm.h | 839 +++++++++++++- 4 files changed, 3349 insertions(+), 294 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 48e01e0efa..cfe4eb5d09 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2486,15 +2486,137 @@ config STM32_TIM1_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM1_PWM + +config STM32_TIM1_MODE + int "TIM1 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM1_CHANNEL1 + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM1_CHANNEL1 + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM1_CHANNEL2 + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM1_CHANNEL2 + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM1_CHANNEL3 + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM1_CHANNEL3 + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM1_CHANNEL4 + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM1_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM1_CHANNEL int "TIM1 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM1_PWM ---help--- If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM1_PWM + config STM32_TIM2_PWM bool "TIM2 PWM" default n @@ -2508,15 +2630,137 @@ config STM32_TIM2_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM2_PWM + +config STM32_TIM2_MODE + int "TIM2 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM2_CHANNEL1 + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM2_CHANNEL1 + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM2_CHANNEL2 + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM2_CHANNEL2 + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM2_CHANNEL3 + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM2_CHANNEL3 + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM2_CHANNEL4 + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM2_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM2_CHANNEL int "TIM2 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM2_PWM ---help--- If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM2_PWM + config STM32_TIM3_PWM bool "TIM3 PWM" default n @@ -2530,15 +2774,137 @@ config STM32_TIM3_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM3_PWM + +config STM32_TIM3_MODE + int "TIM3 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM3_CHANNEL1 + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM3_CHANNEL1 + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM3_CHANNEL2 + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM3_CHANNEL2 + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM3_CHANNEL3 + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM3_CHANNEL3 + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM3_CHANNEL4 + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM3_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM3_CHANNEL int "TIM3 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM3_PWM ---help--- If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM3_PWM + config STM32_TIM4_PWM bool "TIM4 PWM" default n @@ -2552,15 +2918,137 @@ config STM32_TIM4_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM4_PWM + +config STM32_TIM4_MODE + int "TIM4 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM4_CHANNEL1 + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM4_CHANNEL1 + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM4_CHANNEL2 + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM4_CHANNEL2 + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM4_CHANNEL3 + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM4_CHANNEL3 + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM4_CHANNEL4 + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM4_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM4_CHANNEL int "TIM4 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM4_PWM ---help--- If TIM4 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM4_PWM + config STM32_TIM5_PWM bool "TIM5 PWM" default n @@ -2574,15 +3062,137 @@ config STM32_TIM5_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM5_PWM + +config STM32_TIM5_MODE + int "TIM5 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM5_CHANNEL1 + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM5_CHANNEL1 + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM5_CHANNEL2 + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM5_CHANNEL2 + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM5_CHANNEL3 + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM5_CHANNEL3 + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM5_CHANNEL4 + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM5_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM5_CHANNEL int "TIM5 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM5_PWM ---help--- If TIM5 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM5_PWM + config STM32_TIM8_PWM bool "TIM8 PWM" default n @@ -2596,15 +3206,137 @@ config STM32_TIM8_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM8_PWM + +config STM32_TIM8_MODE + int "TIM8 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32_PWM_MULTICHAN + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM8_CHANNEL1 + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM8_CHANNEL1 + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM8_CHANNEL2 + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM8_CHANNEL2 + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM8_CHANNEL3 + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM8_CHANNEL3 + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM8_CHANNEL4 + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM8_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM8_CHANNEL int "TIM8 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM8_PWM ---help--- If TIM8 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM8_PWM + config STM32_TIM9_PWM bool "TIM9 PWM" default n @@ -2618,15 +3350,130 @@ config STM32_TIM9_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM9_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM9_CHANNEL1 + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM9_CHANNEL1 + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM9_CHANNEL2 + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM9_CHANNEL2 + +config STM32_TIM9_CHANNEL3 + bool "TIM9 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM9_CHANNEL3 + +config STM32_TIM9_CH3MODE + int "TIM9 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH3OUT + bool "TIM9 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM9_CHANNEL3 + +config STM32_TIM9_CHANNEL4 + bool "TIM9 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM9_CHANNEL4 + +config STM32_TIM9_CH4MODE + int "TIM9 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM9_CH4OUT + bool "TIM9 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM9_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM9_CHANNEL int "TIM9 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM9_PWM ---help--- If TIM9 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM9_PWM + config STM32_TIM10_PWM bool "TIM10 PWM" default n @@ -2640,15 +3487,130 @@ config STM32_TIM10_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM10_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM10_CHANNEL1 + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM10_CHANNEL1 + +config STM32_TIM10_CHANNEL2 + bool "TIM10 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM10_CHANNEL2 + +config STM32_TIM10_CH2MODE + int "TIM10 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH2OUT + bool "TIM10 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM10_CHANNEL2 + +config STM32_TIM10_CHANNEL3 + bool "TIM10 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM10_CHANNEL3 + +config STM32_TIM10_CH3MODE + int "TIM10 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH3OUT + bool "TIM10 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM10_CHANNEL3 + +config STM32_TIM10_CHANNEL4 + bool "TIM10 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM10_CHANNEL4 + +config STM32_TIM10_CH4MODE + int "TIM10 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM10_CH4OUT + bool "TIM10 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM10_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM10_CHANNEL int "TIM10 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM10_PWM ---help--- If TIM10 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM10_PWM + config STM32_TIM11_PWM bool "TIM11 PWM" default n @@ -2662,15 +3624,130 @@ config STM32_TIM11_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM11_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM11_CHANNEL1 + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM11_CHANNEL1 + +config STM32_TIM11_CHANNEL2 + bool "TIM11 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM11_CHANNEL2 + +config STM32_TIM11_CH2MODE + int "TIM11 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH2OUT + bool "TIM11 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM11_CHANNEL2 + +config STM32_TIM11_CHANNEL3 + bool "TIM11 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM11_CHANNEL3 + +config STM32_TIM11_CH3MODE + int "TIM11 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH3OUT + bool "TIM11 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM11_CHANNEL3 + +config STM32_TIM11_CHANNEL4 + bool "TIM11 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM11_CHANNEL4 + +config STM32_TIM11_CH4MODE + int "TIM11 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM11_CH4OUT + bool "TIM11 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM11_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM11_CHANNEL int "TIM11 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM11_PWM ---help--- If TIM11 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM11_PWM + config STM32_TIM12_PWM bool "TIM12 PWM" default n @@ -2684,15 +3761,130 @@ config STM32_TIM12_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM12_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM12_CHANNEL1 + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM12_CHANNEL1 + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM12_CHANNEL2 + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM12_CHANNEL2 + +config STM32_TIM12_CHANNEL3 + bool "TIM12 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM12_CHANNEL3 + +config STM32_TIM12_CH3MODE + int "TIM12 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH3OUT + bool "TIM12 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM12_CHANNEL3 + +config STM32_TIM12_CHANNEL4 + bool "TIM12 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM12_CHANNEL4 + +config STM32_TIM12_CH4MODE + int "TIM12 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM12_CH4OUT + bool "TIM12 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM12_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM12_CHANNEL int "TIM12 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM12_PWM ---help--- If TIM12 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM12_PWM + config STM32_TIM13_PWM bool "TIM13 PWM" default n @@ -2706,15 +3898,130 @@ config STM32_TIM13_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM13_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM13_CHANNEL1 + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM13_CHANNEL1 + +config STM32_TIM13_CHANNEL2 + bool "TIM13 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM13_CHANNEL2 + +config STM32_TIM13_CH2MODE + int "TIM13 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH2OUT + bool "TIM13 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM13_CHANNEL2 + +config STM32_TIM13_CHANNEL3 + bool "TIM13 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM13_CHANNEL3 + +config STM32_TIM13_CH3MODE + int "TIM13 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH3OUT + bool "TIM13 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM13_CHANNEL3 + +config STM32_TIM13_CHANNEL4 + bool "TIM13 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM13_CHANNEL4 + +config STM32_TIM13_CH4MODE + int "TIM13 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM13_CH4OUT + bool "TIM13 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM13_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM13_CHANNEL int "TIM13 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM13_PWM ---help--- If TIM13 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM13_PWM + config STM32_TIM14_PWM bool "TIM14 PWM" default n @@ -2728,15 +4035,130 @@ config STM32_TIM14_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM14_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM14_CHANNEL1 + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM14_CHANNEL1 + +config STM32_TIM14_CHANNEL2 + bool "TIM14 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM14_CHANNEL2 + +config STM32_TIM14_CH2MODE + int "TIM14 Channel 2 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH2OUT + bool "TIM14 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM14_CHANNEL2 + +config STM32_TIM14_CHANNEL3 + bool "TIM14 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32_TIM14_CHANNEL3 + +config STM32_TIM14_CH3MODE + int "TIM14 Channel 3 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH3OUT + bool "TIM14 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32_TIM14_CHANNEL3 + +config STM32_TIM14_CHANNEL4 + bool "TIM14 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32_TIM14_CHANNEL4 + +config STM32_TIM14_CH4MODE + int "TIM14 Channel 4 Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM14_CH4OUT + bool "TIM14 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32_TIM14_CHANNEL4 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM14_CHANNEL int "TIM14 PWM Output Channel" default 1 range 1 4 - depends on STM32_TIM14_PWM ---help--- If TIM14 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + default 0 + range 0 5 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM14_PWM + config STM32_TIM15_PWM bool "TIM15 PWM" default n @@ -2749,15 +4171,82 @@ config STM32_TIM15_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM15_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM15_CHANNEL1 + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM15_CHANNEL1 + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32_TIM15_CHANNEL2 + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32_TIM15_CHANNEL2 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM15_CHANNEL int "TIM15 PWM Output Channel" default 1 range 1 2 - depends on STM32_TIM15_PWM ---help--- If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + default 0 + range 0 3 if STM32_STM32F30XX + range 0 1 if !STM32_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM15_PWM + config STM32_TIM16_PWM bool "TIM16 PWM" default n @@ -2770,15 +4259,56 @@ config STM32_TIM16_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM16_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM16_CHANNEL1 + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM16_CHANNEL1 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 - depends on STM32_TIM16_PWM ---help--- If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM16_PWM + config STM32_TIM17_PWM bool "TIM17 PWM" default n @@ -2791,15 +4321,65 @@ config STM32_TIM17_PWM is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. +if STM32_TIM17_PWM + +if STM32_PWM_MULTICHAN + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32_TIM17_CHANNEL1 + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32_TIM17_CHANNEL1 + +endif # STM32_PWM_MULTICHAN + +if !STM32_PWM_MULTICHAN + config STM32_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 - depends on STM32_TIM17_PWM ---help--- If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32_PWM_MULTICHAN + +endif # STM32_TIM17_PWM + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + default n + depends on STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM || STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM || STM32_TIM9_PWM || STM32_TIM10_PWM || STM32_TIM11_PWM || STM32_TIM12_PWM || STM32_TIM13_PWM || STM32_TIM14_PWM || STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + select ARCH_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + config STM32_TIM1_ADC bool "TIM1 ADC" default n diff --git a/arch/arm/src/stm32/chip/stm32_tim.h b/arch/arm/src/stm32/chip/stm32_tim.h index 80e86c0026..573dd9dd84 100644 --- a/arch/arm/src/stm32/chip/stm32_tim.h +++ b/arch/arm/src/stm32/chip/stm32_tim.h @@ -677,8 +677,8 @@ #define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ #ifdef CONFIG_STM32_STM32F30XX -# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ +# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ #endif /* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ @@ -698,6 +698,10 @@ #define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ #define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ #define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ /* Capture/compare mode register 1 -- Input capture mode */ @@ -764,8 +768,8 @@ #define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ #ifdef CONFIG_STM32_STM32F30XX -# define ATIM_CCMR1_OC3M 1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -# define ATIM_CCMR1_OC4M 1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ +# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ #endif /* Capture/compare mode register 2 - Input Capture Mode */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index a3a1645688..d8b98e0ee2 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_pwm.c * * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -65,7 +67,9 @@ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \ defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \ - defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) + defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) /**************************************************************************** * Pre-processor Definitions @@ -75,7 +79,7 @@ #define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */ #define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */ -#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4, TIM15-17 on F3 */ #define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */ #define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */ @@ -105,6 +109,9 @@ #define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16 /* Debug ********************************************************************/ /* Non-standard debug that may be enabled just for testing PWM */ @@ -136,14 +143,42 @@ /**************************************************************************** * Private Types ****************************************************************************/ + +enum stm32_timmode_e +{ + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, +}; + +enum stm32_chanmode_e +{ + STM32_CHANMODE_PWM1 = 0, + STM32_CHANMODE_PWM2 = 1, + STM32_CHANMODE_COMBINED1 = 2, + STM32_CHANMODE_COMBINED2 = 3, + STM32_CHANMODE_ASYMMETRIC1 = 4, + STM32_CHANMODE_ASYMMETRIC2 = 5, +}; + +struct stm32_pwmchan_s +{ + uint8_t channel; /* Timer output channel: {1,..4} */ + uint32_t pincfg; /* Output pin configuration */ + enum stm32_chanmode_e mode; +}; + /* This structure represents the state of one PWM timer */ struct stm32_pwmtimer_s { FAR const struct pwm_ops_s *ops; /* PWM operations */ - uint8_t timid; /* Timer ID {1,...,14} */ - uint8_t channel; /* Timer output channel: {1,..4} */ + uint8_t timid; /* Timer ID {1,...,17} */ + struct stm32_pwmchan_s channels[PWM_NCHANNELS]; uint8_t timtype; /* See the TIMTYPE_* definitions */ + enum stm32_timmode_e mode; #ifdef CONFIG_PWM_PULSECOUNT uint8_t irq; /* Timer update IRQ */ uint8_t prev; /* The previous value of the RCR (pre-loaded) */ @@ -151,11 +186,10 @@ struct stm32_pwmtimer_s uint32_t count; /* Remaining pluse count */ #endif uint32_t base; /* The base address of the timer */ - uint32_t pincfg; /* Output pin configuration */ uint32_t pclk; /* The frequency of the peripheral clock * that drives the timer module. */ #ifdef CONFIG_PWM_PULSECOUNT - FAR void * handle; /* Handle used for upper-half callback */ + FAR void *handle; /* Handle used for upper-half callback */ #endif }; @@ -214,185 +248,515 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, static const struct pwm_ops_s g_pwmops = { - .setup = pwm_setup, - .shutdown = pwm_shutdown, - .start = pwm_start, - .stop = pwm_stop, - .ioctl = pwm_ioctl, + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, }; #ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmtimer_s g_pwm1dev = { - .ops = &g_pwmops, - .timid = 1, - .channel = CONFIG_STM32_TIM1_CHANNEL, - .timtype = TIMTYPE_TIM1, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM1UP, + .ops = &g_pwmops, + .timid = 1, + .channels = + { +#ifdef CONFIG_STM32_TIM1_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM1_CH1CFG, + .mode = CONFIG_STM32_TIM1_CH1MODE, + }, #endif - .base = STM32_TIM1_BASE, - .pincfg = PWM_TIM1_PINCFG, - .pclk = STM32_APB2_TIM1_CLKIN, +#ifdef CONFIG_STM32_TIM1_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM1_CH2CFG, + .mode = CONFIG_STM32_TIM1_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM1_CH3CFG, + .mode = CONFIG_STM32_TIM1_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM1_CH4CFG, + .mode = CONFIG_STM32_TIM1_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM1, + .mode = CONFIG_STM32_TIM1_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM1UP, +#endif + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmtimer_s g_pwm2dev = { - .ops = &g_pwmops, - .timid = 2, - .channel = CONFIG_STM32_TIM2_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM2, + .ops = &g_pwmops, + .timid = 2, + .channels = + { +#ifdef CONFIG_STM32_TIM2_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM2_CH1CFG, + .mode = CONFIG_STM32_TIM2_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM2, - .base = STM32_TIM2_BASE, - .pincfg = PWM_TIM2_PINCFG, - .pclk = STM32_APB1_TIM2_CLKIN, +#ifdef CONFIG_STM32_TIM2_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM2_CH2CFG, + .mode = CONFIG_STM32_TIM2_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM2_CH3CFG, + .mode = CONFIG_STM32_TIM2_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM2_CH4CFG, + .mode = CONFIG_STM32_TIM2_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM2, + .mode = CONFIG_STM32_TIM2_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM2, +#endif + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmtimer_s g_pwm3dev = { - .ops = &g_pwmops, - .timid = 3, - .channel = CONFIG_STM32_TIM3_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM3, + .ops = &g_pwmops, + .timid = 3, + .channels = + { +#ifdef CONFIG_STM32_TIM3_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM3_CH1CFG, + .mode = CONFIG_STM32_TIM3_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM3, - .base = STM32_TIM3_BASE, - .pincfg = PWM_TIM3_PINCFG, - .pclk = STM32_APB1_TIM3_CLKIN, +#ifdef CONFIG_STM32_TIM3_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM3_CH2CFG, + .mode = CONFIG_STM32_TIM3_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM3_CH3CFG, + .mode = CONFIG_STM32_TIM3_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM3_CH4CFG, + .mode = CONFIG_STM32_TIM3_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM3, + .mode = CONFIG_STM32_TIM3_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM3, +#endif + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmtimer_s g_pwm4dev = { - .ops = &g_pwmops, - .timid = 4, - .channel = CONFIG_STM32_TIM4_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM4, + .ops = &g_pwmops, + .timid = 4, + .channels = + { +#ifdef CONFIG_STM32_TIM4_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM4_CH1CFG, + .mode = CONFIG_STM32_TIM4_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM4, - .base = STM32_TIM4_BASE, - .pincfg = PWM_TIM4_PINCFG, - .pclk = STM32_APB1_TIM4_CLKIN, +#ifdef CONFIG_STM32_TIM4_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM4_CH2CFG, + .mode = CONFIG_STM32_TIM4_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM4_CH3CFG, + .mode = CONFIG_STM32_TIM4_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM4_CH4CFG, + .mode = CONFIG_STM32_TIM4_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM4, + .mode = CONFIG_STM32_TIM4_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM4, +#endif + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmtimer_s g_pwm5dev = { - .ops = &g_pwmops, - .timid = 5, - .channel = CONFIG_STM32_TIM5_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM5, + .ops = &g_pwmops, + .timid = 5, + .channels = + { +#ifdef CONFIG_STM32_TIM5_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM5_CH1CFG, + .mode = CONFIG_STM32_TIM5_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM5, - .base = STM32_TIM5_BASE, - .pincfg = PWM_TIM5_PINCFG, - .pclk = STM32_APB1_TIM5_CLKIN, +#ifdef CONFIG_STM32_TIM5_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM5_CH2CFG, + .mode = CONFIG_STM32_TIM5_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM5_CH3CFG, + .mode = CONFIG_STM32_TIM5_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM5_CH4CFG, + .mode = CONFIG_STM32_TIM5_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM5, + .mode = CONFIG_STM32_TIM5_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM5, +#endif + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmtimer_s g_pwm8dev = { - .ops = &g_pwmops, - .timid = 8, - .channel = CONFIG_STM32_TIM8_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM8UP, + .ops = &g_pwmops, + .timid = 8, + .channels = + { +#ifdef CONFIG_STM32_TIM8_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM8_CH1CFG, + .mode = CONFIG_STM32_TIM8_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM8, - .base = STM32_TIM8_BASE, - .pincfg = PWM_TIM8_PINCFG, - .pclk = STM32_APB2_TIM8_CLKIN, +#ifdef CONFIG_STM32_TIM8_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM8_CH2CFG, + .mode = CONFIG_STM32_TIM8_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM8_CH3CFG, + .mode = CONFIG_STM32_TIM8_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM8_CH4CFG, + .mode = CONFIG_STM32_TIM8_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM8, + .mode = CONFIG_STM32_TIM8_MODE, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM8UP, +#endif + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmtimer_s g_pwm9dev = { - .ops = &g_pwmops, - .timid = 9, - .channel = CONFIG_STM32_TIM9_CHANNEL, - .timtype = TIMTYPE_TIM9, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM9, + .ops = &g_pwmops, + .timid = 9, + .channels = + { +#ifdef CONFIG_STM32_TIM9_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM9_CH1CFG, + .mode = CONFIG_STM32_TIM9_CH1MODE, + }, #endif - .base = STM32_TIM9_BASE, - .pincfg = PWM_TIM9_PINCFG, - .pclk = STM32_APB2_TIM9_CLKIN, +#ifdef CONFIG_STM32_TIM9_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM9_CH2CFG, + .mode = CONFIG_STM32_TIM9_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM9_CH3CFG, + .mode = CONFIG_STM32_TIM9_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM9_CH4CFG, + .mode = CONFIG_STM32_TIM9_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM9, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM9, +#endif + .base = STM32_TIM9_BASE, + .pclk = STM32_APB2_TIM9_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmtimer_s g_pwm10dev = { - .ops = &g_pwmops, - .timid = 10, - .channel = CONFIG_STM32_TIM10_CHANNEL, - .timtype = TIMTYPE_TIM10, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM10, + .ops = &g_pwmops, + .timid = 10, + .channels = + { +#ifdef CONFIG_STM32_TIM10_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM10_CH1CFG, + .mode = CONFIG_STM32_TIM10_CH1MODE, + }, #endif - .base = STM32_TIM10_BASE, - .pincfg = PWM_TIM10_PINCFG, - .pclk = STM32_APB2_TIM10_CLKIN, +#ifdef CONFIG_STM32_TIM10_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM10_CH2CFG, + .mode = CONFIG_STM32_TIM10_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM10_CH3CFG, + .mode = CONFIG_STM32_TIM10_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM10_CH4CFG, + .mode = CONFIG_STM32_TIM10_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM10, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM10, +#endif + .base = STM32_TIM10_BASE, + .pclk = STM32_APB2_TIM10_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmtimer_s g_pwm11dev = { - .ops = &g_pwmops, - .timid = 11, - .channel = CONFIG_STM32_TIM11_CHANNEL, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM11, + .ops = &g_pwmops, + .timid = 11, + .channels = + { +#ifdef CONFIG_STM32_TIM11_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM11_CH1CFG, + .mode = CONFIG_STM32_TIM11_CH1MODE, + }, #endif - .timtype = TIMTYPE_TIM11, - .base = STM32_TIM11_BASE, - .pincfg = PWM_TIM11_PINCFG, - .pclk = STM32_APB2_TIM11_CLKIN, +#ifdef CONFIG_STM32_TIM11_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM11_CH2CFG, + .mode = CONFIG_STM32_TIM11_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM11_CH3CFG, + .mode = CONFIG_STM32_TIM11_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM11_CH4CFG, + .mode = CONFIG_STM32_TIM11_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM11, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM11, +#endif + .base = STM32_TIM11_BASE, + .pclk = STM32_APB2_TIM11_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmtimer_s g_pwm12dev = { - .ops = &g_pwmops, - .timid = 12, - .channel = CONFIG_STM32_TIM12_CHANNEL, - .timtype = TIMTYPE_TIM12, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM12, + .ops = &g_pwmops, + .timid = 12, + .channels = + { +#ifdef CONFIG_STM32_TIM12_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM12_CH1CFG, + .mode = CONFIG_STM32_TIM12_CH1MODE, + }, #endif - .base = STM32_TIM12_BASE, - .pincfg = PWM_TIM12_PINCFG, - .pclk = STM32_APB1_TIM12_CLKIN, +#ifdef CONFIG_STM32_TIM12_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM12_CH2CFG, + .mode = CONFIG_STM32_TIM12_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM12_CH3CFG, + .mode = CONFIG_STM32_TIM12_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM12_CH4CFG, + .mode = CONFIG_STM32_TIM12_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM12, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM12, +#endif + .base = STM32_TIM12_BASE, + .pclk = STM32_APB1_TIM12_CLKIN, }; #endif #ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmtimer_s g_pwm13dev = { - .ops = &g_pwmops, - .timid = 13, - .channel = CONFIG_STM32_TIM13_CHANNEL, - .timtype = TIMTYPE_TIM13, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM13, + .ops = &g_pwmops, + .timid = 13, + .channels = + { +#ifdef CONFIG_STM32_TIM13_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM13_CH1CFG, + .mode = CONFIG_STM32_TIM13_CH1MODE, + }, #endif - .base = STM32_TIM13_BASE, - .pincfg = PWM_TIM13_PINCFG, +#ifdef CONFIG_STM32_TIM13_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM13_CH2CFG, + .mode = CONFIG_STM32_TIM13_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM13_CH3CFG, + .mode = CONFIG_STM32_TIM13_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM13_CH4CFG, + .mode = CONFIG_STM32_TIM13_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM13, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM13, +#endif + .base = STM32_TIM13_BASE, .pclk = STM32_APB1_TIM13_CLKIN, }; #endif @@ -400,16 +764,128 @@ static struct stm32_pwmtimer_s g_pwm13dev = #ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmtimer_s g_pwm14dev = { - .ops = &g_pwmops, - .timid = 14, - .channel = CONFIG_STM32_TIM14_CHANNEL, - .timtype = TIMTYPE_TIM14, -#ifdef CONFIG_PWM_PULSECOUNT - .irq = STM32_IRQ_TIM14, + .ops = &g_pwmops, + .timid = 14, + .channels = + { +#ifdef CONFIG_STM32_TIM14_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM14_CH1CFG, + .mode = CONFIG_STM32_TIM14_CH1MODE, + }, #endif - .base = STM32_TIM14_BASE, - .pincfg = PWM_TIM14_PINCFG, - .pclk = STM32_APB1_TIM14_CLKIN, +#ifdef CONFIG_STM32_TIM14_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM14_CH2CFG, + .mode = CONFIG_STM32_TIM14_CH2MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL3 + { + .channel = 3, + .pincfg = PWM_TIM14_CH3CFG, + .mode = CONFIG_STM32_TIM14_CH3MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL4 + { + .channel = 4, + .pincfg = PWM_TIM14_CH4CFG, + .mode = CONFIG_STM32_TIM14_CH4MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM14, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM14, +#endif + .base = STM32_TIM14_BASE, + .pclk = STM32_APB1_TIM14_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +static struct stm32_pwmtimer_s g_pwm15dev = +{ + .ops = &g_pwmops, + .timid = 15, + .channels = + { +#ifdef CONFIG_STM32_TIM15_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM15_CH1CFG, + .mode = CONFIG_STM32_TIM15_CH1MODE, + }, +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 + { + .channel = 2, + .pincfg = PWM_TIM15_CH2CFG, + .mode = CONFIG_STM32_TIM15_CH2MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM15, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM15, +#endif + .base = STM32_TIM15_BASE, + .pclk = STM32_APB1_TIM15_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +static struct stm32_pwmtimer_s g_pwm16dev = +{ + .ops = &g_pwmops, + .timid = 16, + .channels = + { +#ifdef CONFIG_STM32_TIM16_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM16_CH1CFG, + .mode = CONFIG_STM32_TIM16_CH1MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM16, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM16, +#endif + .base = STM32_TIM16_BASE, + .pclk = STM32_APB1_TIM16_CLKIN, +}; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +static struct stm32_pwmtimer_s g_pwm17dev = +{ + .ops = &g_pwmops, + .timid = 17, + .channels = + { +#ifdef CONFIG_STM32_TIM17_CHANNEL1 + { + .channel = 1, + .pincfg = PWM_TIM17_CH1CFG, + .mode = CONFIG_STM32_TIM17_CH1MODE, + }, +#endif + }, + .timtype = TIMTYPE_TIM17, + .mode = STM32_TIMMODE_COUNTUP, +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM17, +#endif + .base = STM32_TIM17_BASE, + .pclk = STM32_APB1_TIM17_CLKIN, }; #endif @@ -551,6 +1027,10 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, FAR const struct pwm_info_s *info) { +#ifdef CONFIG_PWM_MULTICHAN + int i; +#endif + /* Calculated values */ uint32_t prescaler; @@ -563,18 +1043,31 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, uint16_t cr1; uint16_t ccer; uint16_t cr2; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t ccmr1; + uint32_t ccmr2; +#else uint16_t ccmr1; uint16_t ccmr2; +#endif /* New timer regiser bit settings */ uint16_t ccenable; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t ocmode1; + uint32_t ocmode2; +#else uint16_t ocmode1; uint16_t ocmode2; +#endif DEBUGASSERT(priv != NULL && info != NULL); -#ifdef CONFIG_PWM_PULSECOUNT +#if defined(CONFIG_PWM_MULTICHAN) + pwmvdbg("TIM%d frequency: %d\n", + priv->timid, info->frequency); +#elif defined(CONFIG_PWM_PULSECOUNT) pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x count: %d\n", priv->timid, priv->channel, info->frequency, info->duty, info->count); @@ -582,8 +1075,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n", priv->timid, priv->channel, info->frequency, info->duty); #endif - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_PWM_MULTICHAN + DEBUGASSERT(info->duty > 0 && info->duty < uitoub16(100)); +#endif /* Disable all interrupts and DMA requests, clear all pending status */ @@ -647,22 +1142,16 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, reload = 65535; } - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(info->duty * reload + b16HALF); - - pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d ccr: %d\n", - priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload, ccr); + pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d\n", + priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload); /* Set up the timer CR1 register: * - * 1-8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); @@ -672,25 +1161,53 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, cr1 &= ~GTIM_CR1_CEN; /* Set the counter mode for the advanced timers (1,8) and most general - * purpose timers (all 2-5, but not 9-14), i.e., all but TIMTYPE_COUNTUP16 + * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 * and TIMTYPE_BASIC */ -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ - defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16) { - /* Select the Counter Mode == count up: + /* Select the Counter Mode: * * GTIM_CR1_EDGE: The counter counts up or down depending on the - * direction bit(DIR). + * direction bit (DIR). + * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter + * counts up then down. * GTIM_CR1_DIR: 0: count up, 1: count down */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; + + switch (priv->mode) + { + case STM32_TIMMODE_COUNTUP: + cr1 |= GTIM_CR1_EDGE; + break; + + case STM32_TIMMODE_COUNTDOWN: + cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; + break; + + case STM32_TIMMODE_CENTER1: + cr1 |= GTIM_CR1_CENTER1; + break; + + case STM32_TIMMODE_CENTER2: + cr1 |= GTIM_CR1_CENTER2; + break; + + case STM32_TIMMODE_CENTER3: + cr1 |= GTIM_CR1_CENTER3; + break; + + default: + pwmdbg("No such timer mode: %d\n", (int)priv->mode); + return -EINVAL; + } } #endif @@ -706,7 +1223,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - /* Set the advanced timer's repitition counter */ + /* Set the advanced timer's repetition counter */ #if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) @@ -719,12 +1236,12 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, #ifdef CONFIG_PWM_PULSECOUNT if (info->count > 0) { - /* Save the remining count and the number of counts that will have + /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. */ /* If the first interrupt occurs at the end end of the first - * repition count, then the count will be the same as the RCR + * repetition count, then the count will be the same as the RCR * value. */ @@ -746,12 +1263,12 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } - /* Otherwise, just clear the repitition counter */ + /* Otherwise, just clear the repetition counter */ else #endif { - /* Set the repeition counter to zero */ + /* Set the repetition counter to zero */ pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); @@ -770,85 +1287,203 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Handle channel specific setup */ - ocmode1 = 0; - ocmode2 = 0; - switch (priv->channel) + ccenable = 0; + ocmode1 = 0; + ocmode2 = 0; + +#ifdef CONFIG_PWM_MULTICHAN + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) +#endif { - case 1: /* PWM Mode configuration: Channel 1 */ + ub16_t duty; +#ifdef CONFIG_STM32_STM32F30XX + uint32_t chanmode; + bool ocmbit = false; +#else + uint16_t chanmode; +#endif + uint8_t channel; +#ifdef CONFIG_PWM_MULTICHAN + int j; +#endif + enum stm32_chanmode_e mode; + +#ifdef CONFIG_PWM_MULTICHAN + duty = info->channels[i].duty; + channel = info->channels[i].channel; + + for (j = 0; j < PWM_NCHANNELS; j++) { - /* Select the CCER enable bit for this channel */ - - ccenable = ATIM_CCER_CC1E; - - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | - ATIM_CCMR1_OC1PE; - - /* Set the duty cycle by writing to the CCR register for this channel */ - - pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr); + if (priv->channels[j].channel == channel) + { + mode = priv->channels[j].mode; + break; + } } - break; - case 2: /* PWM Mode configuration: Channel 2 */ + if (j >= PWM_NCHANNELS) { - /* Select the CCER enable bit for this channel */ - - ccenable = ATIM_CCER_CC2E; - - /* Set the CCMR1 mode values (leave CCMR2 zero) */ - - ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | - ATIM_CCMR1_OC2PE; - - /* Set the duty cycle by writing to the CCR register for this channel */ - - pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr); + pwmdbg("No such channel: %d\n", channel); + return -EINVAL; } - break; +#else + duty = info->duty; + channel = priv->channels[0].channel; + mode = priv->channels[0].mode; +#endif - case 3: /* PWM Mode configuration: Channel3 */ + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwmvdbg("ccr: %d\n", ccr); + + switch (mode) { - /* Select the CCER enable bit for this channel */ + case STM32_CHANMODE_PWM1: + chanmode = ATIM_CCMR_MODE_PWM1; + break; - ccenable = ATIM_CCER_CC3E; + case STM32_CHANMODE_PWM2: + chanmode = ATIM_CCMR_MODE_PWM2; + break; - /* Set the CCMR2 mode values (leave CCMR1 zero) */ +#ifdef CONFIG_STM32_STM32F30XX + case STM32_CHANMODE_COMBINED1: + chanmode = ATIM_CCMR_MODE_COMBINED1; + ocmbit = true; + break; - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; + case STM32_CHANMODE_COMBINED2: + chanmode = ATIM_CCMR_MODE_COMBINED2; + ocmbit = true; + break; - /* Set the duty cycle by writing to the CCR register for this channel */ + case STM32_CHANMODE_ASYMMETRIC1: + chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; + ocmbit = true; + break; - pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr); + case STM32_CHANMODE_ASYMMETRIC2: + chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; + ocmbit = true; + break; +#endif + + default: + pwmdbg("No such mode: %d\n", (int)mode); + return -EINVAL; } - break; - case 4: /* PWM1 Mode configuration: Channel4 */ + switch (channel) { - /* Select the CCER enable bit for this channel */ + case 1: /* PWM Mode configuration: Channel 1 */ + { + /* Select the CCER enable bit for this channel */ - ccenable = ATIM_CCER_CC4E; + ccenable |= ATIM_CCER_CC1E; - /* Set the CCMR2 mode values (leave CCMR1 zero) */ + /* Set the CCMR1 mode values (leave CCMR2 zero) */ - ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; + ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | + (chanmode << ATIM_CCMR1_OC1M_SHIFT) | + ATIM_CCMR1_OC1PE; - /* Set the duty cycle by writing to the CCR register for this channel */ +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode1 |= ATIM_CCMR1_OC1M; + } +#endif - pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr); + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr); + } + break; + + case 2: /* PWM Mode configuration: Channel 2 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC2E; + + /* Set the CCMR1 mode values (leave CCMR2 zero) */ + + ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | + (chanmode << ATIM_CCMR1_OC2M_SHIFT) | + ATIM_CCMR1_OC2PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode1 |= ATIM_CCMR1_OC2M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr); + } + break; + + case 3: /* PWM Mode configuration: Channel 3 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC3E; + + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | + (chanmode << ATIM_CCMR2_OC3M_SHIFT) | + ATIM_CCMR2_OC3PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC3M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr); + } + break; + + case 4: /* PWM Mode configuration: Channel 4 */ + { + /* Select the CCER enable bit for this channel */ + + ccenable |= ATIM_CCER_CC4E; + + /* Set the CCMR2 mode values (leave CCMR1 zero) */ + + ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | + (chanmode << ATIM_CCMR2_OC4M_SHIFT) | + ATIM_CCMR2_OC4PE; + +#ifdef CONFIG_STM32_STM32F30XX + if (ocmbit) + { + ocmode2 |= ATIM_CCMR2_OC4M; + } +#endif + + /* Set the duty cycle by writing to the CCR register for this channel */ + + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr); + } + break; + + default: + pwmdbg("No such channel: %d\n", channel); + return -EINVAL; } - break; - - default: - pwmdbg("No such channel: %d\n", priv->channel); - return -EINVAL; } /* Disable the Channel by resetting the CCxE Bit in the CCER register */ @@ -866,9 +1501,17 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Reset the Output Compare Mode Bits and set the select output compare mode */ ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | - ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); + ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE +#ifdef CONFIG_STM32_STM32F30XX + | ATIM_CCMR1_OC1M | ATIM_CCMR1_OC2M +#endif + ); ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE | - ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE); + ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE +#ifdef CONFIG_STM32_STM32F30XX + | ATIM_CCMR2_OC3M | ATIM_CCMR2_OC4M +#endif + ); ccmr1 |= ocmode1; ccmr2 |= ocmode2; @@ -876,7 +1519,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P); - /* Enable the output state of the selected channel (only) */ + /* Enable the output state of the selected channels */ ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; @@ -892,7 +1535,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, * output compare N idle state. */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); #else @@ -914,11 +1558,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, bdtr |= ATIM_BDTR_MOE; pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); } -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) else #endif #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) { ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); } @@ -927,8 +1573,13 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Save the modified register values */ pwm_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); +#ifdef CONFIG_STM32_STM32F30XX + putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); + putreg32(ccmr2, priv->base + STM32_GTIM_CCMR2_OFFSET); +#else pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); +#endif pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the ARR Preload Bit */ @@ -939,7 +1590,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Setup update interrupt. If info->count is > 0, then we can be * assured that pwm_start() has already verified: (1) that this is an - * advanced timer, and that (2) the repetitioncount is within range. + * advanced timer, and that (2) the repetition count is within range. */ #ifdef CONFIG_PWM_PULSECOUNT @@ -1222,6 +1873,24 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM14EN; break; +#endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM15EN; + break; +#endif +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM16EN; + break; +#endif +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2ENR; + en_bit = RCC_APB2ENR_TIM17EN; + break; #endif } @@ -1260,18 +1929,32 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t pincfg; + int i; - pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwmvdbg("TIM%d\n", priv->timid); pwm_dumpregs(priv, "Initially"); /* Enable APB1/2 clocking for timer. */ pwm_set_apb_clock(priv, true); - /* Configure the PWM output pin, but do not start the timer yet */ + /* Configure the PWM output pins, but do not start the timer yet */ + + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg == 0) + { + continue; + } + + pwmvdbg("pincfg: %08x\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } - stm32_configgpio(priv->pincfg); - pwm_dumpgpio(priv->pincfg, "PWM setup"); return OK; } @@ -1295,8 +1978,9 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; uint32_t pincfg; + int i; - pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwmvdbg("TIM%d\n", priv->timid); /* Make sure that the output has been stopped */ @@ -1306,20 +1990,34 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pwm_set_apb_clock(priv, false); - /* Then put the GPIO pin back to the default state */ + /* Then put the GPIO pins back to the default state */ - pincfg = priv->pincfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + for (i = 0; i < PWM_NCHANNELS; i++) + { + pincfg = priv->channels[i].pincfg; + if (pincfg == 0) + { + continue; + } + + pwmvdbg("pincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); #if defined(CONFIG_STM32_STM32F10XX) - pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) - pincfg |= (GPIO_INPUT | GPIO_FLOAT); + pincfg |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + pincfg |= GPIO_INPUT | GPIO_FLOAT; #else # error "Unrecognized STM32 chip" #endif - stm32_configgpio(pincfg); + stm32_configgpio(pincfg); + } + return OK; } @@ -1491,6 +2189,24 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM14RST; break; +#endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM15RST; + break; +#endif +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM16RST; + break; +#endif +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + regaddr = STM32_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM17RST; + break; #endif } @@ -1552,7 +2268,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg * Input Parameters: * timer - A number identifying the timer use. The number of valid timer * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,14}. + * the range of {1,..,17}. * * Returned Value: * On success, a pointer to the STM32 lower half PWM driver is returned. @@ -1654,6 +2370,24 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif +#ifdef CONFIG_STM32_TIM15_PWM + case 15: + lower = &g_pwm15dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM16_PWM + case 16: + lower = &g_pwm16dev; + break; +#endif + +#ifdef CONFIG_STM32_TIM17_PWM + case 17: + lower = &g_pwm17dev; + break; +#endif + default: pwmdbg("No such timer configured\n"); return NULL; @@ -1662,4 +2396,4 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (FAR struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,14 */ +#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */ diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h index 96764de9bc..e636ead3a3 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/stm32/stm32_pwm.h @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_pwm.h * * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -96,6 +98,15 @@ #ifndef CONFIG_STM32_TIM14 # undef CONFIG_STM32_TIM14_PWM #endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM +#endif +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM +#endif +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM +#endif /* The basic timers (timer 6 and 7) are not capable of generating output pulses */ @@ -109,11 +120,597 @@ defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \ defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \ - defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) + defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) #include #include "chip/stm32_tim.h" +#ifdef CONFIG_PWM_MULTICHAN + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# else +# define PWM_TIM1_CH1CFG 0 +# endif +# define PWM_TIM1_CHANNEL1 1 +#else +# define PWM_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# else +# define PWM_TIM1_CH2CFG 0 +# endif +# define PWM_TIM1_CHANNEL2 1 +#else +# define PWM_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# else +# define PWM_TIM1_CH3CFG 0 +# endif +# define PWM_TIM1_CHANNEL3 1 +#else +# define PWM_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +# else +# define PWM_TIM1_CH4CFG 0 +# endif +# define PWM_TIM1_CHANNEL4 1 +#else +# define PWM_TIM1_CHANNEL4 0 +#endif +#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# else +# define PWM_TIM2_CH1CFG 0 +# endif +# define PWM_TIM2_CHANNEL1 1 +#else +# define PWM_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# else +# define PWM_TIM2_CH2CFG 0 +# endif +# define PWM_TIM2_CHANNEL2 1 +#else +# define PWM_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# else +# define PWM_TIM2_CH3CFG 0 +# endif +# define PWM_TIM2_CHANNEL3 1 +#else +# define PWM_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +# else +# define PWM_TIM2_CH4CFG 0 +# endif +# define PWM_TIM2_CHANNEL4 1 +#else +# define PWM_TIM2_CHANNEL4 0 +#endif +#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ + PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# else +# define PWM_TIM3_CH1CFG 0 +# endif +# define PWM_TIM3_CHANNEL1 1 +#else +# define PWM_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# else +# define PWM_TIM3_CH2CFG 0 +# endif +# define PWM_TIM3_CHANNEL2 1 +#else +# define PWM_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# else +# define PWM_TIM3_CH3CFG 0 +# endif +# define PWM_TIM3_CHANNEL3 1 +#else +# define PWM_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +# else +# define PWM_TIM3_CH4CFG 0 +# endif +# define PWM_TIM3_CHANNEL4 1 +#else +# define PWM_TIM3_CHANNEL4 0 +#endif +#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ + PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT +# else +# define PWM_TIM4_CH1CFG 0 +# endif +# define PWM_TIM4_CHANNEL1 1 +#else +# define PWM_TIM4_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT +# else +# define PWM_TIM4_CH2CFG 0 +# endif +# define PWM_TIM4_CHANNEL2 1 +#else +# define PWM_TIM4_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT +# else +# define PWM_TIM4_CH3CFG 0 +# endif +# define PWM_TIM4_CHANNEL3 1 +#else +# define PWM_TIM4_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT +# else +# define PWM_TIM4_CH4CFG 0 +# endif +# define PWM_TIM4_CHANNEL4 1 +#else +# define PWM_TIM4_CHANNEL4 0 +#endif +#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ + PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) + +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT +# else +# define PWM_TIM5_CH1CFG 0 +# endif +# define PWM_TIM5_CHANNEL1 1 +#else +# define PWM_TIM5_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT +# else +# define PWM_TIM5_CH2CFG 0 +# endif +# define PWM_TIM5_CHANNEL2 1 +#else +# define PWM_TIM5_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT +# else +# define PWM_TIM5_CH3CFG 0 +# endif +# define PWM_TIM5_CHANNEL3 1 +#else +# define PWM_TIM5_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT +# else +# define PWM_TIM5_CH4CFG 0 +# endif +# define PWM_TIM5_CHANNEL4 1 +#else +# define PWM_TIM5_CHANNEL4 0 +#endif +#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ + PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) + +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT +# else +# define PWM_TIM8_CH1CFG 0 +# endif +# define PWM_TIM8_CHANNEL1 1 +#else +# define PWM_TIM8_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT +# else +# define PWM_TIM8_CH2CFG 0 +# endif +# define PWM_TIM8_CHANNEL2 1 +#else +# define PWM_TIM8_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT +# else +# define PWM_TIM8_CH3CFG 0 +# endif +# define PWM_TIM8_CHANNEL3 1 +#else +# define PWM_TIM8_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT +# else +# define PWM_TIM8_CH4CFG 0 +# endif +# define PWM_TIM8_CHANNEL4 1 +#else +# define PWM_TIM8_CHANNEL4 0 +#endif +#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ + PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) + +#ifdef CONFIG_STM32_TIM9_CHANNEL1 +# ifdef CONFIG_STM32_TIM9_CH1OUT +# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT +# else +# define PWM_TIM9_CH1CFG 0 +# endif +# define PWM_TIM9_CHANNEL1 1 +#else +# define PWM_TIM9_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL2 +# ifdef CONFIG_STM32_TIM9_CH2OUT +# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT +# else +# define PWM_TIM9_CH2CFG 0 +# endif +# define PWM_TIM9_CHANNEL2 1 +#else +# define PWM_TIM9_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL3 +# ifdef CONFIG_STM32_TIM9_CH3OUT +# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT +# else +# define PWM_TIM9_CH3CFG 0 +# endif +# define PWM_TIM9_CHANNEL3 1 +#else +# define PWM_TIM9_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL4 +# ifdef CONFIG_STM32_TIM9_CH4OUT +# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT +# else +# define PWM_TIM9_CH4CFG 0 +# endif +# define PWM_TIM9_CHANNEL4 1 +#else +# define PWM_TIM9_CHANNEL4 0 +#endif +#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2 + \ + PWM_TIM9_CHANNEL3 + PWM_TIM9_CHANNEL4) + +#ifdef CONFIG_STM32_TIM10_CHANNEL1 +# ifdef CONFIG_STM32_TIM10_CH1OUT +# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT +# else +# define PWM_TIM10_CH1CFG 0 +# endif +# define PWM_TIM10_CHANNEL1 1 +#else +# define PWM_TIM10_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL2 +# ifdef CONFIG_STM32_TIM10_CH2OUT +# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT +# else +# define PWM_TIM10_CH2CFG 0 +# endif +# define PWM_TIM10_CHANNEL2 1 +#else +# define PWM_TIM10_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL3 +# ifdef CONFIG_STM32_TIM10_CH3OUT +# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT +# else +# define PWM_TIM10_CH3CFG 0 +# endif +# define PWM_TIM10_CHANNEL3 1 +#else +# define PWM_TIM10_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL4 +# ifdef CONFIG_STM32_TIM10_CH4OUT +# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT +# else +# define PWM_TIM10_CH4CFG 0 +# endif +# define PWM_TIM10_CHANNEL4 1 +#else +# define PWM_TIM10_CHANNEL4 0 +#endif +#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1 + PWM_TIM10_CHANNEL2 + \ + PWM_TIM10_CHANNEL3 + PWM_TIM10_CHANNEL4) + +#ifdef CONFIG_STM32_TIM11_CHANNEL1 +# ifdef CONFIG_STM32_TIM11_CH1OUT +# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT +# else +# define PWM_TIM11_CH1CFG 0 +# endif +# define PWM_TIM11_CHANNEL1 1 +#else +# define PWM_TIM11_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL2 +# ifdef CONFIG_STM32_TIM11_CH2OUT +# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT +# else +# define PWM_TIM11_CH2CFG 0 +# endif +# define PWM_TIM11_CHANNEL2 1 +#else +# define PWM_TIM11_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL3 +# ifdef CONFIG_STM32_TIM11_CH3OUT +# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT +# else +# define PWM_TIM11_CH3CFG 0 +# endif +# define PWM_TIM11_CHANNEL3 1 +#else +# define PWM_TIM11_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL4 +# ifdef CONFIG_STM32_TIM11_CH4OUT +# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT +# else +# define PWM_TIM11_CH4CFG 0 +# endif +# define PWM_TIM11_CHANNEL4 1 +#else +# define PWM_TIM11_CHANNEL4 0 +#endif +#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1 + PWM_TIM11_CHANNEL2 + \ + PWM_TIM11_CHANNEL3 + PWM_TIM11_CHANNEL4) + +#ifdef CONFIG_STM32_TIM12_CHANNEL1 +# ifdef CONFIG_STM32_TIM12_CH1OUT +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT +# else +# define PWM_TIM12_CH1CFG 0 +# endif +# define PWM_TIM12_CHANNEL1 1 +#else +# define PWM_TIM12_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL2 +# ifdef CONFIG_STM32_TIM12_CH2OUT +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT +# else +# define PWM_TIM12_CH2CFG 0 +# endif +# define PWM_TIM12_CHANNEL2 1 +#else +# define PWM_TIM12_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL3 +# ifdef CONFIG_STM32_TIM12_CH3OUT +# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT +# else +# define PWM_TIM12_CH3CFG 0 +# endif +# define PWM_TIM12_CHANNEL3 1 +#else +# define PWM_TIM12_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL4 +# ifdef CONFIG_STM32_TIM12_CH4OUT +# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT +# else +# define PWM_TIM12_CH4CFG 0 +# endif +# define PWM_TIM12_CHANNEL4 1 +#else +# define PWM_TIM12_CHANNEL4 0 +#endif +#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2 + \ + PWM_TIM12_CHANNEL3 + PWM_TIM12_CHANNEL4) + +#ifdef CONFIG_STM32_TIM13_CHANNEL1 +# ifdef CONFIG_STM32_TIM13_CH1OUT +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT +# else +# define PWM_TIM13_CH1CFG 0 +# endif +# define PWM_TIM13_CHANNEL1 1 +#else +# define PWM_TIM13_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL2 +# ifdef CONFIG_STM32_TIM13_CH2OUT +# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT +# else +# define PWM_TIM13_CH2CFG 0 +# endif +# define PWM_TIM13_CHANNEL2 1 +#else +# define PWM_TIM13_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL3 +# ifdef CONFIG_STM32_TIM13_CH3OUT +# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT +# else +# define PWM_TIM13_CH3CFG 0 +# endif +# define PWM_TIM13_CHANNEL3 1 +#else +# define PWM_TIM13_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL4 +# ifdef CONFIG_STM32_TIM13_CH4OUT +# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT +# else +# define PWM_TIM13_CH4CFG 0 +# endif +# define PWM_TIM13_CHANNEL4 1 +#else +# define PWM_TIM13_CHANNEL4 0 +#endif +#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1 + PWM_TIM13_CHANNEL2 + \ + PWM_TIM13_CHANNEL3 + PWM_TIM13_CHANNEL4) + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# else +# define PWM_TIM14_CH1CFG 0 +# endif +# define PWM_TIM14_CHANNEL1 1 +#else +# define PWM_TIM14_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL2 +# ifdef CONFIG_STM32_TIM14_CH2OUT +# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT +# else +# define PWM_TIM14_CH2CFG 0 +# endif +# define PWM_TIM14_CHANNEL2 1 +#else +# define PWM_TIM14_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL3 +# ifdef CONFIG_STM32_TIM14_CH3OUT +# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT +# else +# define PWM_TIM14_CH3CFG 0 +# endif +# define PWM_TIM14_CHANNEL3 1 +#else +# define PWM_TIM14_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL4 +# ifdef CONFIG_STM32_TIM14_CH4OUT +# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT +# else +# define PWM_TIM14_CH4CFG 0 +# endif +# define PWM_TIM14_CHANNEL4 1 +#else +# define PWM_TIM14_CHANNEL4 0 +#endif +#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1 + PWM_TIM14_CHANNEL2 + \ + PWM_TIM14_CHANNEL3 + PWM_TIM14_CHANNEL4) + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# else +# define PWM_TIM15_CH1CFG 0 +# endif +# define PWM_TIM15_CHANNEL1 1 +#else +# define PWM_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# define PWM_TIM15_CH2CFG 0 +# endif +# define PWM_TIM15_CHANNEL2 1 +#else +# define PWM_TIM15_CHANNEL2 0 +#endif +#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# define PWM_TIM16_CH1CFG 0 +# endif +# define PWM_TIM16_CHANNEL1 1 +#else +# define PWM_TIM16_CHANNEL1 0 +#endif +#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# define PWM_TIM17_CH1CFG 0 +# endif +# define PWM_TIM17_CHANNEL1 1 +#else +# define PWM_TIM17_CHANNEL1 0 +#endif +#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 + +#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \ + PWM_MAX(PWM_TIM2_NCHANNELS, \ + PWM_MAX(PWM_TIM3_NCHANNELS, \ + PWM_MAX(PWM_TIM4_NCHANNELS, \ + PWM_MAX(PWM_TIM5_NCHANNELS, \ + PWM_MAX(PWM_TIM8_NCHANNELS, \ + PWM_MAX(PWM_TIM9_NCHANNELS, \ + PWM_MAX(PWM_TIM10_NCHANNELS, \ + PWM_MAX(PWM_TIM11_NCHANNELS, \ + PWM_MAX(PWM_TIM12_NCHANNELS, \ + PWM_MAX(PWM_TIM13_NCHANNELS, \ + PWM_MAX(PWM_TIM14_NCHANNELS, \ + PWM_MAX(PWM_TIM15_NCHANNELS, \ + PWM_MAX(PWM_TIM16_NCHANNELS, \ + PWM_TIM17_NCHANNELS)))))))))))))) + +#else + /* For each timer that is enabled for PWM usage, we need the following additional * configuration settings: * @@ -131,13 +728,21 @@ # if !defined(CONFIG_STM32_TIM1_CHANNEL) # error "CONFIG_STM32_TIM1_CHANNEL must be provided" # elif CONFIG_STM32_TIM1_CHANNEL == 1 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH1OUT +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # elif CONFIG_STM32_TIM1_CHANNEL == 2 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH2OUT +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # elif CONFIG_STM32_TIM1_CHANNEL == 3 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH3OUT +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # elif CONFIG_STM32_TIM1_CHANNEL == 4 -# define PWM_TIM1_PINCFG GPIO_TIM1_CH4OUT +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif @@ -147,13 +752,21 @@ # if !defined(CONFIG_STM32_TIM2_CHANNEL) # error "CONFIG_STM32_TIM2_CHANNEL must be provided" # elif CONFIG_STM32_TIM2_CHANNEL == 1 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH1OUT +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # elif CONFIG_STM32_TIM2_CHANNEL == 2 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH2OUT +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # elif CONFIG_STM32_TIM2_CHANNEL == 3 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH3OUT +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # elif CONFIG_STM32_TIM2_CHANNEL == 4 -# define PWM_TIM2_PINCFG GPIO_TIM2_CH4OUT +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif @@ -163,13 +776,21 @@ # if !defined(CONFIG_STM32_TIM3_CHANNEL) # error "CONFIG_STM32_TIM3_CHANNEL must be provided" # elif CONFIG_STM32_TIM3_CHANNEL == 1 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH1OUT +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # elif CONFIG_STM32_TIM3_CHANNEL == 2 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH2OUT +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # elif CONFIG_STM32_TIM3_CHANNEL == 3 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH3OUT +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # elif CONFIG_STM32_TIM3_CHANNEL == 4 -# define PWM_TIM3_PINCFG GPIO_TIM3_CH4OUT +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif @@ -179,13 +800,21 @@ # if !defined(CONFIG_STM32_TIM4_CHANNEL) # error "CONFIG_STM32_TIM4_CHANNEL must be provided" # elif CONFIG_STM32_TIM4_CHANNEL == 1 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH1OUT +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT # elif CONFIG_STM32_TIM4_CHANNEL == 2 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH2OUT +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT # elif CONFIG_STM32_TIM4_CHANNEL == 3 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH3OUT +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT # elif CONFIG_STM32_TIM4_CHANNEL == 4 -# define PWM_TIM4_PINCFG GPIO_TIM4_CH4OUT +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif @@ -195,13 +824,21 @@ # if !defined(CONFIG_STM32_TIM5_CHANNEL) # error "CONFIG_STM32_TIM5_CHANNEL must be provided" # elif CONFIG_STM32_TIM5_CHANNEL == 1 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH1OUT +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT # elif CONFIG_STM32_TIM5_CHANNEL == 2 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH2OUT +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT # elif CONFIG_STM32_TIM5_CHANNEL == 3 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH3OUT +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT # elif CONFIG_STM32_TIM5_CHANNEL == 4 -# define PWM_TIM5_PINCFG GPIO_TIM5_CH4OUT +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif @@ -211,13 +848,21 @@ # if !defined(CONFIG_STM32_TIM8_CHANNEL) # error "CONFIG_STM32_TIM8_CHANNEL must be provided" # elif CONFIG_STM32_TIM8_CHANNEL == 1 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH1OUT +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # elif CONFIG_STM32_TIM8_CHANNEL == 2 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH2OUT +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # elif CONFIG_STM32_TIM8_CHANNEL == 3 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH3OUT +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # elif CONFIG_STM32_TIM8_CHANNEL == 4 -# define PWM_TIM8_PINCFG GPIO_TIM8_CH4OUT +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif @@ -227,13 +872,21 @@ # if !defined(CONFIG_STM32_TIM9_CHANNEL) # error "CONFIG_STM32_TIM9_CHANNEL must be provided" # elif CONFIG_STM32_TIM9_CHANNEL == 1 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH1OUT +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT # elif CONFIG_STM32_TIM9_CHANNEL == 2 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH2OUT +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT # elif CONFIG_STM32_TIM9_CHANNEL == 3 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH3OUT +# define CONFIG_STM32_TIM9_CHANNEL3 1 +# define CONFIG_STM32_TIM9_CH3MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT # elif CONFIG_STM32_TIM9_CHANNEL == 4 -# define PWM_TIM9_PINCFG GPIO_TIM9_CH4OUT +# define CONFIG_STM32_TIM9_CHANNEL4 1 +# define CONFIG_STM32_TIM9_CH4MODE CONFIG_STM32_TIM9_CHMODE +# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif @@ -243,13 +896,21 @@ # if !defined(CONFIG_STM32_TIM10_CHANNEL) # error "CONFIG_STM32_TIM10_CHANNEL must be provided" # elif CONFIG_STM32_TIM10_CHANNEL == 1 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH1OUT +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT # elif CONFIG_STM32_TIM10_CHANNEL == 2 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH2OUT +# define CONFIG_STM32_TIM10_CHANNEL2 1 +# define CONFIG_STM32_TIM10_CH2MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT # elif CONFIG_STM32_TIM10_CHANNEL == 3 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH3OUT +# define CONFIG_STM32_TIM10_CHANNEL3 1 +# define CONFIG_STM32_TIM10_CH3MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT # elif CONFIG_STM32_TIM10_CHANNEL == 4 -# define PWM_TIM10_PINCFG GPIO_TIM10_CH4OUT +# define CONFIG_STM32_TIM10_CHANNEL4 1 +# define CONFIG_STM32_TIM10_CH4MODE CONFIG_STM32_TIM10_CHMODE +# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif @@ -259,13 +920,21 @@ # if !defined(CONFIG_STM32_TIM11_CHANNEL) # error "CONFIG_STM32_TIM11_CHANNEL must be provided" # elif CONFIG_STM32_TIM11_CHANNEL == 1 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH1OUT +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT # elif CONFIG_STM32_TIM11_CHANNEL == 2 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH2OUT +# define CONFIG_STM32_TIM11_CHANNEL2 1 +# define CONFIG_STM32_TIM11_CH2MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT # elif CONFIG_STM32_TIM11_CHANNEL == 3 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH3OUT +# define CONFIG_STM32_TIM11_CHANNEL3 1 +# define CONFIG_STM32_TIM11_CH3MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT # elif CONFIG_STM32_TIM11_CHANNEL == 4 -# define PWM_TIM11_PINCFG GPIO_TIM11_CH4OUT +# define CONFIG_STM32_TIM11_CHANNEL4 1 +# define CONFIG_STM32_TIM11_CH4MODE CONFIG_STM32_TIM11_CHMODE +# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif @@ -275,13 +944,21 @@ # if !defined(CONFIG_STM32_TIM12_CHANNEL) # error "CONFIG_STM32_TIM12_CHANNEL must be provided" # elif CONFIG_STM32_TIM12_CHANNEL == 1 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH1OUT +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT # elif CONFIG_STM32_TIM12_CHANNEL == 2 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH2OUT +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT # elif CONFIG_STM32_TIM12_CHANNEL == 3 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH3OUT +# define CONFIG_STM32_TIM12_CHANNEL3 1 +# define CONFIG_STM32_TIM12_CH3MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT # elif CONFIG_STM32_TIM12_CHANNEL == 4 -# define PWM_TIM12_PINCFG GPIO_TIM12_CH4OUT +# define CONFIG_STM32_TIM12_CHANNEL4 1 +# define CONFIG_STM32_TIM12_CH4MODE CONFIG_STM32_TIM12_CHMODE +# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif @@ -291,13 +968,21 @@ # if !defined(CONFIG_STM32_TIM13_CHANNEL) # error "CONFIG_STM32_TIM13_CHANNEL must be provided" # elif CONFIG_STM32_TIM13_CHANNEL == 1 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH1OUT +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT # elif CONFIG_STM32_TIM13_CHANNEL == 2 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH2OUT +# define CONFIG_STM32_TIM13_CHANNEL2 1 +# define CONFIG_STM32_TIM13_CH2MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT # elif CONFIG_STM32_TIM13_CHANNEL == 3 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH3OUT +# define CONFIG_STM32_TIM13_CHANNEL3 1 +# define CONFIG_STM32_TIM13_CH3MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT # elif CONFIG_STM32_TIM13_CHANNEL == 4 -# define PWM_TIM13_PINCFG GPIO_TIM13_CH4OUT +# define CONFIG_STM32_TIM13_CHANNEL4 1 +# define CONFIG_STM32_TIM13_CH4MODE CONFIG_STM32_TIM13_CHMODE +# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif @@ -307,18 +992,70 @@ # if !defined(CONFIG_STM32_TIM14_CHANNEL) # error "CONFIG_STM32_TIM14_CHANNEL must be provided" # elif CONFIG_STM32_TIM14_CHANNEL == 1 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH1OUT +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT # elif CONFIG_STM32_TIM14_CHANNEL == 2 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH2OUT +# define CONFIG_STM32_TIM14_CHANNEL2 1 +# define CONFIG_STM32_TIM14_CH2MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT # elif CONFIG_STM32_TIM14_CHANNEL == 3 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH3OUT +# define CONFIG_STM32_TIM14_CHANNEL3 1 +# define CONFIG_STM32_TIM14_CH3MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT # elif CONFIG_STM32_TIM14_CHANNEL == 4 -# define PWM_TIM14_PINCFG GPIO_TIM14_CH4OUT +# define CONFIG_STM32_TIM14_CHANNEL4 1 +# define CONFIG_STM32_TIM14_CH4MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT # else # error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif #endif +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" +# endif +#endif + +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" +# endif +#endif + +#define PWM_NCHANNELS 1 + +#endif + /************************************************************************************ * Public Types ************************************************************************************/ @@ -351,7 +1088,7 @@ extern "C" * Input Parameters: * timer - A number identifying the timer use. The number of valid timer * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,14}. + * the range of {1,..,17}. * * Returned Value: * On success, a pointer to the STM32 lower half PWM driver is returned. From f6d7da24a7cd6c3b6a5a80a76a4deec704b9e77c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 2 Nov 2015 06:39:24 -0600 Subject: [PATCH 23/41] SAM4CM should advertise that it supports Tickless operation in Kconfig --- arch/arm/src/sam34/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 56c7ff2c9f..65d456fa96 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A config ARCH_CHIP_SAM4CM bool default n + select ARCH_HAVE_TICKLESS config ARCH_CHIP_SAM4L bool From c90876ff9c0ad935b0872ff586b3ecaa082c038a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 2 Nov 2015 13:58:19 -0600 Subject: [PATCH 24/41] SAMV7: Add configuration support (only) for use of USART as SPI --- arch/arm/src/samv7/sam_config.h | 22 +++++--- arch/arm/src/samv7/sam_serial.c | 90 ++++++++++++++++++++------------- 2 files changed, 70 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/samv7/sam_config.h b/arch/arm/src/samv7/sam_config.h index 8aca6fb6fd..242c2eb503 100644 --- a/arch/arm/src/samv7/sam_config.h +++ b/arch/arm/src/samv7/sam_config.h @@ -109,18 +109,26 @@ #endif /* USARTs *******************************************************************/ -/* If the USART is not being used as a UART, then it really isn't enabled - * for our purposes. +/* If the USART is not being used as a UART or for SPI, then it really isn't + * enabled for our purposes. */ -#ifndef CONFIG_USART0_ISUART +#if !defined(CONFIG_USART0_ISUART) && !defined(CONFIG_USART0_ISSPI) # undef CONFIG_SAMV7_USART0 +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART0_IFLOWCONTROL #endif -#ifndef CONFIG_USART1_ISUART + +#if !defined(CONFIG_USART1_ISUART) && !defined(CONFIG_USART1_ISSPI) # undef CONFIG_SAMV7_USART1 +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART1_IFLOWCONTROL #endif -#ifndef CONFIG_USART2_ISUART + +#if !defined(CONFIG_USART2_ISUART) && !defined(CONFIG_USART2_ISSPI) # undef CONFIG_SAMV7_USART2 +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART2_IFLOWCONTROL #endif /* Don't enable USARTs not supported by the chip. */ @@ -153,10 +161,10 @@ #undef CONFIG_UART3_IFLOWCONTROL #undef CONFIG_UART4_IFLOWCONTROL -/* Hardware flow control requires using DMAC channel (not yet supported) */ +/* Hardware flow control requires using a DMAC channel (not yet supported) */ #ifdef CONFIG_SERIAL_IFLOWCONTROL -# warning PDC or DMAC support is required for RTS hardware flow control +# warning XDMAC support is required for RTS hardware flow control # undef CONFIG_SERIAL_IFLOWCONTROL # undef CONFIG_USART0_IFLOWCONTROL # undef CONFIG_USART1_IFLOWCONTROL diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 47f7d8e926..a520350f98 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -123,13 +123,13 @@ # elif defined(CONFIG_SAMV7_UART4) # define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ # define UART4_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART0) +# elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) # define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ # define USART0_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART1) +# elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) # define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ # define USART1_ASSIGNED 1 -# elif defined(CONFIG_SAMV7_USART2) +# elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) # define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ # define USART2_ASSIGNED 1 # endif @@ -154,13 +154,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */ # define USART2_ASSIGNED 1 #endif @@ -182,13 +185,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */ # define USART2_ASSIGNED 1 #endif @@ -207,13 +213,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */ # define USART2_ASSIGNED 1 #endif @@ -229,13 +238,16 @@ #elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ # define USART2_ASSIGNED 1 #endif @@ -248,13 +260,16 @@ #if defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED) # define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ # define UART4_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ # define USART2_ASSIGNED 1 #endif @@ -264,13 +279,16 @@ * One of USART0-2 could also be the console. */ -#if defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED) +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \ + !defined(USART0_ASSIGNED) # define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */ # define USART0_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */ # define USART2_ASSIGNED 1 #endif @@ -280,10 +298,12 @@ * One of of USART1-2 could also be the console. */ -#if defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED) +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \ + !defined(USART1_ASSIGNED) # define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */ # define USART1_ASSIGNED 1 -#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED) +#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \ + !defined(USART2_ASSIGNED) # define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */ # define USART2_ASSIGNED 1 #endif @@ -349,13 +369,13 @@ static int sam_uart3_interrupt(int irq, void *context); #ifdef CONFIG_SAMV7_UART4 static int sam_uart4_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static int sam_usart0_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static int sam_usart1_interrupt(int irq, void *context); #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static int sam_usart2_interrupt(int irq, void *context); #endif static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); @@ -412,15 +432,15 @@ static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; #endif @@ -582,7 +602,7 @@ static uart_dev_t g_uart4port = /* This describes the state of the USART0 port. */ -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static struct sam_dev_s g_usart0priv = { .usartbase = SAM_USART0_BASE, @@ -616,7 +636,7 @@ static uart_dev_t g_usart0port = /* This describes the state of the USART1 port. */ -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static struct sam_dev_s g_usart1priv = { .usartbase = SAM_USART1_BASE, @@ -650,7 +670,7 @@ static uart_dev_t g_usart1port = /* This describes the state of the USART2 port. */ -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static struct sam_dev_s g_usart2priv = { .usartbase = SAM_USART2_BASE, @@ -1095,19 +1115,19 @@ static int sam_uart4_interrupt(int irq, void *context) * ****************************************************************************/ -#ifdef CONFIG_SAMV7_USART0 +#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) static int sam_usart0_interrupt(int irq, void *context) { return sam_interrupt(&g_usart0port); } #endif -#ifdef CONFIG_SAMV7_USART1 +#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) static int sam_usart1_interrupt(int irq, void *context) { return sam_interrupt(&g_usart1port); } #endif -#ifdef CONFIG_SAMV7_USART2 +#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) static int sam_usart2_interrupt(int irq, void *context) { return sam_interrupt(&g_usart2port); From 1299160d1d9aff2cc15d55718ff84ded1ffba90f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 3 Nov 2015 10:47:37 -0600 Subject: [PATCH 25/41] SAMV71-XULT: Add call to can_txready() to MCAN driver. This is part of a fix to a CAN hang problem --- arch/arm/src/samv7/Kconfig | 2 ++ arch/arm/src/samv7/sam_mcan.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 3dede34314..7aa5707bd0 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -223,6 +223,7 @@ config SAMV7_MCAN0 bool "CAN controller 0 (MCAN0)" default n select CAN + select CAN_TXREADY select SAMV7_MCAN config SAMV7_MCAN1 @@ -230,6 +231,7 @@ config SAMV7_MCAN1 default n depends on SAMV7_HAVE_MCAN1 select CAN + select CAN_TXREADY select SAMV7_MCAN config SAMV7_DAC0 diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 1fcefd32c7..b72a08d4df 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -128,6 +128,12 @@ # endif #endif +/* General Configuration ****************************************************/ + +#ifndef CONFIG_CAN_TXREADY +# warning WARNING!!! CONFIG_CAN_TXREADY is required by this driver +#endif + /* MCAN0 Configuration ******************************************************/ #ifdef CONFIG_SAMV7_MCAN0 @@ -3190,6 +3196,14 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) mcan_buffer_release(priv); handled = true; + +#ifdef CONFIG_CAN_TXREADY + /* Inform the upper half driver that we are again ready to accept + * data in mcan_send(). + */ + + can_txready(dev); +#endif } else if ((pending & priv->txints) != 0) { From 9cbbfe7e596f9c9f5f0064ff67b662b795cd1321 Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Wed, 4 Nov 2015 08:03:27 -0600 Subject: [PATCH 26/41] SAMV7 MCAN: Fix receipt of RTR requests. From Frank Benkert --- arch/arm/src/samv7/sam_mcan.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index b72a08d4df..adc71f2ea8 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -3045,10 +3045,18 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer, regval = *rxbuffer++; canregdbg("R0: %08x\n", regval); - hdr.ch_rtr = 0; hdr.ch_error = 0; hdr.ch_unused = 0; + if ((regval & BUFFER_R0_RTR) != 0) + { + hdr.ch_rtr = true; + } + else + { + hdr.ch_rtr = false; + } + #ifdef CONFIG_CAN_EXTID if ((regval & BUFFER_R0_XTD) != 0) { @@ -3466,14 +3474,11 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv) /* Global Filter Configuration: * - * ANFS=0: Store all rejected extended frame in RX FIFO0 - * ANFE=0: Store all rejected extended frame in RX FIFO0 - * FFSE=1: Reject all remote frames with 11-bit standard IDs. - * RRFE=1: Reject all remote frames with 29-bit extended IDs. + * ANFS=0: Store all non matching standard frame in RX FIFO0 + * ANFE=0: Store all non matching extended frame in RX FIFO0 */ - regval = MCAN_GFC_RRFE | MCAN_GFC_RRFS | MCAN_GFC_ANFE_RX_FIFO0 | - MCAN_GFC_ANFS_RX_FIFO0; + regval = MCAN_GFC_ANFE_RX_FIFO0 | MCAN_GFC_ANFS_RX_FIFO0; mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval); /* Extended ID Filter AND mask */ From 7d793bb99b90effb9d18a0c7645674bf77365f0b Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Thu, 5 Nov 2015 10:09:37 -0500 Subject: [PATCH 27/41] STM32 ADC: Add support for STM32F30xxx --- arch/arm/src/stm32/chip/stm32_adc.h | 130 +- arch/arm/src/stm32/chip/stm32f30xxx_adc.h | 233 ++- arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h | 54 +- arch/arm/src/stm32/stm32_adc.c | 1802 ++++++++++-------- arch/arm/src/stm32/stm32_adc.h | 1137 +++++++++-- 5 files changed, 2273 insertions(+), 1083 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h index ea9579c391..3a59ba25a8 100644 --- a/arch/arm/src/stm32/chip/stm32_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc.h @@ -308,24 +308,37 @@ /* Bits 12-15: Reserved */ # define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ # define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T1CC4 (0x0 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event. For STM32L15XX: TIM9_CC1 event */ -# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event. For STM32L15XX: TIM9_TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event. For STM32L15XX: TIM2_TRGO event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event. For STM32L15XX: TIM2_CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event. For STM32L15XX: TIM3_CC4 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event. For STM32L15XX: TIM4_TRGO event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event. For STM32L15XX: TIM4_CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event. For STM32L15XX: TIM4_CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event. For STM32L15XX: TIM4_CC3 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event. For STM32L15XX: TIM10_CC1 event */ -# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event. For STM32L15XX: TIM7_TRGO event */ -# ifndef CONFIG_STM32_STM32L15XX -# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event. */ -# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event. */ -# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event. */ -# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event. */ +# ifdef CONFIG_STM32_STM32L15XX +# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ +# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ +# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ +# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +# else +# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ +# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ +# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ +# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ +# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ +# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ # endif -# define ADC_CR2_JEXTSEL_EXTI (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line15 */ # define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ # define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) @@ -338,24 +351,37 @@ /* Bit 23: Reserved, must be kept at reset value. */ # define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ # define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event. For STM32L15XX: TIM9_CC2 event */ -# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event. For STM32L15XX: TIM9_TRGO event */ -# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event. For STM32L15XX: TIM2_CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event. For STM32L15XX: TIM2_CC2 event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event. For STM32L15XX: TIM3_TRGO event */ -# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event. For STM32L15XX: TIM4_CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event. For STM32L15XX: TIM2_TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event. For STM32L15XX: TIM3_CC1 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event. For STM32L15XX: TIM3_CC3 event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event. For STM32L15XX: TIM4_TRGO event */ -# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event. For STM32L15XX: TIM6_TRGO event */ -# ifndef CONFIG_STM32_STM32L15XX +# ifdef CONFIG_STM32_STM32L15XX +# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ +# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ +# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +# else +# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ # define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ # define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ # define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ # define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ # endif -# define ADC_CR2_EXTSEL_EXTI (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line11 */ # define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ # define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) @@ -375,7 +401,7 @@ # define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ # define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ # define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */ +# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ # define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ # define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ @@ -387,7 +413,7 @@ # define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ # define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ # define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */ +# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ # define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ # define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ @@ -585,6 +611,9 @@ # define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ # define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) # define ADC_SQR1_RESERVED (0xff000000) +# define ADC_SQR1_FIRST (13) +# define ADC_SQR1_LAST (16) +# define ADC_SQR1_SQ_OFFSET (0) #else # define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ # define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) @@ -597,6 +626,9 @@ # define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ # define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) # define ADC_SQR1_RESERVED (0xff000000) +# define ADC_SQR1_FIRST (25) +# define ADC_SQR1_LAST (28) +# define ADC_SQR1_SQ_OFFSET (0) #endif /* ADC regular sequence register 2 */ @@ -615,6 +647,9 @@ # define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ # define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) # define ADC_SQR2_RESERVED (0xc0000000) +# define ADC_SQR2_FIRST (7) +# define ADC_SQR2_LAST (12) +# define ADC_SQR2_SQ_OFFSET (0) #else # define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ # define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) @@ -629,6 +664,9 @@ # define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ # define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) # define ADC_SQR2_RESERVED (0xc0000000) +# define ADC_SQR2_FIRST (19) +# define ADC_SQR2_LAST (24) +# define ADC_SQR2_SQ_OFFSET (0) #endif /* ADC regular sequence register 3 */ @@ -647,6 +685,9 @@ # define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ # define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) # define ADC_SQR3_RESERVED (0xc0000000) +# define ADC_SQR3_FIRST (1) +# define ADC_SQR3_LAST (6) +# define ADC_SQR3_SQ_OFFSET (0) #else # define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ # define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) @@ -661,6 +702,9 @@ # define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ # define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) # define ADC_SQR3_RESERVED (0xc0000000) +# define ADC_SQR3_FIRST (13) +# define ADC_SQR3_LAST (18) +# define ADC_SQR3_SQ_OFFSET (0) #endif /* ADC regular sequence register 4 */ @@ -679,6 +723,9 @@ # define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ # define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) # define ADC_SQR4_RESERVED (0xc0000000) +# define ADC_SQR4_FIRST (7) +# define ADC_SQR4_LAST (12) +# define ADC_SQR4_SQ_OFFSET (0) #endif /* ADC regular sequence register 5 */ @@ -697,8 +744,15 @@ # define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ # define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) # define ADC_SQR5_RESERVED (0xc0000000) +# define ADC_SQR5_FIRST (1) +# define ADC_SQR5_LAST (6) +# define ADC_SQR5_SQ_OFFSET (0) #endif +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + /* ADC injected sequence register */ #define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ @@ -714,15 +768,15 @@ /* ADC injected data register 1-4 */ -#define ADC_JDR_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_MASK (0xffff << ADC_JDR_SHIFT) +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) /* ADC regular data register */ -#define ADC_DR_DATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_DATA_MASK (0xffff << ADC_DR_DATA_SHIFT) +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) -#ifndef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_STM32F10XX # define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ # define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) #endif @@ -784,7 +838,7 @@ /* Bits 5-7: Reserved, must be kept at reset value. */ # define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ # define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((5)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ /* Bit 12 Reserved, must be kept at reset value. */ # define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h index 638acf7486..5763260eb9 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h @@ -210,7 +210,7 @@ #define STM32_ADC34_CDR (STM32_ADC34_BASE+STM32_ADC_CDR_OFFSET) /* Register Bitfield Definitions ********************************************************************/ -/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ +/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ #define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ #define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ @@ -242,7 +242,8 @@ /* ADC configuration register */ -#define ADC_CFGR_DMACFG (1 << 1) /* Bit 0: Direct memory access configuration */ +#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ #define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ #define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT) # define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */ @@ -252,7 +253,34 @@ #define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */ #define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ #define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */ +# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T4CC4 (5 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ +# define ADC12_CFGR_EXTSEL_T8TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T3CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2CC3 (1 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T8CC1 (3 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T8TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T20TRGO (5 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T4CC1 (6 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T3TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T7TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2CC1 (15 << ADC_CFGR_EXTSEL_SHIFT) #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ #define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) # define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ @@ -285,7 +313,7 @@ #define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ #define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ #define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ -#define ADC_SMPR_2601p5 7 /* 111: 601.5 cycles */ +#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ #define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ #define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) @@ -348,6 +376,10 @@ #define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ #define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (6) + /* ADC regular sequence register 1 */ #define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ @@ -360,6 +392,10 @@ #define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) #define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) +#define ADC_SQR1_RESERVED (0xe0820830) +#define ADC_SQR1_FIRST (1) +#define ADC_SQR1_LAST (4) +#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) /* ADC regular sequence register 2 */ @@ -372,7 +408,11 @@ #define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) #define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT ) +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_RESERVED (0xe0820820) +#define ADC_SQR2_FIRST (5) +#define ADC_SQR2_LAST (9) +#define ADC_SQR2_SQ_OFFSET (0) /* ADC regular sequence register 3 */ @@ -385,18 +425,27 @@ #define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) #define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT ) +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_RESERVED (0xe0820820) +#define ADC_SQR3_FIRST (10) +#define ADC_SQR3_LAST (14) +#define ADC_SQR3_SQ_OFFSET (0) /* ADC regular sequence register 4 */ -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 14th conversion in regular sequence */ +#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 15th conversion in regular sequence */ +#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) +#define ADC_SQR4_RESERVED (0xfffff820) +#define ADC_SQR4_FIRST (15) +#define ADC_SQR4_LAST (16) +#define ADC_SQR4_SQ_OFFSET (0) /* ADC regular data register */ -#define ADC_DR_MASK (0xffff) +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) /* ADC injected sequence register */ @@ -405,7 +454,34 @@ # define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ #define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ #define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT) /* Event = 0..15 */ +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ # define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) # define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ @@ -437,96 +513,97 @@ /* ADC injected data register 1, 2, 3, and 4 */ -#define ADC_JDR_MASK (0xffff) +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) /* ADC analog watchdog 2 configuration register */ -#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) +# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC analog watchdog 3 configuration register */ -#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) +# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC differential mode selection register 2 */ #define ADC_DIFSEL_ -#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) +# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC calibration factors */ -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) +#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ +#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) +#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ +#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) /* Common status register */ -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ +#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ +#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ +#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ +#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ +#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ +#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ +#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ +#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ +#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ +#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ +#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ +#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ +#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ +#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ +#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ +#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ +#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ +#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ +#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ +#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ +#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ /* Common control register */ -#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ -#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) -# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ -# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ -# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ -# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ -# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ -# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ -# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ -# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ -#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ -#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) -# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ -# define ADC_CCR_MDMA_ 10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ -# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ -#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ -#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) -# define ADC_CCR_CKMODE_ASYCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ -# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ -# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ -# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ +#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ +#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) +# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ +# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ +# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ +# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ +# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ +# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ +# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ +# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ +#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ +#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) +# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ +# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ +# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ +#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ +#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) +# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ +# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ +# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ +# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ /* Common regular data register for dual mode */ -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) +#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ +#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) +#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ +#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) /**************************************************************************************************** * Public Types diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h index a12151fd8f..38ae3f0c36 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h @@ -68,6 +68,59 @@ * pins in this file. */ +/* ADC */ + +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4) +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13) + +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_ADC12_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC12_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC12_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC12_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC12_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2) + +#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) +#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13) +#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10) +#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11) +#define GPIO_ADC3_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12) + +#define GPIO_ADC4_IN1 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14) +#define GPIO_ADC4_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15) +#define GPIO_ADC4_IN3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ADC4_IN4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_ADC4_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) +#define GPIO_ADC4_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8) +#define GPIO_ADC4_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9) + +#define GPIO_ADC34_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8) +#define GPIO_ADC34_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10) +#define GPIO_ADC34_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11) +#define GPIO_ADC34_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12) +#define GPIO_ADC34_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13) +#define GPIO_ADC34_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14) + /* CAN */ #define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) @@ -603,4 +656,3 @@ #define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10) #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H */ - diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index a2ad492f0d..514e707cf3 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -2,8 +2,10 @@ * arch/arm/src/stm32/stm32_adc.c * * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Diego Sanchez + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -71,12 +73,13 @@ /* Some ADC peripheral must be enabled */ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) /* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) /* At the moment there is no proper implementation for timers external * trigger in STM32L15XX May be added latter @@ -89,21 +92,80 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* RCC reset ****************************************************************/ + +#if defined(CONFIG_STM32_STM32F10XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST +# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADC4RST +#elif defined(CONFIG_STM32_STM32F30XX) +# define STM32_RCC_RSTR STM32_RCC_AHBRSTR +# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST +# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADCRST +#elif defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +#endif + /* ADC interrupts ***********************************************************/ -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_SR_ALLINTS (ADC_SR_AWD | ADC_SR_EOC | ADC_SR_JEOC) +#ifdef CONFIG_STM32_STM32F30XX +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET +# define ADC_DMAREG_DMA ADC_CFGR_DMAEN +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR_EXTSEL_MASK +# define ADC_EXTREG_EXTEN_MASK ADC_CFGR_EXTEN_MASK +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING +# define ADC_ISR_EOC ADC_INT_EOC +# define ADC_IER_EOC ADC_INT_EOC +# define ADC_ISR_AWD ADC_INT_AWD1 +# define ADC_IER_AWD ADC_INT_AWD1 +# define ADC_ISR_JEOC ADC_INT_JEOC +# define ADC_IER_JEOC ADC_INT_JEOC +# define ADC_ISR_OVR ADC_INT_OVR +# define ADC_IER_OVR ADC_INT_OVR #else -# define ADC_SR_ALLINTS (ADC_SR_AWD | ADC_SR_EOC | ADC_SR_JEOC | \ - ADC_SR_OVR) +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_DMAREG_DMA ADC_CR2_DMA +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK +# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET +# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET +# define ADC_ISR_EOC ADC_SR_EOC +# define ADC_IER_EOC ADC_CR1_EOCIE +# define ADC_ISR_AWD ADC_SR_AWD +# define ADC_IER_AWD ADC_CR1_AWDIE +# define ADC_ISR_JEOC ADC_SR_JEOC +# define ADC_IER_JEOC ADC_CR1_JEOCIE +# ifdef CONFIG_STM32_STM32F10XX +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG +# define ADC_EXTREG_EXTEN_NONE 0 +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG +# define ADC_ISR_OVR 0 +# define ADC_IER_OVR 0 +# else +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK +# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING +# define ADC_ISR_OVR ADC_SR_OVR +# define ADC_IER_OVR ADC_CR1_OVRIE +# endif #endif -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) -#else -# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE | \ - ADC_CR1_OVRIE) -#endif +#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ + ADC_ISR_OVR) +#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ + ADC_IER_OVR) /* ADC Channels/DMA ********************************************************/ /* The maximum number of channels that can be sampled. If DMA support is @@ -122,17 +184,70 @@ /* DMA channels and interface values differ for the F1 and F4 families */ -#if defined(CONFIG_STM32_STM32L15XX) -# define ADC_CHANNELS_NUMBER 32 -# define ADC_DEFAULT_SAMPLE 0x7 -#endif - -/* This can be refined or defined in Kconfig */ - -#ifndef CONFIG_ADC_TOTAL_CHANNELS -# define ADC_MAX_CHANNELS ADC_MAX_SAMPLES -#else -# define ADC_MAX_CHANNELS CONFIG_ADC_TOTAL_CHANNELS +#if defined(CONFIG_STM32_STM32F10XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_55p5 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_112 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32L15XX) +# define ADC_CHANNELS_NUMBER 32 +# define ADC_SMPR_DEFAULT ADC_SMPR_384 #endif /**************************************************************************** @@ -149,10 +264,10 @@ struct stm32_dev_s uint8_t intf; /* ADC interface number */ uint8_t current; /* Current ADC channel being converted */ #ifdef ADC_HAVE_DMA - uint8_t dmachan; /* DMA channel needed by this ADC */ - bool hasdma; /* True: This channel supports DMA */ + uint8_t dmachan; /* DMA channel needed by this ADC */ + bool hasdma; /* True: This channel supports DMA */ #endif -#if defined(CONFIG_STM32_STM32L15XX) +#ifdef CONFIG_STM32_STM32L15XX /* Sample time selection. These bits must be written only when ADON=0 */ uint8_t sample_rate[ADC_CHANNELS_NUMBER]; @@ -161,7 +276,7 @@ struct stm32_dev_s uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, * 3=CC4, 4=TRGO */ #endif - xcpt_t isr; /* Interrupt handler for this ADC block */ + xcpt_t isr; /* Interrupt handler for this ADC block */ uint32_t base; /* Base address of registers unique to this ADC * block */ #ifdef ADC_HAVE_TIMER @@ -189,31 +304,48 @@ struct stm32_dev_s /* ADC Register access */ -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); -static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value); +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits); +#endif +static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset); +static void adc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value); +static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); #ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); -static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value); -static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg); +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset); +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +static void tim_dumpregs(FAR struct stm32_dev_s *priv, + FAR const char *msg); #endif -static void adc_rccreset(struct stm32_dev_s *priv, bool reset); +static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ static int adc_interrupt(FAR struct adc_dev_s *dev); -#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || \ - defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context); +#ifdef CONFIG_STM32_STM32L15XX +static int adc1_interrupt(int irq, FAR void *context); #endif -#if defined(CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, void *context); +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, FAR void *context); +#endif +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3) +static int adc3_interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, FAR void *context); #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int adc123_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_STM32_STM32L15XX -static int adc_stm32l_interrupt(int irq, void *context); +static int adc123_interrupt(int irq, FAR void *context); #endif /* ADC Driver Methods */ @@ -224,24 +356,26 @@ static void adc_shutdown(FAR struct adc_dev_s *dev); static void adc_rxint(FAR struct adc_dev_s *dev, bool enable); static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); static void adc_enable(FAR struct stm32_dev_s *priv, bool enable); -static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); -static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx); + +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, + int offset); +static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); + #ifdef CONFIG_STM32_STM32L15XX - static void adc_power_down_idle(FAR struct stm32_dev_s *priv, - bool pdi_high); - static void adc_power_down_delay(FAR struct stm32_dev_s *priv, - bool pdd_high); - static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, - uint32_t delay); - static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, - bool chb_selected); - static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, - bool arg); +static void adc_power_down_idle(FAR struct stm32_dev_s *priv, + bool pdi_high); +static void adc_power_down_delay(FAR struct stm32_dev_s *priv, + bool pdd_high); +static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, + uint32_t delay); +static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, + bool chb_selected); +static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, + bool arg); +#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI +static void adc_enable_hsi(bool enable); +static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev); #endif -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) - static void adc_enable_hsi(bool enable); - static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev); #endif #ifdef ADC_HAVE_TIMER @@ -249,11 +383,13 @@ static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable); static int adc_timinit(FAR struct stm32_dev_s *priv); #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) -static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); +#ifdef ADC_HAVE_DMA +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + FAR void *arg); #endif +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -262,8 +398,8 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); static const struct adc_ops_s g_adcops = { -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) .ao_reset = adc_reset_hsi_disable, #else .ao_reset = adc_reset, @@ -279,23 +415,18 @@ static const struct adc_ops_s g_adcops = #ifdef CONFIG_STM32_ADC1 static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #elif defined(CONFIG_STM32_STM32L15XX) .irq = STM32_IRQ_ADC1, - .isr = adc_stm32l_interrupt, + .isr = adc1_interrupt, #else .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, #endif .intf = 1, -#ifndef CONFIG_STM32_STM32L15XX .base = STM32_ADC1_BASE, -#else - .base = STM32_ADC_BASE, -#endif - #ifdef ADC1_HAVE_TIMER .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, @@ -321,7 +452,7 @@ static struct adc_dev_s g_adcdev1 = #ifdef CONFIG_STM32_ADC2 static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #else @@ -355,7 +486,7 @@ static struct adc_dev_s g_adcdev2 = #ifdef CONFIG_STM32_ADC3 static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, #else @@ -387,7 +518,30 @@ static struct adc_dev_s g_adcdev3 = /* ADC4 state */ #ifdef CONFIG_STM32_ADC4 -# error Missing ADC4 implementation +static struct stm32_dev_s g_adcpriv4 = +{ + .irq = STM32_IRQ_ADC4, + .isr = adc4_interrupt, + .intf = 4, + .base = STM32_ADC4_BASE, +#ifdef ADC4_HAVE_TIMER + .trigger = CONFIG_STM32_ADC4_TIMTRIG, + .tbase = ADC4_TIMER_BASE, + .extsel = ADC4_EXTSEL_VALUE, + .pclck = ADC4_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC4_SAMPLE_FREQUENCY, +#endif +#ifdef ADC4_HAVE_DMA + .dmachan = ADC4_DMA_CHAN, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_adcdev4 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv4, +}; #endif /**************************************************************************** @@ -395,23 +549,29 @@ static struct adc_dev_s g_adcdev3 = ****************************************************************************/ /**************************************************************************** - * Name: adc_getreg + * Name: stm32_modifyreg32 * * Description: - * Read the value of an ADC register. + * Modify the value of a 32-bit register (not atomic). * * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read + * addr - The address of the register + * clrbits - The bits to clear + * setbits - The bits to set * * Returned Value: + * None * ****************************************************************************/ -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits) { - return getreg32(priv->base + offset); + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); } +#endif /**************************************************************************** * Name: adc_getreg @@ -420,18 +580,64 @@ static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) * Read the value of an ADC register. * * Input Parameters: - * priv - A reference to the ADC block status + * priv - A reference to the ADC block status * offset - The offset to the register to read * * Returned Value: + * The current contents of the specified register * ****************************************************************************/ -static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) +static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: adc_putreg + * + * Description: + * Write a value to an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value) { putreg32(value, priv->base + offset); } +/**************************************************************************** + * Name: adc_modifyreg + * + * Description: + * Modify the value of an ADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); +} + /**************************************************************************** * Name: tim_getreg * @@ -439,7 +645,7 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) * Read the value of an ADC timer register. * * Input Parameters: - * priv - A reference to the ADC block status + * priv - A reference to the ADC block status * offset - The offset to the register to read * * Returned Value: @@ -448,7 +654,7 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset) { return getreg16(priv->tbase + offset); } @@ -458,11 +664,12 @@ static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) * Name: tim_putreg * * Description: - * Read the value of an ADC timer register. + * Write a value to an ADC timer register. * * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register * * Returned Value: * None @@ -470,14 +677,40 @@ static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value) +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value) { putreg16(value, priv->tbase + offset); } #endif /**************************************************************************** - * Name: adc_tim_dumpregs + * Name: tim_modifyreg + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef ADC_HAVE_TIMER +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} +#endif + +/**************************************************************************** + * Name: tim_dumpregs * * Description: * Dump all timer registers. @@ -491,9 +724,8 @@ static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) +static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) { -#if defined(CONFIG_DEBUG_ANALOG) && defined(CONFIG_DEBUG_VERBOSE) avdbg("%s:\n", msg); avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", tim_getreg(priv, STM32_GTIM_CR1_OFFSET), @@ -514,7 +746,7 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -# ifndef CONFIG_STM32_STM32L15XX +#ifndef CONFIG_STM32_STM32L15XX if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -529,7 +761,6 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_GTIM_DCR_OFFSET), tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } -# endif #endif } #endif @@ -549,28 +780,22 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void adc_timstart(struct stm32_dev_s *priv, bool enable) +static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable) { - uint16_t regval; - - avdbg("enable: %d\n", enable); - regval = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); + avdbg("enable: %d\n", enable ? 1 : 0); if (enable) { /* Start the counter */ - regval |= ATIM_CR1_CEN; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } - else { /* Disable the counter */ - regval &= ~ATIM_CR1_CEN; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } - - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, regval); } #endif @@ -578,8 +803,8 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) * Name: adc_timinit * * Description: - * Initialize the timer that drivers the ADC sampling for this channel using - * the pre-calculated timer divider definitions. + * Initialize the timer that drivers the ADC sampling for this channel + * using the pre-calculated timer divider definitions. * * Input Parameters: * priv - A reference to the ADC block status @@ -597,6 +822,8 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) uint32_t regval; uint32_t timclk; + uint16_t clrbits = 0; + uint16_t setbits = 0; uint16_t cr1; uint16_t cr2; uint16_t ccmr1; @@ -607,45 +834,30 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) uint16_t ccer; uint16_t egr; - avdbg("Initializing timers extsel = 0x%08X\n", priv->extsel); - /* If the timer base address is zero, then this ADC was not configured to * use a timer. */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - -#ifdef CONFIG_STM32_STM32F10XX - if (!priv->tbase) + if (priv->tbase == 0) { - /* Configure the ADC to use the selected timer and timer channel as - * the trigger EXTTRIG: External Trigger Conversion mode for regular - * channels DISABLE - */ - - regval &= ~ADC_CR2_EXTTRIG; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); - return OK; + return ERROR; } - else - { - regval |= ADC_CR2_EXTTRIG; - } -#endif /* EXTSEL selection: These bits select the external event used to trigger * the start of conversion of a regular group. NOTE: * * - The position with of the EXTSEL field varies from one STM32 MCU * to another. - * - The width of the EXTSEL field varies from one STM3 MCU to another. + * - The width of the EXTSEL field varies from one STM32 MCU to another. * - The value in priv->extsel is already shifted into the correct bit * position. */ - regval &= ~ADC_CR2_EXTSEL_MASK; - regval |= priv->extsel; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel); + + adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, + ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK, + ADC_EXTREG_EXTEN_DEFAULT | priv->extsel); /* Configure the timer channel to drive the ADC */ @@ -700,28 +912,24 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) reload = 65535; } - /* Set up the timer CR1 register */ - - cr1 = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); - /* Disable the timer until we get it configured */ adc_timstart(priv, false); - /* Select the Counter Mode == count up: + /* Set up the timer CR1 register. + * + * Select the Counter Mode == count up: * * ATIM_CR1_EDGE: The counter counts up or down depending on the * direction bit(DIR). * ATIM_CR1_DIR: 0: count up, 1: count down + * + * Set the clock division to zero for all */ - cr1 &= ~(ATIM_CR1_DIR | ATIM_CR1_CMS_MASK); - cr1 |= ATIM_CR1_EDGE; - - /* Set the clock division to zero for all */ - - cr1 &= ~GTIM_CR1_CKD_MASK; - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; + setbits = GTIM_CR1_EDGE; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ @@ -740,14 +948,14 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ ocmode1 = 0; ocmode2 = 0; - switch (priv->trigger) + switch (priv->trigger) { case 0: /* TimerX CC1 event */ { @@ -760,7 +968,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC1G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } @@ -777,7 +987,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC2G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } @@ -794,7 +1006,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC3G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } @@ -811,7 +1025,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC4G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } @@ -825,7 +1041,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccenable = 0; egr = GTIM_EGR_TG; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } @@ -848,7 +1066,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); - /* Reset the Output Compare Mode Bits and set the select output compare mode */ + /* Reset the Output Compare Mode Bits and set the select output compare + * mode + */ ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); @@ -857,41 +1077,54 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccmr1 |= ocmode1; ccmr2 |= ocmode2; - /* Reset the output polarity level of all channels (selects high polarity) */ + /* Reset the output polarity level of all channels (selects high + * polarity) + */ - ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P); + ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | + ATIM_CCER_CC3P | ATIM_CCER_CC4P); /* Enable the output state of the selected channel (only) */ - ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E); + ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | + ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; #ifndef CONFIG_STM32_STM32L15XX - if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); +# if defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | + ATIM_CCER_CC4NP); # else - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); # endif - /* Reset the output compare and output compare N IDLE State */ + /* Reset the output compare and output compare N IDLE State */ - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | - ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4); - } -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - else - { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); - } + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | + ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | + ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | + ATIM_CR2_OIS4); + } +# if defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) + else + { + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + } # endif #else @@ -905,8 +1138,11 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. */ - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); + + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | + ATIM_CCER_CC4NP); } #endif @@ -920,17 +1156,13 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Set the ARR Preload Bit */ - cr1 = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_ARPE; - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); - /* Enable the timer counter - * All but the CEN bit with the default config in CR1 - */ + /* Enable the timer counter */ adc_timstart(priv, true); - adc_tim_dumpregs(priv, "After starting Timers"); + tim_dumpregs(priv, "After starting timers"); return OK; } @@ -940,7 +1172,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * Name: adc_startconv * * Description: - * Start (or stop) the ADC conversion process in DMA mode + * Start (or stop) the ADC conversion process * * Input Parameters: * priv - A reference to the ADC block status @@ -950,46 +1182,74 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) -static void adc_startconv(struct stm32_dev_s *priv, bool enable) +#if defined(CONFIG_STM32_STM32F10XX) +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + avdbg("enable: %d\n", enable ? 1 : 0); + + if (!enable) + { + /* Clear ADON to stop the conversion and put the ADC in the + * power down state. + */ + + adc_enable(priv, false); + } + + /* If the ADC is already on, set ADON again to start the conversion. + * Otherwise, set ADON once to wake up the ADC from the power down state. + */ + + adc_enable(priv, true); +} +#elif defined(CONFIG_STM32_STM32F30XX) +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; - avdbg("enable: %d\n", enable); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + avdbg("enable: %d\n", enable ? 1 : 0); if (enable) { -#ifdef CONFIG_ADC_CONTINUOUS + /* Start the conversion of regular channels */ - /* Set continuous mode */ - - regval |= ADC_CR2_CONT; - -#endif - - /* Start conversion of regular channels */ - - regval |= ADC_CR2_SWSTART; + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); } else { -#ifdef CONFIG_ADC_CONTINUOUS + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - /* Disable the continuous conversion */ + /* Is a conversion ongoing? */ - regval &= ~ADC_CR2_CONT; + if ((regval & ADC_CR_ADSTART) != 0) + { + /* Stop the conversion */ -#endif + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); - /* Disable the conversion of regular channels */ + /* Wait for the conversion to stop */ - regval &= ~ADC_CR2_SWSTART; + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADSTP) != 0); + } } +} +#else +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + avdbg("enable: %d\n", enable ? 1 : 0); - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_SWSTART); + } + else + { + /* Stop the conversion */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0); + } } #endif @@ -1008,73 +1268,59 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset) { - irqstate_t flags; - uint32_t regval; uint32_t adcbit; - /* Pick the appropriate bit in the APB2 reset register */ - -#ifdef CONFIG_STM32_STM32F10XX - /* For the STM32 F1, there is an individual bit to reset each ADC. */ + /* Pick the appropriate bit in the APB2 reset register. + * For the STM32 F1, there is an individual bit to reset each ADC, + * but for the STM32 F2/F4, there is one common reset for all ADCs. + * THIS will probably cause some problems! + */ switch (priv->intf) { #ifdef CONFIG_STM32_ADC1 case 1: - adcbit = RCC_APB2RSTR_ADC1RST; + adcbit = RCC_RSTR_ADC1RST; break; #endif #ifdef CONFIG_STM32_ADC2 case 2: - adcbit = RCC_APB2RSTR_ADC2RST; + adcbit = RCC_RSTR_ADC2RST; break; #endif #ifdef CONFIG_STM32_ADC3 case 3: - adcbit = RCC_APB2RSTR_ADC3RST; + adcbit = RCC_RSTR_ADC3RST; + break; +#endif +#ifdef CONFIG_STM32_ADC4 + case 4: + adcbit = RCC_RSTR_ADC4RST; break; #endif default: return; } -#elif defined(CONFIG_STM32_STM32L15XX) - adcbit = RCC_APB2RSTR_ADC1RST; - -#else - /* For the STM32 F4, there is one common reset for all ADC block. - * THIS will probably cause some problems! + /* Set or clear the selected bit in the APB2 reset register. + * modifyreg32() disables interrupts. Disabling interrupts is necessary + * because the APB2RTSR register is used by several different drivers. */ - adcbit = RCC_APB2RSTR_ADCRST; -#endif - - /* Disable interrupts. This is necessary because the APB2RTSR register - * is used by several different drivers. - */ - - flags = irqsave(); - - /* Set or clear the selected bit in the APB2 reset register */ - - regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { - /* Enable ADC reset state */ + /* Enable ADC reset state */ - regval |= adcbit; + modifyreg32(STM32_RCC_RSTR, 0, adcbit); } else { /* Release ADC from reset state */ - regval &= ~adcbit; + modifyreg32(STM32_RCC_RSTR, adcbit, 0); } - - putreg32(regval, STM32_RCC_APB2RSTR); - irqrestore(flags); } /**************************************************************************** @@ -1096,13 +1342,13 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) #ifdef CONFIG_STM32_STM32L15XX static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high) { - uint32_t regval = 0; + uint32_t regval; - avdbg("PDI: %d\n", (pdi_high ? 1 : 0)); + avdbg("PDI: %d\n", pdi_high ? 1 : 0); regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - if (!(STM32_ADC1_CR2 & ADC_CR2_ADON)) + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) { if (pdi_high) { @@ -1137,13 +1383,13 @@ static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high) #ifdef CONFIG_STM32_STM32L15XX static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high) { - uint32_t regval = 0; + uint32_t regval; - avdbg("PDD: %d\n", (pdd_high ? 1 : 0)); + avdbg("PDD: %d\n", pdd_high ? 1 : 0); regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - if (!(STM32_ADC1_CR2 & ADC_CR2_ADON)) + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) { if (pdd_high) { @@ -1179,14 +1425,9 @@ static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high) static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, uint32_t delay) { - uint32_t regval; + avdbg("Delay selected: 0x%08x\n", delay); - avdbg("Delay selected: 0x%08X\n", delay); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_DELS_MASK; - regval |= delay; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay); } #endif @@ -1207,24 +1448,19 @@ static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, bool chb_selected) +static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, + bool chb_selected) { - uint32_t regval; - - avdbg("Bank of channels selected: %c\n", (chb_selected ? 'B' : 'A')); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + avdbg("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A'); if (chb_selected) { - regval |= ADC_CR2_CFG; + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CFG); } else { - regval &= ~ADC_CR2_CFG; + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_CFG, 0); } - - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); } #endif @@ -1244,42 +1480,61 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, bool chb_selected) * ****************************************************************************/ +#ifdef CONFIG_STM32_STM32F30XX static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; - avdbg("enable: %d\n", (enable ? 1 : 0)); + avdbg("enable: %d\n", enable ? 1 : 0); - /* Not all STM32 parts prove the SR ADONS bit */ + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); -#ifdef ADC_SR_ADONS - regval = adc_getreg(priv, STM32_ADC_SR_OFFSET); - - if (!(regval & ADC_SR_ADONS) && enable) - { - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_ADON; - } - else if ((regval & ADC_SR_ADONS) && !enable) - { - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_ADON; - } - -#else - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); if (enable) { - regval |= ADC_CR2_ADON; + /* Enable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); + + /* Wait for the ADC to be ready */ + + while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); } - else + else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) { - regval &= ~ADC_CR2_ADON; + /* Stop ongoing conversions */ + + adc_startconv(priv, false); + + /* Disable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); + + /* Wait for the ADC to be disabled */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); } +} +#else +static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) +{ +#ifdef ADC_SR_ADONS + bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0; +#else + bool enabled = false; #endif - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + avdbg("enable: %d\n", enable ? 1 : 0); + + if (!enabled && enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); + } + else if (enabled && !enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); + } } +#endif /**************************************************************************** * Name: adc_write_sample_time_registers @@ -1299,7 +1554,8 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t value = 0; - uint8_t i, shift; + uint8_t i; + uint8_t shift; /* Sampling time individually for each channel * 000: 4 cycles @@ -1367,11 +1623,10 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) ****************************************************************************/ #ifdef ADC_HAVE_DMA -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) { - FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; - FAR struct stm32_dev_s *priv = dev->ad_priv; - uint32_t regval; + FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int i; for (i = 0; i < priv->nchannels; i++) @@ -1388,12 +1643,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) /* Restart DMA for the next conversion series */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_DMA; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); - - regval |= ADC_CR2_DMA; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); } #endif @@ -1414,21 +1665,32 @@ static void adc_reset(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; irqstate_t flags; - uint32_t regval; + uint32_t clrbits; + uint32_t setbits; #ifdef ADC_HAVE_TIMER int ret; #endif - allvdbg("intf: ADC%d\n", priv->intf); + allvdbg("intf: %d\n", priv->intf); flags = irqsave(); - /* In STM32L15XX family HSI used as an independent clock-source for the ADC */ +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) + /* The STM32L15XX family uses HSI as an independent clock-source + * for the ADC + */ adc_enable_hsi(true); +#endif + +#ifdef CONFIG_STM32_STM32F30XX + + /* Turn off the ADC so we can write the RCC bits */ + + adc_enable(priv, false); + #endif /* Enable ADC reset state */ @@ -1439,7 +1701,39 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_rccreset(priv, false); - /* Initialize the ADC data structures */ +#ifdef CONFIG_STM32_STM32F30XX + + /* Set voltage regular enable to intermediate state */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_INTER); + + /* Enable the ADC voltage regulator */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_ENABLED); + + /* Wait for the ADC voltage regulator to startup */ + + up_udelay(10); + +#if 0 /* Doesn't work */ + + /* Calibrate the ADC */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL); + + /* Wait for the calibration to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); + +#endif + + /* Initialize the watchdog 1 threshold register */ + + adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000); + +#else /* Initialize the watchdog high threshold register */ @@ -1449,67 +1743,105 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000); - /* Initialize the same sample time for each ADC 55.5 cycles - * +#endif + + /* Initialize the same sample time for each ADC. * During sample cycles channel selection bits must remain unchanged. - * For F-family only - * - * 000: 1.5 cycles - * 001: 7.5 cycles - * 010: 13.5 cycles - * 011: 28.5 cycles - * 100: 41.5 cycles - * 101: 55.5 cycles - * 110: 71.5 cycles - * 111: 239.5 cycles */ -#ifndef CONFIG_STM32_STM32L15XX - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); -#else +#ifdef CONFIG_STM32_STM32L15XX adc_write_sample_time_registers(dev); +#else + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); #endif - /* ADC CR1 Configuration */ +#ifdef CONFIG_STM32_STM32F30XX - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); + /* Enable the analog watchdog */ - /* Set mode configuration (Independent mode) */ + clrbits = ADC_CFGR_AWD1CH_MASK; + setbits = ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | + (priv->chanlist[0] << ADC_CFGR_AWD1CH_SHIFT); -#ifdef CONFIG_STM32_STM32F10XX - regval |= ADC_CR1_IND; -#endif + /* Set the resolution of the conversion */ - /* Initialize the Analog watchdog enable */ - - regval |= ADC_CR1_AWDEN; - regval |= (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT); - - /* Enable interrupt flags */ - - regval |= ADC_CR1_ALLINTS; + clrbits |= ADC_CFGR_RES_MASK; + setbits |= ADC_CFGR_RES_12BIT; #ifdef ADC_HAVE_DMA if (priv->hasdma) { - regval |= ADC_CR1_SCAN; + /* Set DMA one shot mode */ + + clrbits |= ADC_CFGR_DMACFG; + + /* Enable DMA */ + + setbits |= ADC_CFGR_DMAEN; } #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) + /* Disable continuous mode and set align to right */ - /* Enable or disable Overrun interrupt */ + clrbits |= ADC_CFGR_CONT | ADC_CFGR_ALIGN; - regval &= ~ADC_CR1_OVRIE; + /* Disable external trigger for regular channels */ + + clrbits |= ADC_CFGR_EXTEN_MASK; + setbits |= ADC_CFGR_EXTEN_NONE; + + /* Set CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); + + /* Enable interrupt flags, but disable overrun interrupt */ + + clrbits = ADC_IER_OVR; + setbits = ADC_IER_ALLINTS & ~ADC_IER_OVR; + + /* Set IER configuration */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); + +#else + + /* Enable the analog watchdog */ + + clrbits = ADC_CR1_AWDCH_MASK; + setbits = ADC_CR1_AWDEN | (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT); + +#ifdef CONFIG_STM32_STM32F10XX + + /* Set independent mode */ + + clrbits |= ADC_CR1_DUALMOD_MASK; + setbits |= ADC_CR1_IND; + +#else /* Set the resolution of the conversion */ - regval |= ADC_CR1_RES_12BIT; + clrbits |= ADC_CR1_RES_MASK; + setbits |= ADC_CR1_RES_12BIT; + #endif - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); +#ifdef ADC_HAVE_DMA + if (priv->hasdma) + { + setbits |= ADC_CR1_SCAN; + } +#endif + + /* Enable interrupt flags, but disable overrun interrupt */ + + clrbits |= ADC_IER_OVR; + setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR; + + /* Set CR1 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); #ifdef CONFIG_STM32_STM32L15XX @@ -1517,9 +1849,6 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_power_down_idle(priv, false); adc_power_down_delay(priv, false); -#endif - -#ifdef CONFIG_STM32_STM32L15XX /* Select the bank of channels A */ @@ -1528,85 +1857,70 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* Delay until the converted data has been read */ adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD); + #endif - /* ADC CR2 Configuration */ + /* Disable continuous mode and set align to right */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN; + setbits = 0; - /* Clear CONT, continuous mode disable */ + /* Disable external trigger for regular channels */ - regval &= ~ADC_CR2_CONT; - - /* Set ALIGN (Right = 0) */ - - regval &= ~ADC_CR2_ALIGN; - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - /* External trigger enable for regular channels */ - - regval |= ADC_CR2_EXTEN_NONE; -#endif + clrbits |= ADC_EXTREG_EXTEN_MASK; + setbits |= ADC_EXTREG_EXTEN_NONE; #ifdef ADC_HAVE_DMA if (priv->hasdma) { - regval |= ADC_CR2_DMA; + setbits |= ADC_CR2_DMA; } #endif - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + /* Set CR2 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); + +#endif /* Configuration of the channel conversions */ -#if ADC_MAX_SAMPLES == 1 - /* Select on first indexed channel for backward compatibility. */ - - adc_set_ch_idx(dev, 0); -#else adc_set_ch(dev, 0); -#endif /* ADC CCR configuration */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | - ADC_CCR_TSVREFE); - regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | - ADC_CCR_ADCPRE_DIV2); - putreg32(regval, STM32_ADC_CCR); +#if defined(CONFIG_STM32_STM32F30XX) + clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | + ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | + ADC_CCR_TSEN | ADC_CCR_VBATEN; + setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED | + ADC_CCR_CKMODE_ASYNCH; -#elif defined(CONFIG_STM32_STM32L15XX) - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE); - regval |= ADC_CCR_ADCPRE_DIV2; - putreg32(regval, STM32_ADC_CCR); -#endif - - /* Set the number of conversions */ - -#ifdef ADC_HAVE_DMA - if (priv->hasdma) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_DMA); + stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits); } else -#endif { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA); + stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits); } +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE; + setbits = ADC_CCR_ADCPRE_DIV2; - regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT); - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | + ADC_CCR_DMA_MASK | ADC_CCR_VBATE; + setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED; +#endif - /* Set the channel index of the first conversion */ - - priv->current = 0; + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); +#endif #ifdef ADC_HAVE_DMA + /* Enable DMA */ if (priv->hasdma) @@ -1636,52 +1950,72 @@ static void adc_reset(FAR struct adc_dev_s *dev) stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); } + #endif - /* Set ADON to wake up the ADC from Power Down state. */ + /* Set ADON to wake up the ADC from the power down state */ adc_enable(priv, true); #ifdef ADC_HAVE_TIMER - ret = adc_timinit(priv); - if (ret != OK) + if (priv->tbase != 0) { - adbg("Error initializing the timers\n"); + ret = adc_timinit(priv); + if (ret < 0) + { + adbg("adc_timinit failed: %d\n", ret); + } } -#elif !defined(CONFIG_ADC_NO_STARTUP_CONV) - -#ifdef CONFIG_STM32_STM32F10XX - /* Set ADON (Again) to start the conversion. Only if Timers are not - * configured as triggers - */ - - adc_enable(priv, true); -#else - adc_startconv(priv, true); -#endif /* CONFIG_STM32_STM32F10XX */ - -#endif /* ADC_HAVE_TIMER */ +#ifndef CONFIG_ADC_NO_STARTUP_CONV + else +#endif +#endif +#ifndef CONFIG_ADC_NO_STARTUP_CONV + { + adc_startconv(priv, true); + } +#endif irqrestore(flags); +#ifdef CONFIG_STM32_STM32F30XX + avdbg("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); +#else avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), adc_getreg(priv, STM32_ADC_CR1_OFFSET), adc_getreg(priv, STM32_ADC_CR2_OFFSET)); +#endif + avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); -#ifdef CONFIG_STM32_STM32L15XX + +#if defined(CONFIG_STM32_STM32F30XX) + avdbg("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); +#elif defined(CONFIG_STM32_STM32L15XX) avdbg("SQR4: 0x%08x SQR5: 0x%08x\n", - adc_getreg(priv, STM32_ADC_SQR4_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET) adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - avdbg("CCR: 0x%08x\n", - getreg32(STM32_ADC_CCR)); +#if defined(CONFIG_STM32_STM32F30XX) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) + { + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); + } + else + { + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR)); + } +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); #endif } @@ -1700,8 +2034,8 @@ static void adc_reset(FAR struct adc_dev_s *dev) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev) { adc_reset(dev); @@ -1715,8 +2049,8 @@ static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev) * Description: * Configure the ADC. This method is called the first time that the ADC * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching ADC interrupts. Interrupts - * are all disabled upon return. + * This setup includes configuring and attaching ADC interrupts. + * Interrupts are all disabled upon return. * * Input Parameters: * @@ -1732,18 +2066,21 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Attach the ADC interrupt */ ret = irq_attach(priv->irq, priv->isr); - if (ret == OK) + if (ret < 0) { - /* Make sure that the ADC device is in the powered up, reset state */ - - adc_reset(dev); - - /* Enable the ADC interrupt */ - - avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq); - up_enable_irq(priv->irq); + avdbg("irq_attach failed: %d\n", ret); + return ret; } + /* Make sure that the ADC device is in the powered up, reset state */ + + adc_reset(dev); + + /* Enable the ADC interrupt */ + + avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq); + up_enable_irq(priv->irq); + return ret; } @@ -1764,11 +2101,10 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; -#ifdef CONFIG_STM32_STM32L15XX adc_enable(priv, false); -# if (STM32_CFGR_PLLSRC != 0) || (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) - adc_enable_hsi(false); -# endif +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) + adc_enable_hsi(false); #endif /* Disable ADC interrupts and detach the ADC interrupt handler */ @@ -1796,40 +2132,21 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - avdbg("intf: %d enable: %d\n", priv->intf, enable); + avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - -#ifndef CONFIG_STM32_HAVE_ONLY_EOCIE if (enable) { /* Enable the end-of-conversion ADC and analog watchdog interrupts */ - regval |= ADC_CR1_ALLINTS; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_ALLINTS); } -#else - if (enable) - { - - /* Clear all interrupts */ - - regval &= ~ADC_CR1_ALLINTS; - - /* Enable the end-of-conversion ADC interrupt */ - - regval |= ADC_CR1_EOCIE; - } -#endif else { /* Disable all ADC interrupts */ - regval &= ~ADC_CR1_ALLINTS; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } /**************************************************************************** @@ -1840,8 +2157,10 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * * Input Parameters: * dev - pointer to device structure used by the driver - * enable - true: Temperature sensor and V REFINT channel enabled (ch 16 and 17) - * false: Temperature sensor and V REFINT channel disabled (ch 16 and 17) + * enable - true: Temperature sensor and V REFINT channel enabled + * (ch 16 and 17) + * false: Temperature sensor and V REFINT channel disabled + * (ch 16 and 17) * * Returned Value: * None. @@ -1849,23 +2168,19 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, bool enable) +static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, + bool enable) { - uint32_t regval; - - regval = getreg32(STM32_ADC_CCR); - if (enable) { - regval |= ADC_CCR_TSVREFE; + stm32_modifyreg32(STM32_ADC_CCR, 0, ADC_CCR_TSVREFE); } else { - regval &= ~ADC_CCR_TSVREFE; + stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_TSVREFE, 0); } - putreg32(regval, STM32_ADC_CCR); - allvdbg("STM32_ADC_CCR value: 0x%08X\n", getreg32(STM32_ADC_CCR)); + avdbg("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR)); } #endif @@ -1923,7 +2238,7 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, * Name: adc_ioc_enable_awd_int * * Description: - * Turns ON/OFF ADC analog watch-dog interrupt. + * Turns ON/OFF ADC analog watchdog interrupt. * * Input Parameters: * dev - pointer to device structure used by the driver @@ -1937,19 +2252,14 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_AWDIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); } else { - regval &= ~ADC_CR1_AWDIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -1971,19 +2281,14 @@ static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_EOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); } else { - regval &= ~ADC_CR1_EOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2005,19 +2310,14 @@ static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_JEOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_JEOC); } else { - regval &= ~ADC_CR1_JEOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_JEOC, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2039,19 +2339,14 @@ static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_OVRIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); } else { - regval &= ~ADC_CR1_OVRIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2127,12 +2422,11 @@ static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg) #ifdef CONFIG_STM32_STM32L15XX static int adc_ioc_wait_rcnr_zeroed(FAR struct stm32_dev_s *priv) { - int i = 0; - uint32_t regval = 0; + int i; for (i = 0; i < 30000; i++) { - if (!((regval = adc_getreg(priv, STM32_ADC_SR_OFFSET)) & ADC_SR_RCNR)) + if ((adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_RCNR) == 0) { return OK; } @@ -2156,68 +2450,44 @@ static int adc_ioc_wait_rcnr_zeroed(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) static void adc_enable_hsi(bool enable) { - uint32_t regval = 0; - if (enable) { - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_HSION; - putreg32(regval, STM32_RCC_CR); /* Enable the HSI */ + /* Enable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, 0, RCC_CR_HSION); while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0); } else { - regval = getreg32(STM32_RCC_CR); - regval &= ~RCC_CR_HSION; - putreg32(regval, STM32_RCC_CR); /* Disable the HSI */ + /* Disable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, RCC_CR_HSION, 0); } } #endif /**************************************************************************** - * Name: adc_set_ch_idx - * - * Description: - * Set single channel for adc conversion. Channel selected from - * configured channel list by index. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * idx - channel index in configured channel list - * - * Returned Value: - * int - errno - * + * Name: adc_sqrbits ****************************************************************************/ -static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx) +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, + int offset) { - FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - int32_t regval; + uint32_t bits = 0; + int i; - if (idx < priv->cchannels) + for (i = first - 1; + i < priv->nchannels && i < last; + i++, offset += ADC_SQ_OFFSET) { -#ifdef CONFIG_STM32_STM32L15XX - regval = adc_getreg(priv, STM32_ADC_SQR5_OFFSET) & ADC_SQR3_RESERVED; -#else - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; -#endif - regval |= (uint32_t)priv->chanlist[idx]; -#ifdef CONFIG_STM32_STM32L15XX - adc_putreg(priv, STM32_ADC_SQR5_OFFSET, regval); -#else - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); -#endif - return 0; - } - else - { - return -ENODEV; + bits |= (uint32_t)priv->chanlist[i] << offset; } + + return bits; } /**************************************************************************** @@ -2238,105 +2508,48 @@ static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx) static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - int i, ret = 0; + uint32_t bits; + int i; if (ch == 0) { - int offset; - -#ifdef CONFIG_STM32_STM32L15XX + priv->current = 0; priv->nchannels = priv->cchannels; - regval = adc_getreg(priv, STM32_ADC_SQR5_OFFSET) & ADC_SQR5_RESERVED; - for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR5_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR4_OFFSET) & ADC_SQR4_RESERVED; - for (i = 6, offset = 0; i < priv->nchannels && i < 12; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR4_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - for (i = 12, offset = 0; i < priv->nchannels && i < 18; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ADC_SQR2_RESERVED; - for (i = 18, offset = 0; i < priv->nchannels && i < 24; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - for (i = 24, offset = 0; i < priv->nchannels && i < 28; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - -#else - priv->nchannels = priv->cchannels; - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ADC_SQR2_RESERVED; - for (i = 6, offset = 0; i < priv->nchannels && i < 12; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - for (i = 12, offset = 0; i < priv->nchannels && i < 16; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } -#endif } else { - ch = ch - 1; - for (i = 0; i < priv->cchannels; i++) + for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++); + + if (i >= priv->cchannels) { - if ((uint32_t)priv->chanlist[i] == ch) - { - ret = adc_set_ch_idx(dev, i); - if (ret < 0) - { - break; - } - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - regval &= ~(ADC_SQR1_L_MASK); - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); - - priv->current = i; - priv->nchannels = 1; - return ret; - } + return -ENODEV; } - ret = -ENODEV; + priv->current = i; + priv->nchannels = 1; } - return ret; +#ifdef STM32_ADC_SQR5_OFFSET + bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, ADC_SQR5_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits); +#endif + +#ifdef STM32_ADC_SQR4_OFFSET + bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); +#endif + + bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + + bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + + bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT | + adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + + return OK; } /**************************************************************************** @@ -2356,16 +2569,14 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { - FAR struct stm32_dev_s * priv = (FAR struct stm32_dev_s *)dev->ad_priv; + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int ret = OK; switch (cmd) { -#ifdef ADC_HAVE_DMA case ANIOC_TRIGGER: adc_startconv(priv, true); break; -#endif #ifdef CONFIG_STM32_STM32L15XX case IO_ENABLE_TEMPER_VOLT_CH: @@ -2413,10 +2624,10 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) } adc_startconv(priv, true); - break; } + break; -#if (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI case IO_STOP_ADC: adc_enable(priv, false); adc_enable_hsi(false); @@ -2432,9 +2643,9 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) default: adbg("ERROR: Unknown cmd: %d\n", cmd); ret = -ENOTTY; + break; } - UNUSED(priv); return ret; } @@ -2453,37 +2664,40 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) static int adc_interrupt(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t adcsr; - int32_t value; + uint32_t regval; + uint32_t pending; + int32_t data; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } /* Identifies the interruption AWD, OVR or EOC */ - adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET); - if ((adcsr & ADC_SR_AWD) != 0) + if ((regval & ADC_ISR_AWD) != 0) { alldbg("WARNING: Analog Watchdog, Value converted out of range!\n"); } -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - if ((adcsr & ADC_SR_OVR) != 0) + if ((regval & ADC_ISR_OVR) != 0) { alldbg("WARNING: Overrun has occurred!\n"); } -#endif /* EOC: End of conversion */ - if ((adcsr & ADC_SR_EOC) != 0) + if ((regval & ADC_ISR_EOC) != 0) { /* Read the converted value and clear EOC bit * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32_ADC_DR_OFFSET); - value &= ADC_DR_DATA_MASK; + data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; - /* Give the ADC data to the ADC driver. adc_receive accepts 3 + /* Give the ADC data to the ADC driver. adc_receive() accepts 3 * parameters: * * 1) The first is the ADC device instance for this ADC block. @@ -2491,7 +2705,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) * 3) The third is the converted data for the channel. */ - adc_receive(dev, priv->chanlist[priv->current], value); + adc_receive(dev, priv->chanlist[priv->current], data); /* Set the channel number of the next channel that will complete * conversion. @@ -2507,92 +2721,13 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) } } + regval &= ~pending; + adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval); return OK; } /**************************************************************************** - * Name: adc12_interrupt - * - * Description: - * ADC12 interrupt handler for the STM32 F1 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || \ - defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context) -{ - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC1 interrupts */ - -#ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } -#endif - - /* Check for pending ADC2 interrupts */ - -#ifdef CONFIG_STM32_ADC2 - regval = getreg32(STM32_ADC2_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev2); - regval &= ~pending; - putreg32(regval, STM32_ADC2_SR); - } -#endif - return OK; -} -#endif - -/**************************************************************************** - * Name: adc3_interrupt - * - * Description: - * ADC1/2 interrupt handler for the STM32 F1 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined (CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, void *context) -{ - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC3 interrupts */ - - regval = getreg32(STM32_ADC3_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev3); - regval &= ~pending; - putreg32(regval, STM32_ADC3_SR); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc123_interrupt + * Name: adc1_interrupt * * Description: * ADC interrupt handler for the STM32 L15XX family. @@ -2606,24 +2741,82 @@ static int adc3_interrupt(int irq, void *context) ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static int adc_stm32l_interrupt(int irq, void *context) +static int adc1_interrupt(int irq, FAR void *context) { - uint32_t regval; - uint32_t pending; + adc_interrupt(&g_adcdev1); - /* STM32L15XX-family has the only ADC. For the sake of the simplicity the ADC1 - * name is used everywhere - */ + return OK; +} +#endif +/**************************************************************************** + * Name: adc12_interrupt + * + * Description: + * ADC1/2 interrupt handler for the STM32 F1/F3 families. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, FAR void *context) +{ #ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } + adc_interrupt(&g_adcdev1); +#endif + +#ifdef CONFIG_STM32_ADC2 + adc_interrupt(&g_adcdev2); +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc3_interrupt + * + * Description: + * ADC3 interrupt handler for the STM32 F1 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3) +static int adc3_interrupt(int irq, FAR void *context) +{ + adc_interrupt(&g_adcdev3); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc4_interrupt + * + * Description: + * ADC4 interrupt handler for the STM32 F3 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, FAR void *context) +{ +#ifdef CONFIG_STM32_ADC4 + adc_interrupt(&g_adcdev4); #endif return OK; @@ -2634,7 +2827,7 @@ static int adc_stm32l_interrupt(int irq, void *context) * Name: adc123_interrupt * * Description: - * ADC1/2/3 interrupt handler for the STM32 F4 family. + * ADC1/2/3 interrupt handler for the STM32 F2/F4 families. * * Input Parameters: * @@ -2643,49 +2836,20 @@ static int adc_stm32l_interrupt(int irq, void *context) ****************************************************************************/ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int adc123_interrupt(int irq, void *context) +static int adc123_interrupt(int irq, FAR void *context) { - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC1 interrupts */ - #ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } + adc_interrupt(&g_adcdev1); #endif - /* Check for pending ADC2 interrupts */ - #ifdef CONFIG_STM32_ADC2 - regval = getreg32(STM32_ADC2_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev2); - regval &= ~pending; - putreg32(regval, STM32_ADC2_SR); - } + adc_interrupt(&g_adcdev2); #endif - /* Check for pending ADC3 interrupts */ - #ifdef CONFIG_STM32_ADC3 - regval = getreg32(STM32_ADC3_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev3); - regval &= ~pending; - putreg32(regval, STM32_ADC3_SR); - } + adc_interrupt(&g_adcdev3); #endif + return OK; } #endif @@ -2697,21 +2861,21 @@ static int adc123_interrupt(int irq, void *context) /**************************************************************************** * Name: adc_change_sample_time * - * Description : Changes sample times for specified channels. This method - * doesn't make any register writing. So, it's only stores the information. - * Values provided by user will be written in registers only on the next adc - * peripheral start, as it was told to do in manual. However, before very first - * start, user can call this method and override default values either - * for every channels or for only some predefined by user channel(s) + * Description: + * Changes sample times for specified channels. This method + * doesn't make any register writing. So, it's only stores the information. + * Values provided by user will be written in registers only on the next + * ADC peripheral start, as it was told to do in manual. However, before + * very first start, user can call this method and override default values + * either for every channels or for only some predefined by user channel(s) * * Input Parameters: - * * priv - pointer to the adc device structure * pdi_high - true: The ADC is powered down when waiting for a start event * false: The ADC is powered up when waiting for a start event * * Returned Value: - * None. + * None * ****************************************************************************/ @@ -2773,65 +2937,58 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, * ****************************************************************************/ -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, +struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, int cchannels) { FAR struct adc_dev_s *dev; FAR struct stm32_dev_s *priv; - allvdbg("intf: %d cchannels: %d\n", intf, cchannels); + avdbg("intf: %d cchannels: %d\n", intf, cchannels); -#ifdef CONFIG_STM32_ADC1 - if (intf == 1) + switch (intf) { - allvdbg("ADC1 Selected\n"); - dev = &g_adcdev1; - } - else +#ifdef CONFIG_STM32_ADC1 + case 1: + avdbg("ADC1 selected\n"); + dev = &g_adcdev1; + break; #endif #ifdef CONFIG_STM32_ADC2 - if (intf == 2) - { - avdbg("ADC2 Selected\n"); - dev = &g_adcdev2; - } - else + case 2: + avdbg("ADC2 selected\n"); + dev = &g_adcdev2; + break; #endif #ifdef CONFIG_STM32_ADC3 - if (intf == 3) - { - avdbg("ADC3 Selected\n"); - dev = &g_adcdev3; - } - else + case 3: + avdbg("ADC3 selected\n"); + dev = &g_adcdev3; + break; #endif - { - adbg("No ADC interface defined\n"); - return NULL; +#ifdef CONFIG_STM32_ADC4 + case 4: + avdbg("ADC4 selected\n"); + dev = &g_adcdev4; + break; +#endif + default: + adbg("No ADC interface defined\n"); + return NULL; } /* Configure the selected ADC */ - priv = dev->ad_priv; + priv = (FAR struct stm32_dev_s *)dev->ad_priv; #if defined(CONFIG_STM32_STM32L15XX) /* Assign default values for the sample time table */ - memset(priv->sample_rate, ADC_DEFAULT_SAMPLE, ADC_CHANNELS_NUMBER); + memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); #endif -#ifdef ADC_HAVE_DMA - if (priv->hasdma) - { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_DMA); - } - else -#endif - { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA); - } + DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); priv->cchannels = cchannels; @@ -2840,6 +2997,11 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */ -#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || + * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F40XX || + * CONFIG_STM32_STM32L15XX + */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 + */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index 5a4534b275..3f354f28f3 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_adc.h * * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -62,33 +64,48 @@ * to be used for that purpose. */ -/* For the STM32 F1 line, timers 1-4 may be used. For STM32 F4 line, timers 1-5 and - * 8 may be used. For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used +/* For the STM32 F1 line, timers 1-4 may be used. + * For the STM32 F3 line, timers 1-4, 6-8, 15, 20 may be used. + * For the STM32 F2/F4 lines, timers 1-5 and 8 may be used. + * For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used. */ -#ifndef CONFIG_STM32_TIM1 +#ifdef CONFIG_STM32_STM32L15XX # undef CONFIG_STM32_TIM1_ADC # undef CONFIG_STM32_TIM1_ADC1 # undef CONFIG_STM32_TIM1_ADC2 # undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +#else +# ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +# endif #endif + #ifndef CONFIG_STM32_TIM2 # undef CONFIG_STM32_TIM2_ADC # undef CONFIG_STM32_TIM2_ADC1 # undef CONFIG_STM32_TIM2_ADC2 # undef CONFIG_STM32_TIM2_ADC3 +# undef CONFIG_STM32_TIM2_ADC4 #endif #ifndef CONFIG_STM32_TIM3 # undef CONFIG_STM32_TIM3_ADC # undef CONFIG_STM32_TIM3_ADC1 # undef CONFIG_STM32_TIM3_ADC2 # undef CONFIG_STM32_TIM3_ADC3 +# undef CONFIG_STM32_TIM3_ADC4 #endif #ifndef CONFIG_STM32_TIM4 # undef CONFIG_STM32_TIM4_ADC # undef CONFIG_STM32_TIM4_ADC1 # undef CONFIG_STM32_TIM4_ADC2 # undef CONFIG_STM32_TIM4_ADC3 +# undef CONFIG_STM32_TIM4_ADC4 #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) @@ -97,23 +114,31 @@ # undef CONFIG_STM32_TIM5_ADC1 # undef CONFIG_STM32_TIM5_ADC2 # undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 # endif -# ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_ADC -# undef CONFIG_STM32_TIM8_ADC1 -# undef CONFIG_STM32_TIM8_ADC2 -# undef CONFIG_STM32_TIM8_ADC3 -# endif -# #else # undef CONFIG_STM32_TIM5_ADC # undef CONFIG_STM32_TIM5_ADC1 # undef CONFIG_STM32_TIM5_ADC2 # undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) +# ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 +# endif +#else # undef CONFIG_STM32_TIM8_ADC # undef CONFIG_STM32_TIM8_ADC1 # undef CONFIG_STM32_TIM8_ADC2 # undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 #endif /* Timers 6, 7, 9, 10 used by STM32L15XX family devices. Though there is only ADC @@ -121,50 +146,60 @@ * See definition of the STM32_NADC */ -#if defined(CONFIG_STM32_STM32L15XX) +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F30XX) # ifndef CONFIG_STM32_TIM6 # undef CONFIG_STM32_TIM6_ADC # undef CONFIG_STM32_TIM6_ADC1 # undef CONFIG_STM32_TIM6_ADC2 # undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 # endif # ifndef CONFIG_STM32_TIM7 # undef CONFIG_STM32_TIM7_ADC # undef CONFIG_STM32_TIM7_ADC1 # undef CONFIG_STM32_TIM7_ADC2 # undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 # endif +#else +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 +# undef CONFIG_STM32_TIM7_ADC +# undef CONFIG_STM32_TIM7_ADC1 +# undef CONFIG_STM32_TIM7_ADC2 +# undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32L15XX) # ifndef CONFIG_STM32_TIM9 # undef CONFIG_STM32_TIM9_ADC # undef CONFIG_STM32_TIM9_ADC1 # undef CONFIG_STM32_TIM9_ADC2 # undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 # endif # ifndef CONFIG_STM32_TIM10 # undef CONFIG_STM32_TIM10_ADC # undef CONFIG_STM32_TIM10_ADC1 # undef CONFIG_STM32_TIM10_ADC2 # undef CONFIG_STM32_TIM10_ADC3 +# undef CONFIG_STM32_TIM10_ADC4 # endif -# #else -# undef CONFIG_STM32_TIM6_ADC -# undef CONFIG_STM32_TIM6_ADC1 -# undef CONFIG_STM32_TIM6_ADC2 -# undef CONFIG_STM32_TIM6_ADC3 -# undef CONFIG_STM32_TIM7_ADC -# undef CONFIG_STM32_TIM7_ADC1 -# undef CONFIG_STM32_TIM7_ADC2 -# undef CONFIG_STM32_TIM7_ADC3 # undef CONFIG_STM32_TIM9_ADC # undef CONFIG_STM32_TIM9_ADC1 # undef CONFIG_STM32_TIM9_ADC2 # undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 # undef CONFIG_STM32_TIM10_ADC # undef CONFIG_STM32_TIM10_ADC1 # undef CONFIG_STM32_TIM10_ADC2 # undef CONFIG_STM32_TIM10_ADC3 -# +# undef CONFIG_STM32_TIM10_ADC4 #endif /* Timers 6, 7, and 10-14 are not used with the ADC by any supported family @@ -174,20 +209,56 @@ #undef CONFIG_STM32_TIM11_ADC1 #undef CONFIG_STM32_TIM11_ADC2 #undef CONFIG_STM32_TIM11_ADC3 +#undef CONFIG_STM32_TIM11_ADC4 #undef CONFIG_STM32_TIM12_ADC #undef CONFIG_STM32_TIM12_ADC1 #undef CONFIG_STM32_TIM12_ADC2 #undef CONFIG_STM32_TIM12_ADC3 +#undef CONFIG_STM32_TIM12_ADC4 #undef CONFIG_STM32_TIM13_ADC #undef CONFIG_STM32_TIM13_ADC1 #undef CONFIG_STM32_TIM13_ADC2 #undef CONFIG_STM32_TIM13_ADC3 +#undef CONFIG_STM32_TIM13_ADC4 #undef CONFIG_STM32_TIM14_ADC #undef CONFIG_STM32_TIM14_ADC1 #undef CONFIG_STM32_TIM14_ADC2 #undef CONFIG_STM32_TIM14_ADC3 +#undef CONFIG_STM32_TIM14_ADC4 -/* Up to 3 ADC interfaces are supported */ +#ifdef CONFIG_STM32_STM32F30XX +# ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# endif +# ifndef CONFIG_STM32_TIM20 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +#endif + +/* Up to 4 ADC interfaces are supported */ + +#if STM32_NADC < 4 +# undef CONFIG_STM32_ADC4 +#endif #if STM32_NADC < 3 # undef CONFIG_STM32_ADC3 @@ -202,17 +273,17 @@ #endif #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) /* DMA support */ #undef ADC_HAVE_DMA #if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA) -# if defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32F40XX) -# define ADC_HAVE_DMA 1 +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ADC_HAVE_DMA 1 # else -# warning DMA is only supported for the STM32 F2/F4 family +# warning "DMA is only supported for the STM32 F2/F3/F4 families" # undef CONFIG_STM32_ADC1_DMA # undef CONFIG_STM32_ADC2_DMA # undef CONFIG_STM32_ADC3_DMA @@ -291,6 +362,10 @@ # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM10_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN #else # undef ADC1_HAVE_TIMER #endif @@ -325,10 +400,18 @@ # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM6_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN #else # undef ADC2_HAVE_TIMER #endif @@ -363,10 +446,22 @@ # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM7_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM20_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN #else # undef ADC3_HAVE_TIMER #endif @@ -381,7 +476,58 @@ # endif #endif -#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER) +#if defined(CONFIG_STM32_TIM1_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM1_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM2_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM3_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM4_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM5_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM7_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM8_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM15_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM20_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +#else +# undef ADC4_HAVE_TIMER +#endif + +#ifdef ADC4_HAVE_TIMER +# ifndef CONFIG_STM32_ADC4_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC4_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC4_TIMTRIG +# error "CONFIG_STM32_ADC4_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" +# endif +#endif + +#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \ + defined(ADC3_HAVE_TIMER) || defined(ADC4_HAVE_TIMER) # define ADC_HAVE_TIMER 1 # if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER) # warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" @@ -401,143 +547,641 @@ * for other 3 ADC's */ +#ifdef CONFIG_STM32_STM32F30XX +# define ADC1_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO +#else +# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +#endif + #if defined(CONFIG_STM32_TIM1_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM6_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM7_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM9_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM10_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif @@ -545,85 +1189,113 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif @@ -631,88 +1303,258 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#endif + +#if defined(CONFIG_STM32_TIM1_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif #endif /************************************************************************************ @@ -740,7 +1582,7 @@ typedef enum ADC_IO_CMDS typedef struct adc_channel_s { - uint8_t channel : 5; + uint8_t channel:5; /* Sampling time individually for each channel * 000: 4 cycles @@ -753,19 +1595,20 @@ typedef struct adc_channel_s * 111: 384 cycles - selected for all channels */ - uint8_t sample_time : 3; + uint8_t sample_time:3; } adc_channel_t; /* This structure will be used while setting channels to specified by the * "channel-sample time" pairs' values */ -struct adc_sample_time_s { - adc_channel_t *channel; /* array of channels */ - uint8_t channels_nbr:5; /* number of channels in array */ - bool all_same:1; /* All 32 channels will get the +struct adc_sample_time_s +{ + adc_channel_t *channel; /* Array of channels */ + uint8_t channels_nbr:5; /* Number of channels in array */ + bool all_same:1; /* All 32 channels will get the * same value of the sample time */ - uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */ + uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */ }; #endif @@ -814,5 +1657,7 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 + */ #endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */ From 68ae17a8a79df71a790206b6f0aef4096d29d4ed Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 5 Nov 2015 10:31:52 -0600 Subject: [PATCH 28/41] SAMV7 QSPI: Various kludges added during debug of QSPI. I am not if any of these are really correct --- arch/arm/src/samv7/sam_qspi.c | 49 +++++++++++++++++++++++++---------- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index e886d7356c..9cd7ea37d3 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -130,12 +130,14 @@ /* The SAMV7x QSPI driver insists that transfers be performed in multiples * of 32-bits. + * + * REVISIT: Why is this done? This logic is here only because it is also + * done this way in the Atmel sample code. But I have no idea why. */ #define ALIGN_SHIFT 2 #define ALIGN_MASK 3 #define ALIGN_UP(n) (((n)+ALIGN_MASK) & ~ALIGN_MASK) -#define ALIGN_WORDS(n) (((n)+ALIGN_MASK) >> ALIGN_SHIFT) #define IS_ALIGNED(n) (((uint32_t)(n) & ALIGN_MASK) == 0) /* Debug *******************************************************************/ @@ -1205,8 +1207,12 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * * DLYBCT = 500 * QSPI_CLK / 1000000000 / 32 * = (500 * (QSPI_CLK / 1000000) / 1000 / 32 - */ + * + * REVISIT: The following logic is conditioned out because for some + * inexplicable reason results in hangs -- Even though is it effectively + * a no-op for the default case where DLYBCT == 0. +#if 0 /* REVISIT -- Causes a hang for some reason */ regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); regval &= ~QSPI_MR_DLYBCT_MASK; @@ -1216,6 +1222,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) #endif qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); +#endif /* Calculate the new actual frequency */ @@ -1461,17 +1468,23 @@ static int qspi_command(struct qspi_dev_s *dev, ifr |= QSPI_IFR_WIDTH_SINGLE | QSPI_IFR_INSTEN | QSPI_IFR_DATAEN | QSPI_IFR_NBDUM(0); + /* Read or write operation? */ + if (QSPICMD_ISWRITE(cmdinfo->flags)) { - /* Set write data operation */ + /* Set write data operation + * + * Write the IFR to the hardware. If the instructrion frame + * includes data, writing to the IFR does not trigger the + * instruction frame transfer. Rather, the instruction frame + * is triggered by the first access to QSPI memory. + */ ifr |= QSPI_IFR_TFRTYP_WRITE; qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET); - /* Write the IFR to the hardware. If the instructrion frame - * includes data, writing to the IFR does not trigger the - * instruction frame transfer. Rather, the instruction frame - * is triggered by the first access to QSPI memory. + /* Read QSPI_IFR (dummy read) to synchronize APB and AHB + * accesses. */ (void)qspi_getreg(priv, SAM_QSPI_IFR_OFFSET); @@ -1483,15 +1496,19 @@ static int qspi_command(struct qspi_dev_s *dev, } else { - /* Set read data operation */ + /* Set read data operation + * + * Write the IFR to the hardware. If the instructrion frame + * includes data, writing to the IFR does not trigger the + * instruction frame transfer. Rather, the instruction frame + * is triggered by the first access to QSPI memory. + */ ifr |= QSPI_IFR_TFRTYP_READ; qspi_putreg(priv, ifr, SAM_QSPI_IFR_OFFSET); - /* Write the IFR to the hardware. If the instructrion frame - * includes data, writing to the IFR does not trigger the - * instruction frame transfer. Rather, the instruction frame - * is triggered by the first access to QSPI memory. + /* Read QSPI_IFR (dummy read) to synchronize APB and AHB + * accesses. */ (void)qspi_getreg(priv, SAM_QSPI_IFR_OFFSET); @@ -1539,7 +1556,13 @@ static int qspi_command(struct qspi_dev_s *dev, /* If the insruction frame does not include data, writing to the IFR * tiggers sending of the instruction frame. Fall through to INSTRE * wait. + * + * REVISIT: Setting QSPI_CR_LASTXFER should not be necessary in this + * case. However, I see hangs in the following wait for QSPI_SR_INSTRE + * if I do not do this. No idea why. */ + + qspi_putreg(priv, QSPI_CR_LASTXFER, SAM_QSPI_CR_OFFSET); } /* When the command has been sent, Instruction End Status (INTRE) will be @@ -1588,7 +1611,7 @@ static int qspi_memory(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: QSPI_ALLOC + * Name: qspi_alloc * * Description: * Allocate a buffer suitable for DMA data transfer From e866cdd6f1dd870873f6177c3e95470eaca0a4f3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 5 Nov 2015 10:43:49 -0600 Subject: [PATCH 29/41] Fix missed closing comment in last commit --- arch/arm/src/samv7/sam_qspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 9cd7ea37d3..495b5c66f8 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -1211,6 +1211,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * REVISIT: The following logic is conditioned out because for some * inexplicable reason results in hangs -- Even though is it effectively * a no-op for the default case where DLYBCT == 0. + */ #if 0 /* REVISIT -- Causes a hang for some reason */ regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); From dff502d99b8af78ae5168ece8a907afe848f18c9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 5 Nov 2015 15:03:53 -0600 Subject: [PATCH 30/41] SAMV7 QSPI: Costmetic changes --- arch/arm/src/samv7/sam_qspi.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 495b5c66f8..1baf392fb5 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -126,7 +126,7 @@ /* QSPI memory synchronization */ -#define MEMORY_SYNC() do { ARM_DSB();ARM_ISB(); } while (0) +#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) /* The SAMV7x QSPI driver insists that transfers be performed in multiples * of 32-bits. @@ -715,7 +715,7 @@ static int qspi_memory_enable(struct sam_qspidev_s *priv, * QSPI_ICR_OPT(0) No option */ - regval = QSPI_ICR_INST(meminfo->cmd) | QSPI_ICR_OPT(0); + regval = QSPI_ICR_INST(meminfo->cmd) | QSPI_ICR_OPT(0); qspi_putreg(priv, regval, SAM_QSPI_ICR_OFFSET); /* Is memory data scrambled? */ @@ -1148,13 +1148,14 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) return priv->actual; } - /* Configure QSPI to a frequency as close as possible to the requested frequency. + /* Configure QSPI to a frequency as close as possible to the requested + * frequency. * * QSCK frequency = QSPI_CLK / SCBR, or SCBR = QSPI_CLK / frequency * - * Where SCBR can have the range 1 to 256 and register holds SCBR - 1. NOTE - * that a "ceiling" type of calculation is performed. 'frequency' is treated - * as a not-to-exceed value. + * Where SCBR can have the range 1 to 256 and the SCR register field holds + * SCBR - 1. NOTE that a "ceiling" type of calculation is performed. + * 'frequency' is treated as a not-to-exceed value. */ scbr = (frequency + SAM_QSPI_CLOCK - 1) / frequency; @@ -1344,7 +1345,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits) regval |= QSPI_MR_NBBITS(nbits); qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); - qspivdbg("SCR%02x]=%08x\n", regval); + qspivdbg("MR=%08x\n", regval); /* Save the selection so the subsequence re-configurations will be faster */ @@ -1758,7 +1759,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) struct sam_qspidev_s *priv; int ret; - /* The support SAM parts have only a single QSPI port */ + /* The supported SAM parts have only a single QSPI port */ qspivdbg("intf: %d\n", intf); DEBUGASSERT(intf >= 0 && intf < SAMV7_NQSPI); From 4371b756df99969e9b0974a0aa3b2f303c1c55e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 11:12:28 -0600 Subject: [PATCH 31/41] SAMV7: Add MPU and protected build support --- arch/arm/src/samv7/Kconfig | 2 + arch/arm/src/samv7/Make.defs | 12 ++- arch/arm/src/samv7/sam_mpuinit.c | 130 +++++++++++++++++++++++++++++ arch/arm/src/samv7/sam_mpuinit.h | 22 +---- arch/arm/src/samv7/sam_start.c | 9 ++ arch/arm/src/samv7/sam_userspace.c | 102 ++++++++++++++++++++++ 6 files changed, 258 insertions(+), 19 deletions(-) create mode 100644 arch/arm/src/samv7/sam_mpuinit.c create mode 100644 arch/arm/src/samv7/sam_userspace.c diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 7aa5707bd0..e0dc801581 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -287,6 +287,8 @@ config SAMV7_PWM1 config SAMV7_QSPI bool "Quad SPI (QSPI)" default n + select ARCH_USE_MPU + select ARMV7M_MPU config SAMV7_RTC bool "Real Time Clock (RTC)" diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 5545c86c65..8a8f86fd2c 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -90,13 +90,16 @@ ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S endif +ifeq ($(CONFIG_ARMV7M_MPU),y) +CMN_CSRCS += up_mpu.c ifeq ($(CONFIG_BUILD_PROTECTED),y) -CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +CMN_CSRCS += up_task_start.c up_pthread_start.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_signal_dispatch.c CMN_UASRCS += up_signal_handler.S endif endif +endif ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c @@ -118,6 +121,13 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += sam_timerisr.c endif +ifeq ($(CONFIG_ARMV7M_MPU),y) +CHIP_CSRCS += sam_mpuinit.c +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += sam_userspace.c +endif +endif + ifeq ($(CONFIG_SAMV7_GPIO_IRQ),y) CHIP_CSRCS += sam_gpioirq.c endif diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c new file mode 100644 index 0000000000..ce0e54021d --- /dev/null +++ b/arch/arm/src/samv7/sam_mpuinit.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/arm/src/common/sam_mpuinit.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "sam_mpuinit.h" + +#ifdef CONFIG_ARMV7M_MPU + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3/4 + * resources. + * + ****************************************************************************/ + +void sam_mpu_initialize(void) +{ +#ifdef CONFIG_BUILD_PROTECTED + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); +#endif + + /* Show MPU information */ + + mpu_showtype(); + +#ifdef CONFIG_BUILD_PROTECTED + /* Configure user flash and SRAM space */ + + mpu_userflash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_userintsram(datastart, dataend - datastart); +#endif + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: sam_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void sam_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_userintsram(start, size); +} +#endif + +#endif /* CONFIG_ARMV7M_MPU */ + diff --git a/arch/arm/src/samv7/sam_mpuinit.h b/arch/arm/src/samv7/sam_mpuinit.h index 10243f29be..e8745f8e6b 100644 --- a/arch/arm/src/samv7/sam_mpuinit.h +++ b/arch/arm/src/samv7/sam_mpuinit.h @@ -1,5 +1,4 @@ /**************************************************************************** - * Name: sam_mpuinitialize * arch/arm/src/samv7/sam_mpuinit.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. @@ -38,7 +37,6 @@ #define __ARCH_ARM_SRC_SAMV7_SAM_MPUINIT_H /**************************************************************************** - * Name: sam_mpuinitialize * Included Files ****************************************************************************/ @@ -48,24 +46,12 @@ #include /**************************************************************************** - * Name: sam_mpuinitialize - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_mpuinitialize - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_mpuinitialize * Inline Functions ****************************************************************************/ #ifndef __ASSEMBLY__ /**************************************************************************** - * Name: sam_mpuinitialize * Public Data ****************************************************************************/ @@ -83,7 +69,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: sam_mpuinitialize + * Name: sam_mpu_initialize * * Description: * Configure the MPU to permit user-space access to only unrestricted SAMV7 @@ -91,10 +77,10 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_BUILD_PROTECTED -void sam_mpuinitialize(void); +#ifdef CONFIG_ARMV7M_MPU +void sam_mpu_initialize(void); #else -# define sam_mpuinitialize() +# define sam_mpu_initialize() #endif /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index ec12b7ef87..bd45aea63b 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -378,6 +378,7 @@ void __start(void) up_earlyserialinit(); #endif +#ifdef CONFIG_ARMV7M_MPU /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. * Normally this just means initializing the user space .data and .bss @@ -388,6 +389,14 @@ void __start(void) sam_userspace(); #endif + /* Configure the MPU to permit user-space access to its FLASH and RAM (for + * CONFIG_BUILD_PROTECTED) or to manage cache properties (for + * CONFIG_SAMV7_QSPI). + */ + + sam_mpu_initialize(); +#endif + /* Then start NuttX */ #ifdef CONFIG_STACK_COLORATION diff --git a/arch/arm/src/samv7/sam_userspace.c b/arch/arm/src/samv7/sam_userspace.c new file mode 100644 index 0000000000..136c5ac1d7 --- /dev/null +++ b/arch/arm/src/samv7/sam_userspace.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_userspace.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "sam_mpuinit.h" +#include "sam_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void sam_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } +} + +#endif /* CONFIG_BUILD_PROTECTED */ From 1c79e77811c79f02ac0ef5e470b9f146c2837f24 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 11:24:52 -0600 Subject: [PATCH 32/41] ARMv7-M: Minor naming change to improve readability --- arch/arm/src/armv7-m/mpu.h | 24 ++++++++++++------------ arch/arm/src/kinetis/kinetis_mpuinit.c | 8 ++++---- arch/arm/src/lpc17xx/lpc17_mpuinit.c | 8 ++++---- arch/arm/src/lpc43xx/lpc43_mpuinit.c | 8 ++++---- arch/arm/src/sam34/sam_mpuinit.c | 8 ++++---- arch/arm/src/samv7/sam_mpuinit.c | 8 ++++---- arch/arm/src/stm32/stm32_mpuinit.c | 8 ++++---- arch/arm/src/stm32f7/stm32_mpuinit.c | 8 ++++---- arch/arm/src/tiva/tiva_mpuinit.c | 8 ++++---- 9 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 3726ee5764..780e5710a5 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -248,14 +248,14 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena) } /**************************************************************************** - * Name: mpu_userflash + * Name: mpu_user_flash * * Description: * Configure a region for user program flash * ****************************************************************************/ -static inline void mpu_userflash(uintptr_t base, size_t size) +static inline void mpu_user_flash(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -286,14 +286,14 @@ static inline void mpu_userflash(uintptr_t base, size_t size) } /**************************************************************************** - * Name: mpu_privflash + * Name: mpu_priv_flash * * Description: * Configure a region for privileged program flash * ****************************************************************************/ -static inline void mpu_privflash(uintptr_t base, size_t size) +static inline void mpu_priv_flash(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -324,14 +324,14 @@ static inline void mpu_privflash(uintptr_t base, size_t size) } /**************************************************************************** - * Name: mpu_userintsram + * Name: mpu_user_intsram * * Description: * Configure a region as user internal SRAM * ****************************************************************************/ -static inline void mpu_userintsram(uintptr_t base, size_t size) +static inline void mpu_user_intsram(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -363,14 +363,14 @@ static inline void mpu_userintsram(uintptr_t base, size_t size) } /**************************************************************************** - * Name: mpu_privintsram + * Name: mpu_priv_intsram * * Description: * Configure a region as privileged internal SRAM * ****************************************************************************/ -static inline void mpu_privintsram(uintptr_t base, size_t size) +static inline void mpu_priv_intsram(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -402,14 +402,14 @@ static inline void mpu_privintsram(uintptr_t base, size_t size) } /**************************************************************************** - * Name: mpu_userextsram + * Name: mpu_user_extsram * * Description: * Configure a region as user external SRAM * ****************************************************************************/ -static inline void mpu_userextsram(uintptr_t base, size_t size) +static inline void mpu_user_extsram(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -442,14 +442,14 @@ static inline void mpu_userextsram(uintptr_t base, size_t size) } /**************************************************************************** - * Name: mpu_privextsram + * Name: mpu_priv_extsram * * Description: * Configure a region as privileged external SRAM * ****************************************************************************/ -static inline void mpu_privextsram(uintptr_t base, size_t size) +static inline void mpu_priv_extsram(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); uint32_t regval; diff --git a/arch/arm/src/kinetis/kinetis_mpuinit.c b/arch/arm/src/kinetis/kinetis_mpuinit.c index 112aa63f40..8e2bceb622 100644 --- a/arch/arm/src/kinetis/kinetis_mpuinit.c +++ b/arch/arm/src/kinetis/kinetis_mpuinit.c @@ -95,10 +95,10 @@ void kinetis_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void kinetis_mpuinitialize(void) void kinetis_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/lpc17xx/lpc17_mpuinit.c b/arch/arm/src/lpc17xx/lpc17_mpuinit.c index 19b5858aaa..adc4bc918c 100644 --- a/arch/arm/src/lpc17xx/lpc17_mpuinit.c +++ b/arch/arm/src/lpc17xx/lpc17_mpuinit.c @@ -95,10 +95,10 @@ void lpc17_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void lpc17_mpuinitialize(void) void lpc17_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/lpc43xx/lpc43_mpuinit.c b/arch/arm/src/lpc43xx/lpc43_mpuinit.c index 770bb496df..499c38a977 100644 --- a/arch/arm/src/lpc43xx/lpc43_mpuinit.c +++ b/arch/arm/src/lpc43xx/lpc43_mpuinit.c @@ -95,10 +95,10 @@ void lpc43_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void lpc43_mpuinitialize(void) void lpc43_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/sam34/sam_mpuinit.c b/arch/arm/src/sam34/sam_mpuinit.c index b5f6c7e906..a33788b7d1 100644 --- a/arch/arm/src/sam34/sam_mpuinit.c +++ b/arch/arm/src/sam34/sam_mpuinit.c @@ -95,10 +95,10 @@ void sam_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void sam_mpuinitialize(void) void sam_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c index ce0e54021d..842012be4d 100644 --- a/arch/arm/src/samv7/sam_mpuinit.c +++ b/arch/arm/src/samv7/sam_mpuinit.c @@ -98,10 +98,10 @@ void sam_mpu_initialize(void) #ifdef CONFIG_BUILD_PROTECTED /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); #endif /* Then enable the MPU */ @@ -122,7 +122,7 @@ void sam_mpu_initialize(void) #ifdef CONFIG_BUILD_PROTECTED void sam_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif diff --git a/arch/arm/src/stm32/stm32_mpuinit.c b/arch/arm/src/stm32/stm32_mpuinit.c index 7145b518a3..e5f727ae38 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.c +++ b/arch/arm/src/stm32/stm32_mpuinit.c @@ -95,10 +95,10 @@ void stm32_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void stm32_mpuinitialize(void) void stm32_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/stm32f7/stm32_mpuinit.c b/arch/arm/src/stm32f7/stm32_mpuinit.c index 4f019c1fbe..60f0c69dc1 100644 --- a/arch/arm/src/stm32f7/stm32_mpuinit.c +++ b/arch/arm/src/stm32f7/stm32_mpuinit.c @@ -87,10 +87,10 @@ void stm32_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -109,7 +109,7 @@ void stm32_mpuinitialize(void) void stm32_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ diff --git a/arch/arm/src/tiva/tiva_mpuinit.c b/arch/arm/src/tiva/tiva_mpuinit.c index dfefebafc0..a1fe80d86e 100644 --- a/arch/arm/src/tiva/tiva_mpuinit.c +++ b/arch/arm/src/tiva/tiva_mpuinit.c @@ -95,10 +95,10 @@ void tiva_mpuinitialize(void) /* Configure user flash and SRAM space */ - mpu_userflash(USERSPACE->us_textstart, - USERSPACE->us_textend - USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); - mpu_userintsram(datastart, dataend - datastart); + mpu_user_intsram(datastart, dataend - datastart); /* Then enable the MPU */ @@ -117,7 +117,7 @@ void tiva_mpuinitialize(void) void tiva_mpu_uheap(uintptr_t start, size_t size) { - mpu_userintsram(start, size); + mpu_user_intsram(start, size); } #endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARMV7M_MPU */ From 771095e25fe2030814be5fe47707f19b0e72a14f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 11:50:57 -0600 Subject: [PATCH 33/41] ARMv7-M: Add MPU support for strongly couple memory regions --- arch/arm/src/armv7-m/mpu.h | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 780e5710a5..990e30aa1d 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -247,6 +247,48 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena) putreg32(regval, MPU_CTRL); } +/**************************************************************************** + * Name: mpu_priv_stronglyordered + * + * Description: + * Configure a region for privileged, strongly ordered memory + * + ****************************************************************************/ + +#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE) +static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) +{ + unsigned int region = mpu_allocregion(); + uint32_t regval; + uint8_t l2size; + uint8_t subregions; + + /* Select the region */ + + putreg32(region, MPU_RNR); + + /* Select the region base address */ + + putreg32((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID, MPU_RBAR); + + /* Select the region size and the sub-region map */ + + l2size = mpu_log2regionceil(size); + subregions = mpu_subregion(base, size, l2size); + + /* The configure the region */ + + regval = MPU_RASR_ENABLE | /* Enable region */ + MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ + ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ + /* Not Cacheable */ + /* Not Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWNO; /* P:RW U:None */ + putreg32(regval, MPU_RASR); +} +#endif + /**************************************************************************** * Name: mpu_user_flash * From 553ba1a68277d89b2d0f038d982d4635bba0622a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 12:10:15 -0600 Subject: [PATCH 34/41] SAMV7 QSPI: When QSPI is enabled, make the QSPI memory strongly ordered --- arch/arm/src/armv7-m/cache.h | 2 ++ arch/arm/src/samv7/chip/samv71_memorymap.h | 4 +++ arch/arm/src/samv7/sam_mpuinit.c | 30 ++++++++++++++++++---- arch/arm/src/samv7/sam_start.c | 1 + 4 files changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/armv7-m/cache.h b/arch/arm/src/armv7-m/cache.h index 7dd1059f79..d6b40b30a1 100644 --- a/arch/arm/src/armv7-m/cache.h +++ b/arch/arm/src/armv7-m/cache.h @@ -76,9 +76,11 @@ #define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") #define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") #define ARM_DSB() arm_dsb(15) #define ARM_ISB() arm_isb(15) +#define ARM_DMB() arm_dmb(15) /**************************************************************************** * Inline Functions diff --git a/arch/arm/src/samv7/chip/samv71_memorymap.h b/arch/arm/src/samv7/chip/samv71_memorymap.h index 917bfd0b5e..b7d55f1031 100644 --- a/arch/arm/src/samv7/chip/samv71_memorymap.h +++ b/arch/arm/src/samv7/chip/samv71_memorymap.h @@ -159,6 +159,10 @@ # define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x6fffffff: EBI Chip select 3 */ #define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */ +/* QSPI memory region */ + +#define SAM_QSPIMEM_SIZE 0x20000000 /* 0x80000000-0x9fffffff: QSPI memory */ + /* System memory region */ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c index 842012be4d..b2f730f40e 100644 --- a/arch/arm/src/samv7/sam_mpuinit.c +++ b/arch/arm/src/samv7/sam_mpuinit.c @@ -44,6 +44,9 @@ #include #include "mpu.h" +#include "cache.h" +#include "chip/sam_memorymap.h" + #include "sam_mpuinit.h" #ifdef CONFIG_ARMV7M_MPU @@ -84,23 +87,40 @@ void sam_mpu_initialize(void) { #ifdef CONFIG_BUILD_PROTECTED - uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); - uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); - - DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && - dataend >= datastart); + uintptr_t datastart; + uintptr_t dataend; #endif /* Show MPU information */ mpu_showtype(); +#ifdef CONFIG_ARMV7M_DCACHE + /* Memory barrier */ + + ARM_DMB(); + +#ifdef CONFIG_SAMV7_QSPI + /* Make QSPI memory region strongly ordered */ + + mpu_priv_stronglyordered(SAM_QSPIMEM_BASE, SAM_QSPIMEM_SIZE); + +#endif +#endif + #ifdef CONFIG_BUILD_PROTECTED /* Configure user flash and SRAM space */ + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart); + mpu_user_flash(USERSPACE->us_textstart, USERSPACE->us_textend - USERSPACE->us_textstart); + datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(dataend >= datastart); + mpu_user_intsram(datastart, dataend - datastart); #endif diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index bd45aea63b..985e24e181 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -55,6 +55,7 @@ #endif #include "sam_clockconfig.h" +#include "sam_mpuinit.h" #include "sam_userspace.h" #include "sam_start.h" From 17c8cbceafb51ba1163297fa54f99ca6b1663779 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 12:59:40 -0600 Subject: [PATCH 35/41] SAMV7 QSPI: Rounding up buffer length for memcpy style transfer is un-necessary --- arch/arm/src/samv7/sam_qspi.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 1baf392fb5..36c5b924e8 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -990,11 +990,6 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv, struct qspi_meminfo_s *meminfo) { uintptr_t qspimem = SAM_QSPIMEM_BASE + meminfo->addr; - size_t buflen; - - /* Get the length as an even multiple of 32-bit words. */ - - buflen = ALIGN_UP(meminfo->buflen); /* Enable the memory transfer */ @@ -1004,13 +999,13 @@ static int qspi_memory_nodma(struct sam_qspidev_s *priv, if (QSPIMEM_ISWRITE(meminfo->flags)) { - qspi_memcpy((uint8_t *)qspimem, - (const uint8_t *)meminfo->buffer, buflen); + qspi_memcpy((uint8_t *)qspimem, (const uint8_t *)meminfo->buffer, + meminfo->buflen); } else { - qspi_memcpy((uint8_t *)meminfo->buffer, - (const uint8_t *)qspimem, buflen); + qspi_memcpy((uint8_t *)meminfo->buffer, (const uint8_t *)qspimem, + meminfo->buflen); } MEMORY_SYNC(); @@ -1443,15 +1438,9 @@ static int qspi_command(struct qspi_dev_s *dev, if (QSPICMD_ISDATA(cmdinfo->flags)) { - uint16_t buflen; - DEBUGASSERT(cmdinfo->buffer != NULL && cmdinfo->buflen > 0); DEBUGASSERT(IS_ALIGNED(cmdinfo->buffer)); - /* Get the length as an even multiple of 32-bit words. */ - - buflen = ALIGN_UP(cmdinfo->buflen); - /* Write Instruction Frame Register: * * QSPI_IFR_WIDTH_SINGLE Instruction=single bit/Data single bit @@ -1494,7 +1483,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Copy the data to write to QSPI_RAM */ qspi_memcpy((uint8_t *)SAM_QSPIMEM_BASE, - (const uint8_t *)cmdinfo->buffer, buflen); + (const uint8_t *)cmdinfo->buffer, cmdinfo->buflen); } else { @@ -1518,7 +1507,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* Copy the data from QSPI memory into the user buffer */ qspi_memcpy((uint8_t *)cmdinfo->buffer, - (const uint8_t *)SAM_QSPIMEM_BASE, buflen); + (const uint8_t *)SAM_QSPIMEM_BASE, cmdinfo->buflen); } MEMORY_SYNC(); From b4b0dde792259924f41bdee86d131468c5270df7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 13:02:45 -0600 Subject: [PATCH 36/41] SAMV7 QSPI: Back out some kludges that are no longer necessary --- arch/arm/src/samv7/sam_qspi.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 36c5b924e8..02d31a8467 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -1203,13 +1203,8 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * * DLYBCT = 500 * QSPI_CLK / 1000000000 / 32 * = (500 * (QSPI_CLK / 1000000) / 1000 / 32 - * - * REVISIT: The following logic is conditioned out because for some - * inexplicable reason results in hangs -- Even though is it effectively - * a no-op for the default case where DLYBCT == 0. */ -#if 0 /* REVISIT -- Causes a hang for some reason */ regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); regval &= ~QSPI_MR_DLYBCT_MASK; @@ -1219,7 +1214,6 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) #endif qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); -#endif /* Calculate the new actual frequency */ @@ -1547,13 +1541,7 @@ static int qspi_command(struct qspi_dev_s *dev, /* If the insruction frame does not include data, writing to the IFR * tiggers sending of the instruction frame. Fall through to INSTRE * wait. - * - * REVISIT: Setting QSPI_CR_LASTXFER should not be necessary in this - * case. However, I see hangs in the following wait for QSPI_SR_INSTRE - * if I do not do this. No idea why. */ - - qspi_putreg(priv, QSPI_CR_LASTXFER, SAM_QSPI_CR_OFFSET); } /* When the command has been sent, Instruction End Status (INTRE) will be From 7b3c0ac7bcdb6924c4dcad3c3d9f279ee39003eb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 6 Nov 2015 13:37:37 -0600 Subject: [PATCH 37/41] ARMv7-M: Cosmetic fixes to some file headers --- arch/arm/src/armv7-m/up_lazyexception.S | 2 +- arch/arm/src/armv7-m/up_stackcheck.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-m/up_lazyexception.S b/arch/arm/src/armv7-m/up_lazyexception.S index c6c837356a..cf43556481 100644 --- a/arch/arm/src/armv7-m/up_lazyexception.S +++ b/arch/arm/src/armv7-m/up_lazyexception.S @@ -1,5 +1,5 @@ /************************************************************************************************ - * arch/arm/src/armv7-m/sam_vectors.S + * arch/arm/src/armv7-m/up_lazyexcption.S * * Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/armv7-m/up_stackcheck.c b/arch/arm/src/armv7-m/up_stackcheck.c index 3da70b449e..1b465d233f 100644 --- a/arch/arm/src/armv7-m/up_stackcheck.c +++ b/arch/arm/src/armv7-m/up_stackcheck.c @@ -1,4 +1,5 @@ /**************************************************************************** + * arch/arm/src/armv7-m/up_stackcheck.c * * Copyright (c) 2013, 2014 PX4 Development Team. All rights reserved. * From 2e99311fb4bbe95a17d13fd7c26890fcb779bbd7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 7 Nov 2015 09:34:40 -0600 Subject: [PATCH 38/41] SAMV7 QSPI: DMA transfer width should be 32- not 16-bits --- arch/arm/src/samv7/sam_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 02d31a8467..b6407243d0 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -858,7 +858,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv, /* Configure RX DMA */ dmaflags |= ((uint32_t)priv->rxintf << DMACH_FLAG_PERIPHPID_SHIFT) | - DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_MEMWIDTH_16BITS; + DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_MEMWIDTH_32BITS; sam_dmaconfig(priv->dmach, dmaflags); /* Setup the RX DMA (memory-to-peripheral) */ From dd69967934106cec32fd9e281b10083d59c15fde Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 7 Nov 2015 09:35:23 -0600 Subject: [PATCH 39/41] SAMV7 protected mode: Don't enable D-Cache until userspace data has been initialized --- arch/arm/src/samv7/sam_start.c | 24 ++++++++++++------------ arch/arm/src/samv7/sam_userspace.c | 3 +++ 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index 985e24e181..285e429b6b 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -367,18 +367,6 @@ void __start(void) sam_boardinitialize(); - /* Enable I- and D-Caches */ - - arch_dcache_writethrough(); - arch_enable_icache(); - arch_enable_dcache(); - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - up_earlyserialinit(); -#endif - #ifdef CONFIG_ARMV7M_MPU /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. @@ -398,6 +386,18 @@ void __start(void) sam_mpu_initialize(); #endif + /* Enable I- and D-Caches */ + + arch_dcache_writethrough(); + arch_enable_icache(); + arch_enable_dcache(); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + /* Then start NuttX */ #ifdef CONFIG_STACK_COLORATION diff --git a/arch/arm/src/samv7/sam_userspace.c b/arch/arm/src/samv7/sam_userspace.c index 136c5ac1d7..255d59919a 100644 --- a/arch/arm/src/samv7/sam_userspace.c +++ b/arch/arm/src/samv7/sam_userspace.c @@ -62,6 +62,9 @@ * Normally this just means initializing the user space .data and .bss * segments. * + * Assumptions: + * The D-Cache has not yet been enabled. + * ****************************************************************************/ void sam_userspace(void) From 352d2a1d025b463f9a8deca039a6829294311616 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 7 Nov 2015 11:25:20 -0600 Subject: [PATCH 40/41] SAMV7 XDMAC: Don't sample interrupt status registers in debug mode. This can cause loss of interrupts --- arch/arm/src/samv7/sam_qspi.c | 5 +---- arch/arm/src/samv7/sam_xdmac.c | 4 ---- arch/arm/src/samv7/sam_xdmac.h | 16 ++++++++++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index b6407243d0..1b831c30ea 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -129,10 +129,7 @@ #define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0) /* The SAMV7x QSPI driver insists that transfers be performed in multiples - * of 32-bits. - * - * REVISIT: Why is this done? This logic is here only because it is also - * done this way in the Atmel sample code. But I have no idea why. + * of 32-bits. The alignment requirement only applies to RX DMA data. */ #define ALIGN_SHIFT 2 diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index b65b2f6eef..c519e15062 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -2037,7 +2037,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) regs->gcfg = sam_getdmac(xdmac, SAM_XDMAC_GCFG_OFFSET); regs->gwac = sam_getdmac(xdmac, SAM_XDMAC_GWAC_OFFSET); regs->gim = sam_getdmac(xdmac, SAM_XDMAC_GIM_OFFSET); - regs->gis = sam_getdmac(xdmac, SAM_XDMAC_GIS_OFFSET); regs->gs = sam_getdmac(xdmac, SAM_XDMAC_GS_OFFSET); regs->grs = sam_getdmac(xdmac, SAM_XDMAC_GRS_OFFSET); regs->gws = sam_getdmac(xdmac, SAM_XDMAC_GWS_OFFSET); @@ -2046,7 +2045,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) /* Sample channel registers */ regs->cim = sam_getdmach(xdmach, SAM_XDMACH_CIM_OFFSET); - regs->cis = sam_getdmach(xdmach, SAM_XDMACH_CIS_OFFSET); regs->csa = sam_getdmach(xdmach, SAM_XDMACH_CSA_OFFSET); regs->cda = sam_getdmach(xdmach, SAM_XDMACH_CDA_OFFSET); regs->cnda = sam_getdmach(xdmach, SAM_XDMACH_CNDA_OFFSET); @@ -2085,14 +2083,12 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, dmadbg(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg); dmadbg(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac); dmadbg(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim); - dmadbg(" GIS[%08x]: %08x\n", SAM_XDMAC_GIS, regs->gis); dmadbg(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs); dmadbg(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs); dmadbg(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws); dmadbg(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws); dmadbg(" DMA Channel Registers:\n"); dmadbg(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); - dmadbg(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis); dmadbg(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); dmadbg(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); dmadbg(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h index d11913f3cf..fe98581d08 100644 --- a/arch/arm/src/samv7/sam_xdmac.h +++ b/arch/arm/src/samv7/sam_xdmac.h @@ -175,22 +175,30 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); #ifdef CONFIG_DEBUG_DMA struct sam_dmaregs_s { - /* Global Registers */ + /* Global Registers. + * + * This includes all readable global XDMAC registers except for the global + * interrupt status register (XDMAC_GIS). Reading from the status + * register could cause loss of interrupts. + */ uint32_t gtype; /* Global Type Register */ uint32_t gcfg; /* Global Configuration Register */ uint32_t gwac; /* Global Weighted Arbiter Configuration Register */ uint32_t gim; /* Global Interrupt Mask Register */ - uint32_t gis; /* Global Interrupt Status Register */ uint32_t gs; /* Global Channel Status Register */ uint32_t grs; /* Global Channel Read Suspend Register */ uint32_t gws; /* Global Channel Write Suspend Register */ uint32_t gsws; /* Global Channel Software Request Status Register */ - /* Channel Registers */ + /* Channel Registers + * + * This includes all readable XDMAC channel registers except for the + * channel interrupt status register (XDMAC_CIS). Reading from the status + * register could cause loss of interrupts. + */ uint32_t cim; /* Channel Interrupt Mask Register */ - uint32_t cis; /* Channel Interrupt Status Register */ uint32_t csa; /* Channel Source Address Register */ uint32_t cda; /* Channel Destination Address Register */ uint32_t cnda; /* Channel Next Descriptor Address Register */ From 612ebdeabd5d9d74b1c57e36ef2e0090d74ed8fd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 8 Nov 2015 06:59:35 -0600 Subject: [PATCH 41/41] Kconfig: Set default number of MPU regions to 16 for Cortex-M7 --- arch/arm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2ba434667d..dd6ce83af0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -426,7 +426,8 @@ config ARMV7M_MPU config ARMV7M_MPU_NREGIONS int "Number of MPU regions" - default 8 + default 16 if ARCH_CORTEXM7 + default 8 if !ARCH_CORTEXM7 depends on ARMV7M_MPU ---help--- This is the number of protection regions supported by the MPU.