Changes to support fully write protecting the backup domain. N.B. stm32_pwr_enablebkp did not account for the delay from enable to the domain being writable. The KISS solution is a up_udelay. A more complex solution would be a negated write test with restore. From David Sidrane.
This commit is contained in:
Gregory Nutt
parent
2d91128111
commit
7d43cf2087
@ -2,7 +2,7 @@
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* arch/arm/src/stm32/stm32_pwr.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
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* Authors: Uros Platise <uros.platise@isotel.eu>
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* Gregory Nutt <gnutt@nuttx.org>
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*
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@ -43,6 +43,7 @@
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#include <nuttx/arch.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include "up_arch.h"
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@ -85,16 +86,64 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
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* and backup SRAM).
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*
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* Input Parameters:
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* None
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* protect - sets the write protections
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebkp(void)
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void stm32_pwr_enablebkp(bool writable)
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{
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stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP);
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uint16_t regval;
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/* Enable or disable the ability to write*/
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regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
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regval &= ~PWR_CR_DBP;
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regval |= writable ? PWR_CR_DBP : 0;
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stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
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if (writable)
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{
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/* Enable does not happen right away */
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up_udelay(4);
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}
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}
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/************************************************************************************
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* Name: stm32_pwr_enablebreg
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*
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* Description:
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* Enables the Backup regulator, the Backup regulator (used to maintain backup
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* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
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* regulator is switched off. The backup SRAM can still be used but its content will
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* be lost in the Standby and VBAT modes. Once set, the application must wait that
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* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
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* into the RAM will be maintained in the Standby and VBAT modes.
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*
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* Input Parameters:
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* regon - state to set it to
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebreg(bool regon)
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{
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uint16_t regval;
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regval = stm32_pwr_getreg(STM32_PWR_CSR_OFFSET);
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regval &= ~PWR_CSR_BRE;
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regval |= regon ? PWR_CSR_BRE : 0;
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stm32_pwr_putreg(STM32_PWR_CSR_OFFSET, regval);
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if (regon)
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{
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while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_BRR) == 0);
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}
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}
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/************************************************************************************
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_pwr.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -42,6 +42,8 @@
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include "chip.h"
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#include "chip/stm32_pwr.h"
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@ -54,7 +56,8 @@
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C" {
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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@ -71,14 +74,35 @@ extern "C" {
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* and backup SRAM).
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*
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* Input Parameters:
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* None
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* writable - sets the write protections
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebkp(void);
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void stm32_pwr_enablebkp(bool writable);
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/************************************************************************************
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* Name: stm32_pwr_enablebreg
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*
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* Description:
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* Enables the Backup regulator, the Backup regulator (used to maintain backup
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* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
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* regulator is switched off. The backup SRAM can still be used but its content will
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* be lost in the Standby and VBAT modes. Once set, the application must wait that
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* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
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* into the RAM will be maintained in the Standby and VBAT modes.
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*
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* Input Parameters:
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* regon - state to set it to
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebreg(bool regon);
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/************************************************************************************
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* Name: stm32_pwr_setvos
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@ -39,6 +39,7 @@
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <time.h>
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#include <errno.h>
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#include <debug.h>
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@ -219,6 +220,12 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
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static void rtc_wprunlock(void)
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{
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/* Enable write access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(true);
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/* The following steps are required to unlock the write protection on all the
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* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
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*
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@ -251,6 +258,12 @@ static inline void rtc_wprlock(void)
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/* Writing any wrong key reactivates the write protection. */
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putreg32(0xff, STM32_RTC_WPR);
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/* Disable write access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*/
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stm32_pwr_enablebkp(false);
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}
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/************************************************************************************
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@ -569,15 +582,15 @@ static int rtc_resume(void)
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#endif
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int ret;
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/* Wait for the RTC Time and Date registers to be syncrhonized with RTC APB
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/* Wait for the RTC Time and Date registers to be synchronized with RTC APB
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* clock.
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*/
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ret = rtc_synchwait();
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#ifdef CONFIG_RTC_ALARM
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/* Clear the RTC alarm flags */
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#ifdef CONFIG_RTC_ALARM
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regval = getreg32(STM32_RTC_ISR);
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regval &= ~(RTC_ISR_ALRAF|RTC_ISR_ALRBF);
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putreg32(regval, STM32_RTC_ISR);
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@ -645,11 +658,6 @@ int up_rtcinitialize(void)
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* maximum performance.
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*/
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/* Enable access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*/
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stm32_pwr_enablebkp();
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rtc_dumpregs("On reset");
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/* Enable the External Low-Speed (LSE) Oscillator setup the LSE as the RTC clock
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@ -677,6 +685,12 @@ int up_rtcinitialize(void)
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ret = rtc_setup();
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/* Enable write access to the backup domain (RTC registers, RTC
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* backup data registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(true);
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/* Remember that the RTC is initialized */
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putreg32(RTC_MAGIC, STM32_RTC_BK0R);
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@ -710,9 +724,16 @@ int up_rtcinitialize(void)
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}
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while (ret != OK && ++nretry < maxretry);
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/* Disable write access to the backup domain (RTC registers, RTC backup
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* data registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(false);
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if (ret != OK && nretry > 0)
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{
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rtclldbg("setup/resume ran %d times and failed with %d\n", nretry, ret);
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rtclldbg("setup/resume ran %d times and failed with %d\n",
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nretry, ret);
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return -ETIMEDOUT;
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}
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@ -1030,4 +1051,3 @@ int stm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
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#endif
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#endif /* CONFIG_RTC */
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@ -6,7 +6,7 @@
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*
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* With extensions, modifications by:
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*
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* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved.
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* Author: Gregroy Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -164,7 +164,7 @@ static alarmcb_t g_alarmcb;
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* Public Data
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************************************************************************************/
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/* Variable determines the state of the LSE oscilator.
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/* Variable determines the state of the LSE oscillator.
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* Possible errors:
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* - on start-up
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* - during operation, reported by LSE interrupt
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@ -358,12 +358,17 @@ static int stm32_rtc_interrupt(int irq, void *context)
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int up_rtcinitialize(void)
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{
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/* Set access to the peripheral, enable the backup domain (BKP) and the lower power
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* extern 32,768Hz (Low-Speed External, LSE) oscillator. Configure the LSE to
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* drive the RTC.
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/* Enable write access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(true);
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/* Set access to the peripheral, enable the backup domain (BKP) and the lower
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* power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the
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* LSE to drive the RTC.
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*/
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stm32_pwr_enablebkp();
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stm32_rcc_enablelse();
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/* TODO: Get state from this function, if everything is
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@ -397,12 +402,19 @@ int up_rtcinitialize(void)
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{
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up_waste();
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}
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modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE);
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/* Alarm Int via EXTI Line */
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/* STM32_IRQ_RTCALRM 41: RTC alarm through EXTI line interrupt */
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/* Disable write access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(false);
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return OK;
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}
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@ -434,7 +446,7 @@ time_t up_rtc_time(void)
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/* The RTC counter is read from two 16-bit registers to form one 32-bit
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* value. Because these are non-atomic operations, many things can happen
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* between the two reads: This thread could get suspended or interrrupted
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* between the two reads: This thread could get suspended or interrupted
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* or the lower 16-bit counter could rollover between reads. Disabling
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* interrupts will prevent suspensions and interruptions:
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*/
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@ -502,7 +514,7 @@ int up_rtc_gettime(FAR struct timespec *tp)
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/* The RTC counter is read from two 16-bit registers to form one 32-bit
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* value. Because these are non-atomic operations, many things can happen
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* between the two reads: This thread could get suspended or interrrupted
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* between the two reads: This thread could get suspended or interrupted
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* or the lower 16-bit counter could rollover between reads. Disabling
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* interrupts will prevent suspensions and interruptions:
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*/
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@ -643,6 +655,7 @@ int stm32_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
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ret = OK;
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}
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return ret;
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}
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#endif
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@ -684,6 +697,7 @@ int stm32_rtc_cancelalarm(void)
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ret = OK;
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}
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return ret;
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}
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#endif
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