Check return from nxsem_wait_uninterruptible()

Resolution of Issue 619 will require multiple steps, this part of the first step in that resolution:  Every call to nxsem_wait_uninterruptible() must handle the return value from nxsem_wait_uninterruptible properly.  This commit is for all USB host drivers under arch/.

arch/arm/src/efm32/hardware/efm32_usb.h

@@ -75,6 +75,7 @@
 /*******************************************************************************************************************************
  * Pre-processor Definitions
  *******************************************************************************************************************************/
+
 /* General definitions */
 
 #define EFM32_USB_EPTYPE_CTRL                      (0)      /* Control */
@@ -130,7 +131,7 @@
 #define EFM32_USB_HAINTMSK_OFFSET                  0x3c418  /* Host All Channels Interrupt Mask Register */
 #define EFM32_USB_HPRT_OFFSET                      0x3c440  /* Host Port Control and Status Register */
 
-#define EFM32_USB_HCn_OFFSET(n)                    (0x3c500 + ((n) << 5))
+#define EFM32_USB_HC_OFFSET(n)                     (0x3c500 + ((n) << 5))
 #define EFM32_USB_HC0_OFFSET                       0x3c500  /* Host Channel 0 Offset */
 #define EFM32_USB_HC1_OFFSET                       0x3c520  /* Host Channel 1 Offset */
 #define EFM32_USB_HC2_OFFSET                       0x3c540  /* Host Channel 2 Offset */
@@ -146,11 +147,11 @@
 #define EFM32_USB_HC12_OFFSET                      0x3c680  /* Host Channel 12 Offset */
 #define EFM32_USB_HC13_OFFSET                      0x3c6a0  /* Host Channel 13 Offset */
 
-#define EFM32_USB_HCn_CHAR_OFFSET                  0x00000  /* Host Channel n Characteristics Register */
-#define EFM32_USB_HCn_INT_OFFSET                   0x00008  /* Host Channel n Interrupt Register */
-#define EFM32_USB_HCn_INTMSK_OFFSET                0x0000c  /* Host Channel n Interrupt Mask Register */
-#define EFM32_USB_HCn_TSIZ_OFFSET                  0x00010  /* Host Channel n Transfer Size Register */
-#define EFM32_USB_HCn_DMAADDR_OFFSET               0x00014  /* Host Channel n DMA Address Register */
+#define EFM32_USB_HC_CHAR_OFFSET                   0x00000  /* Host Channel n Characteristics Register */
+#define EFM32_USB_HC_INT_OFFSET                    0x00008  /* Host Channel n Interrupt Register */
+#define EFM32_USB_HC_INTMSK_OFFSET                 0x0000c  /* Host Channel n Interrupt Mask Register */
+#define EFM32_USB_HC_TSIZ_OFFSET                   0x00010  /* Host Channel n Transfer Size Register */
+#define EFM32_USB_HC_DMAADDR_OFFSET                0x00014  /* Host Channel n DMA Address Register */
 
 #define EFM32_USB_DCFG_OFFSET                      0x3c800  /* Device Configuration Register */
 #define EFM32_USB_DCTL_OFFSET                      0x3c804  /* Device Control Register */
@@ -334,7 +335,7 @@
 #define EFM32_USB_HAINTMSK                         (EFM32_USB_BASE+EFM32_USB_HAINTMSK_OFFSET)
 #define EFM32_USB_HPRT                             (EFM32_USB_BASE+EFM32_USB_HPRT_OFFSET)
 
-#define EFM32_USB_HCn_BASE(n)                      (EFM32_USB_BASE+EFM32_USB_HCn_OFFSET(n))
+#define EFM32_USB_HC_BASE(n)                       (EFM32_USB_BASE+EFM32_USB_HC_OFFSET(n))
 #define EFM32_USB_HC0_BASE                         (EFM32_USB_BASE+EFM32_USB_HC0_OFFSET)
 #define EFM32_USB_HC1_BASE                         (EFM32_USB_BASE+EFM32_USB_HC1_OFFSET)
 #define EFM32_USB_HC2_BASE                         (EFM32_USB_BASE+EFM32_USB_HC2_OFFSET)
@@ -350,11 +351,11 @@
 #define EFM32_USB_HC12_BASE                        (EFM32_USB_BASE+EFM32_USB_HC12_OFFSET)
 #define EFM32_USB_HC13_BASE                        (EFM32_USB_BASE+EFM32_USB_HC13_OFFSET)
 
-#define EFM32_USB_HCn_CHAR(n)                      (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_CHAR_OFFSET)
-#define EFM32_USB_HCn_INT(n)                       (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_INT_OFFSET)
-#define EFM32_USB_HCn_INTMSK(n)                    (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_INTMSK_OFFSET)
-#define EFM32_USB_HCn_TSIZ(n)                      (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_TSIZ_OFFSET)
-#define EFM32_USB_HCn_DMAADDR(n)                   (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_DMAADDR_OFFSET)
+#define EFM32_USB_HC_CHAR(n)                       (EFM32_USB_HC_BASE(n)+EFM32_USB_HC_CHAR_OFFSET)
+#define EFM32_USB_HC_INT(n)                        (EFM32_USB_HC_BASE(n)+EFM32_USB_HC_INT_OFFSET)
+#define EFM32_USB_HC_INTMSK(n)                     (EFM32_USB_HC_BASE(n)+EFM32_USB_HC_INTMSK_OFFSET)
+#define EFM32_USB_HC_TSIZ(n)                       (EFM32_USB_HC_BASE(n)+EFM32_USB_HC_TSIZ_OFFSET)
+#define EFM32_USB_HC_DMAADDR(n)                    (EFM32_USB_HC_BASE(n)+EFM32_USB_HC_DMAADDR_OFFSET)
 
 #define EFM32_USB_DCFG                             (EFM32_USB_BASE+EFM32_USB_DCFG_OFFSET)
 #define EFM32_USB_DCTL                             (EFM32_USB_BASE+EFM32_USB_DCTL_OFFSET)

arch/arm/src/s32k1xx/s32k1xx_lpi2c.c

@@ -245,9 +245,6 @@ static inline void
                           uint32_t setbits);
 static inline int
   s32k1xx_lpi2c_sem_wait(FAR struct s32k1xx_lpi2c_priv_s *priv);
-static int
-  s32k1xx_lpi2c_sem_wait_uninterruptible(
-    FAR struct s32k1xx_lpi2c_priv_s *priv);
 
 #ifdef CONFIG_S32K1XX_I2C_DYNTIMEO
 static useconds_t
@@ -465,21 +462,6 @@ static inline int
   return nxsem_wait(&priv->sem_excl);
 }
 
-/****************************************************************************
- * Name: s32k1xx_lpi2c_sem_wait_uninterruptible
- *
- * Description:
- *   Take the exclusive access, waiting as necessary
- *
- ****************************************************************************/
-
-static int
-  s32k1xx_lpi2c_sem_wait_uninterruptible(
-    FAR struct s32k1xx_lpi2c_priv_s *priv)
-{
-  return nxsem_wait_uninterruptible(&priv->sem_excl);
-}
-
 /****************************************************************************
  * Name: s32k1xx_lpi2c_tousecs
  *
@@ -1705,7 +1687,7 @@ static int s32k1xx_lpi2c_reset(FAR struct i2c_master_s *dev)
 
   /* Lock out other clients */
 
-  ret = s32k1xx_lpi2c_sem_wait_uninterruptible(priv);
+  ret = s32k1xx_lpi2c_sem_wait(priv);
   if (ret < 0)
     {
       return ret;

arch/arm/src/sama5/sam_twi.c

@@ -182,7 +182,6 @@ struct twi_dev_s
 /* Low-level helper functions */
 
 static int  twi_takesem(sem_t *sem);
-static int  twi_takesem_uninterruptible(sem_t *sem);
 #define     twi_givesem(sem) (nxsem_post(sem))
 
 #ifdef CONFIG_SAMA5_TWI_REGDEBUG
@@ -317,26 +316,6 @@ static int twi_takesem(sem_t *sem)
   return nxsem_wait(sem);
 }
 
-/****************************************************************************
- * Name: twi_takesem_uninterruptible
- *
- * Description:
- *   Take the wait semaphore (handling false alarm wake-ups due to the
- *   receipt of signals).
- *
- * Input Parameters:
- *   dev - Instance of the SDIO device driver state structure.
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-static int twi_takesem_uninterruptible(sem_t *sem)
-{
-  return nxsem_wait_uninterruptible(sem);
-}
-
 /****************************************************************************
  * Name: twi_checkreg
  *
@@ -902,7 +881,7 @@ static int twi_reset(FAR struct i2c_master_s *dev)
 
   /* Get exclusive access to the TWI device */
 
-  ret = twi_takesem_uninterruptible(&priv->exclsem);
+  ret = twi_takesem(&priv->exclsem);
   if (ret < 0)
     {
       return ret;