Merged in paulpatience/nuttx/stm32_can (pull request #29)
STM32 CAN: Add support for both RX FIFOs
This commit is contained in:
Gregory Nutt
commit
7de267645e
@ -75,8 +75,11 @@
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#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
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#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
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#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
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#define STM32_CAN_RFR_OFFSET(m) (0x000c+((m)<<2))
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#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
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#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
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#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
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#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
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#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
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@ -127,8 +130,8 @@
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#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
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#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
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/* There are 14 or 28 filter banks (depending) on the device. Each filter bank is
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* composed of two 32-bit registers, CAN_FiR:
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/* There are 14 or 28 filter banks (depending) on the device.
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* Each filter bank is composed of two 32-bit registers, CAN_FiR:
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* F0R1 Offset 0x240
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* F0R2 Offset 0x244
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* F1R1 Offset 0x248
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@ -4,6 +4,9 @@
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* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
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* Author: Paul Alexander Patience <paul-a.patience@polymtl.ca>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -104,7 +107,7 @@
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struct stm32_can_s
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{
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uint8_t port; /* CAN port number (1 or 2) */
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uint8_t canrx0; /* CAN RX FIFO 0 IRQ number */
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uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */
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uint8_t cantx; /* CAN TX IRQ number */
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uint8_t filter; /* Filter number */
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uint32_t base; /* Base address of the CAN control registers */
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@ -118,14 +121,19 @@ struct stm32_can_s
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/* CAN Register access */
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset);
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset);
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value);
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value);
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static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset);
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static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset);
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static void can_putreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value);
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static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value);
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_dumpctrlregs(struct stm32_can_s *priv, FAR const char *msg);
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static void can_dumpmbregs(struct stm32_can_s *priv, FAR const char *msg);
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static void can_dumpfiltregs(struct stm32_can_s *priv, FAR const char *msg);
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static void can_dumpctrlregs(FAR struct stm32_can_s *priv,
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FAR const char *msg);
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static void can_dumpmbregs(FAR struct stm32_can_s *priv,
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FAR const char *msg);
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static void can_dumpfiltregs(FAR struct stm32_can_s *priv,
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FAR const char *msg);
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#else
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# define can_dumpctrlregs(priv,msg)
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# define can_dumpmbregs(priv,msg)
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@ -147,14 +155,16 @@ static bool can_txempty(FAR struct can_dev_s *dev);
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/* CAN interrupt handling */
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static int can_rx0interrupt(int irq, void *context);
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static int can_txinterrupt(int irq, void *context);
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static int can_rxinterrupt(int irq, FAR void *context, int rxmb);
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static int can_rx0interrupt(int irq, FAR void *context);
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static int can_rx1interrupt(int irq, FAR void *context);
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static int can_txinterrupt(int irq, FAR void *context);
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/* Initialization */
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static int can_bittiming(struct stm32_can_s *priv);
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static int can_cellinit(struct stm32_can_s *priv);
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static int can_filterinit(struct stm32_can_s *priv);
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static int can_bittiming(FAR struct stm32_can_s *priv);
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static int can_cellinit(FAR struct stm32_can_s *priv);
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static int can_filterinit(FAR struct stm32_can_s *priv);
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/****************************************************************************
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* Private Data
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@ -178,7 +188,11 @@ static const struct can_ops_s g_canops =
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static struct stm32_can_s g_can1priv =
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{
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.port = 1,
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.canrx0 = STM32_IRQ_CAN1RX0,
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.canrx =
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{
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STM32_IRQ_CAN1RX0,
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STM32_IRQ_CAN1RX1,
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},
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.cantx = STM32_IRQ_CAN1TX,
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.filter = 0,
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.base = STM32_CAN1_BASE,
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@ -197,7 +211,11 @@ static struct can_dev_s g_can1dev =
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static struct stm32_can_s g_can2priv =
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{
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.port = 2,
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.canrx0 = STM32_IRQ_CAN2RX0,
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.canrx =
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{
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STM32_IRQ_CAN2RX0,
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STM32_IRQ_CAN2RX1,
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},
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.cantx = STM32_IRQ_CAN2TX,
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.filter = CAN_NFILTERS / 2,
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.base = STM32_CAN2_BASE,
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@ -285,23 +303,23 @@ static uint32_t can_vgetreg(uint32_t addr)
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return val;
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}
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset)
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{
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return can_vgetreg(priv->base + offset);
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}
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset)
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static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
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{
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return can_vgetreg(priv->fbase + offset);
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}
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#else
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset)
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{
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return getreg32(priv->base + offset);
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}
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset)
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static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
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{
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return getreg32(priv->fbase + offset);
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}
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@ -338,23 +356,27 @@ static void can_vputreg(uint32_t addr, uint32_t value)
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putreg32(value, addr);
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}
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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static void can_putreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value)
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{
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can_vputreg(priv->base + offset, value);
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}
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value)
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static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value)
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{
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can_vputreg(priv->fbase + offset, value);
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}
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#else
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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static void can_putreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value)
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static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
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uint32_t value)
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{
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putreg32(value, priv->fbase + offset);
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}
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@ -375,7 +397,8 @@ static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value)
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****************************************************************************/
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_dumpctrlregs(struct stm32_can_s *priv, FAR const char *msg)
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static void can_dumpctrlregs(FAR struct stm32_can_s *priv,
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FAR const char *msg)
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{
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if (msg)
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{
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@ -419,7 +442,8 @@ static void can_dumpctrlregs(struct stm32_can_s *priv, FAR const char *msg)
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****************************************************************************/
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_dumpmbregs(struct stm32_can_s *priv, FAR const char *msg)
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static void can_dumpmbregs(FAR struct stm32_can_s *priv,
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FAR const char *msg)
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{
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if (msg)
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{
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@ -479,7 +503,8 @@ static void can_dumpmbregs(struct stm32_can_s *priv, FAR const char *msg)
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****************************************************************************/
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_dumpfiltregs(struct stm32_can_s *priv, FAR const char *msg)
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static void can_dumpfiltregs(FAR struct stm32_can_s *priv,
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FAR const char *msg)
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{
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int i;
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@ -553,8 +578,8 @@ static void can_reset(FAR struct can_dev_s *dev)
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return;
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}
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/* Disable interrupts momentary to stop any ongoing CAN event processing and
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* to prevent any concurrent access to the AHB1RSTR register.
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/* Disable interrupts momentarily to stop any ongoing CAN event processing
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* and to prevent any concurrent access to the AHB1RSTR register.
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*/
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flags = enter_critical_section();
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@ -592,7 +617,8 @@ static int can_setup(FAR struct can_dev_s *dev)
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FAR struct stm32_can_s *priv = dev->cd_priv;
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int ret;
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canllvdbg("CAN%d RX0 irq: %d TX irq: %d\n", priv->port, priv->canrx0, priv->cantx);
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canllvdbg("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
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priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
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/* CAN cell initialization */
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@ -616,19 +642,31 @@ static int can_setup(FAR struct can_dev_s *dev)
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}
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can_dumpfiltregs(priv, "After filter initialization");
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/* Attach the CAN RX FIFO 0 interrupt and TX interrupts. The others are not used */
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/* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts.
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* The others are not used.
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*/
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ret = irq_attach(priv->canrx0, can_rx0interrupt);
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ret = irq_attach(priv->canrx[0], can_rx0interrupt);
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if (ret < 0)
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{
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canlldbg("Failed to attach CAN%d RX0 IRQ (%d)", priv->port, priv->canrx0);
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canlldbg("Failed to attach CAN%d RX0 IRQ (%d)",
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priv->port, priv->canrx[0]);
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return ret;
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}
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ret = irq_attach(priv->canrx[1], can_rx1interrupt);
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if (ret < 0)
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{
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canlldbg("Failed to attach CAN%d RX1 IRQ (%d)",
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priv->port, priv->canrx[1]);
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return ret;
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}
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ret = irq_attach(priv->cantx, can_txinterrupt);
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if (ret < 0)
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{
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canlldbg("Failed to attach CAN%d TX IRQ (%d)", priv->port, priv->cantx);
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canlldbg("Failed to attach CAN%d TX IRQ (%d)",
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priv->port, priv->cantx);
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return ret;
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}
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@ -637,7 +675,8 @@ static int can_setup(FAR struct can_dev_s *dev)
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* no pending interrupts.
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*/
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up_enable_irq(priv->canrx0);
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up_enable_irq(priv->canrx[0]);
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up_enable_irq(priv->canrx[1]);
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up_enable_irq(priv->cantx);
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return OK;
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}
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@ -663,14 +702,16 @@ static void can_shutdown(FAR struct can_dev_s *dev)
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canllvdbg("CAN%d\n", priv->port);
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/* Disable the RX FIFO 0 and TX interrupts */
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/* Disable the RX FIFO 0/1 and TX interrupts */
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up_disable_irq(priv->canrx0);
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up_disable_irq(priv->canrx[0]);
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up_disable_irq(priv->canrx[1]);
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up_disable_irq(priv->cantx);
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/* Detach the RX FIFO 0 and TX interrupts */
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/* Detach the RX FIFO 0/1 and TX interrupts */
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irq_detach(priv->canrx0);
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irq_detach(priv->canrx[0]);
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irq_detach(priv->canrx[1]);
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irq_detach(priv->cantx);
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/* And reset the hardware */
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@ -699,16 +740,16 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
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canllvdbg("CAN%d enable: %d\n", priv->port, enable);
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/* Enable/disable the FIFO 0 message pending interrupt */
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/* Enable/disable the FIFO 0/1 message pending interrupt */
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regval = can_getreg(priv, STM32_CAN_IER_OFFSET);
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if (enable)
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{
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regval |= CAN_IER_FMPIE0;
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regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1;
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}
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else
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{
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regval &= ~CAN_IER_FMPIE0;
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regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1);
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}
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can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
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}
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@ -817,7 +858,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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int dlc;
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int txmb;
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canllvdbg("CAN%d ID: %d DLC: %d\n", priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
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canllvdbg("CAN%d ID: %d DLC: %d\n",
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priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
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/* Select one empty transmit mailbox */
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@ -843,7 +885,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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/* Clear TXRQ, RTR, IDE, EXID, and STID fields */
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regval = can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
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regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK);
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regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE |
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CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK);
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can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
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/* Set up the ID, standard 11-bit or extended 29-bit. */
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@ -970,11 +1013,7 @@ static bool can_txready(FAR struct can_dev_s *dev)
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regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
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canllvdbg("CAN%d TSR: %08x\n", priv->port, regval);
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if ((regval & CAN_ALL_MAILBOXES) != 0)
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{
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return true;
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}
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return false;
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return (regval & CAN_ALL_MAILBOXES) != 0;
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}
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/****************************************************************************
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@ -1005,29 +1044,26 @@ static bool can_txempty(FAR struct can_dev_s *dev)
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regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
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canllvdbg("CAN%d TSR: %08x\n", priv->port, regval);
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if ((regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES)
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{
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return true;
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}
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return false;
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return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
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}
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/****************************************************************************
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* Name: can_rx0interrupt
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* Name: can_rxinterrupt
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*
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* Description:
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* CAN RX FIFO 0 interrupt handler
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* CAN RX FIFO 0/1 interrupt handler
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*
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* Input Parameters:
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* irq - The IRQ number of the interrupt.
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* context - The register state save array at the time of the interrupt.
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* rxmb - The RX mailbox number.
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*
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* Returned Value:
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* Zero on success; a negated errno on failure
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*
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****************************************************************************/
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static int can_rx0interrupt(int irq, void *context)
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static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
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{
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FAR struct can_dev_s *dev = NULL;
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FAR struct stm32_can_s *priv;
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@ -1038,11 +1074,11 @@ static int can_rx0interrupt(int irq, void *context)
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int ret;
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#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
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if (g_can1priv.canrx0 == irq)
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if (g_can1priv.canrx[rxmb] == irq)
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{
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dev = &g_can1dev;
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}
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else if (g_can2priv.canrx0 == irq)
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else if (g_can2priv.canrx[rxmb] == irq)
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{
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dev = &g_can2dev;
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}
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@ -1057,9 +1093,9 @@ static int can_rx0interrupt(int irq, void *context)
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#endif
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priv = dev->cd_priv;
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/* Verify that a message is pending in FIFO 0 */
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/* Verify that a message is pending in the FIFO */
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regval = can_getreg(priv, STM32_CAN_RF0R_OFFSET);
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regval = can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
|
||||
npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT;
|
||||
if (npending < 1)
|
||||
{
|
||||
@ -1067,11 +1103,18 @@ static int can_rx0interrupt(int irq, void *context)
|
||||
return OK;
|
||||
}
|
||||
|
||||
if (rxmb == 0)
|
||||
{
|
||||
can_dumpmbregs(priv, "RX0 interrupt");
|
||||
}
|
||||
else
|
||||
{
|
||||
can_dumpmbregs(priv, "RX1 interrupt");
|
||||
}
|
||||
|
||||
/* Get the CAN identifier. */
|
||||
|
||||
regval = can_getreg(priv, STM32_CAN_RI0R_OFFSET);
|
||||
regval = can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb));
|
||||
|
||||
#ifdef CONFIG_CAN_EXTID
|
||||
if ((regval & CAN_RIR_IDE) != 0)
|
||||
@ -1104,22 +1147,22 @@ static int can_rx0interrupt(int irq, void *context)
|
||||
|
||||
/* Extract the RTR bit */
|
||||
|
||||
hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0 ? true : false;
|
||||
hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0;
|
||||
|
||||
/* Get the DLC */
|
||||
|
||||
regval = can_getreg(priv, STM32_CAN_RDT0R_OFFSET);
|
||||
regval = can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb));
|
||||
hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT;
|
||||
|
||||
/* Save the message data */
|
||||
|
||||
regval = can_getreg(priv, STM32_CAN_RDL0R_OFFSET);
|
||||
regval = can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb));
|
||||
data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT;
|
||||
data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT;
|
||||
data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT;
|
||||
data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT;
|
||||
|
||||
regval = can_getreg(priv, STM32_CAN_RDH0R_OFFSET);
|
||||
regval = can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb));
|
||||
data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT;
|
||||
data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT;
|
||||
data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT;
|
||||
@ -1129,17 +1172,57 @@ static int can_rx0interrupt(int irq, void *context)
|
||||
|
||||
ret = can_receive(dev, &hdr, data);
|
||||
|
||||
/* Release the FIFO0 */
|
||||
/* Release the FIFO */
|
||||
|
||||
#ifndef CONFIG_CAN_EXTID
|
||||
errout:
|
||||
#endif
|
||||
regval = can_getreg(priv, STM32_CAN_RF0R_OFFSET);
|
||||
regval = can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
|
||||
regval |= CAN_RFR_RFOM;
|
||||
can_putreg(priv, STM32_CAN_RF0R_OFFSET, regval);
|
||||
can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: can_rx0interrupt
|
||||
*
|
||||
* Description:
|
||||
* CAN RX FIFO 0 interrupt handler
|
||||
*
|
||||
* Input Parameters:
|
||||
* irq - The IRQ number of the interrupt.
|
||||
* context - The register state save array at the time of the interrupt.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_rx0interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return can_rxinterrupt(irq, context, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: can_rx1interrupt
|
||||
*
|
||||
* Description:
|
||||
* CAN RX FIFO 1 interrupt handler
|
||||
*
|
||||
* Input Parameters:
|
||||
* irq - The IRQ number of the interrupt.
|
||||
* context - The register state save array at the time of the interrupt.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_rx1interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return can_rxinterrupt(irq, context, 1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: can_txinterrupt
|
||||
*
|
||||
@ -1155,7 +1238,7 @@ errout:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_txinterrupt(int irq, void *context)
|
||||
static int can_txinterrupt(int irq, FAR void *context)
|
||||
{
|
||||
FAR struct can_dev_s *dev = NULL;
|
||||
FAR struct stm32_can_s *priv;
|
||||
@ -1304,7 +1387,7 @@ static int can_txinterrupt(int irq, void *context)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_bittiming(struct stm32_can_s *priv)
|
||||
static int can_bittiming(FAR struct stm32_can_s *priv)
|
||||
{
|
||||
uint32_t tmp;
|
||||
uint32_t brp;
|
||||
@ -1401,7 +1484,7 @@ static int can_bittiming(struct stm32_can_s *priv)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_cellinit(struct stm32_can_s *priv)
|
||||
static int can_cellinit(FAR struct stm32_can_s *priv)
|
||||
{
|
||||
volatile uint32_t timeout;
|
||||
uint32_t regval;
|
||||
@ -1415,11 +1498,6 @@ static int can_cellinit(struct stm32_can_s *priv)
|
||||
regval &= ~CAN_MCR_SLEEP;
|
||||
can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Configure CAN behavior. Priority driven request order, not message ID. */
|
||||
|
||||
regval |= CAN_MCR_TXFP;
|
||||
can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Enter initialization mode */
|
||||
|
||||
regval |= CAN_MCR_INRQ;
|
||||
@ -1457,7 +1535,8 @@ static int can_cellinit(struct stm32_can_s *priv)
|
||||
*/
|
||||
|
||||
regval = can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
|
||||
regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART |
|
||||
CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
|
||||
can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Configure bit timing. */
|
||||
@ -1492,7 +1571,8 @@ static int can_cellinit(struct stm32_can_s *priv)
|
||||
|
||||
if (timeout < 1)
|
||||
{
|
||||
canlldbg("ERROR: Timed out waiting to exit initialization mode: %08x\n", regval);
|
||||
canlldbg("ERROR: Timed out waiting to exit initialization mode: %08x\n",
|
||||
regval);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
return OK;
|
||||
@ -1531,7 +1611,7 @@ static int can_cellinit(struct stm32_can_s *priv)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int can_filterinit(struct stm32_can_s *priv)
|
||||
static int can_filterinit(FAR struct stm32_can_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t bitmask;
|
||||
@ -1540,7 +1620,7 @@ static int can_filterinit(struct stm32_can_s *priv)
|
||||
|
||||
/* Get the bitmask associated with the filter used by this CAN block */
|
||||
|
||||
bitmask = ((uint32_t)1) << priv->filter;
|
||||
bitmask = (uint32_t)1 << priv->filter;
|
||||
|
||||
/* Enter filter initialization mode */
|
||||
|
||||
@ -1548,6 +1628,17 @@ static int can_filterinit(struct stm32_can_s *priv)
|
||||
regval |= CAN_FMR_FINIT;
|
||||
can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
|
||||
|
||||
/* Assign half the filters to CAN1, half to CAN2 */
|
||||
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
|
||||
defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX)
|
||||
regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
|
||||
regval &= CAN_FMR_CAN2SB_MASK;
|
||||
regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT;
|
||||
can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
|
||||
#endif
|
||||
|
||||
/* Disable the filter */
|
||||
|
||||
regval = can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
|
||||
@ -1560,8 +1651,8 @@ static int can_filterinit(struct stm32_can_s *priv)
|
||||
regval |= bitmask;
|
||||
can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval);
|
||||
|
||||
/* There are 14 or 28 filter banks (depending) on the device. Each filter bank is
|
||||
* composed of two 32-bit registers, CAN_FiR:
|
||||
/* There are 14 or 28 filter banks (depending) on the device.
|
||||
* Each filter bank is composed of two 32-bit registers, CAN_FiR:
|
||||
*/
|
||||
|
||||
can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0);
|
||||
@ -1613,7 +1704,7 @@ static int can_filterinit(struct stm32_can_s *priv)
|
||||
|
||||
FAR struct can_dev_s *stm32_caninitialize(int port)
|
||||
{
|
||||
struct can_dev_s *dev = NULL;
|
||||
FAR struct can_dev_s *dev = NULL;
|
||||
|
||||
canvdbg("CAN%d\n", port);
|
||||
|
||||
@ -1662,4 +1753,3 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user