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configs/makerlisp: Update external memory settings in linker script.

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This commit is contained in:
Gregory Nutt 2019-06-16 10:22:57 -06:00
parent cad6325589
commit 7e05bacd54
5 changed files with 183 additions and 195 deletions
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18
arch/z80/src/ez80/ez80_clock.c
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@ -43,23 +43,7 @@
#include "arch/board/board.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Data
* Public Data
****************************************************************************/
uint32_t ez80_systemclock = EZ80_SYS_CLK_FREQ;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

4
arch/z80/src/ez80/ez80_startup.asm
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@ -77,7 +77,7 @@
;**************************************************************************
_ez80_startup:
; Set up the stack pointer at the location determined the lincmd
; Set up the stack pointer at the location determined the linkcmd
; file
ld sp, __stack
@ -122,7 +122,7 @@ _ez80_bssdone:
jr z, _ez80_datadone ; __len_data is zero-length ...
ld hl, __low_romdata ; [hl] = data_copy
ld de, __low_data ; [de] = data
ldir ; Copy the data section
ldir ; Copy the data section
_ez80_datadone:
; Copy CODE (which may be in FLASH) to RAM if the

168
arch/z80/src/ez80/ez80_vectors.asm
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@ -134,8 +134,8 @@ _nmi:
; Interrupt Vector Handling
;**************************************************************************
; Symbol Val VecNo Addr
;----------------- --- ----- -----
; Symbol Val VecNo Addr
;----------------- --- ----- -----
_ez80_handlers:
irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040
handlersize equ $-_ez80_handlers
@ -147,8 +147,8 @@ _ez80_handlers:
irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058
irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c
irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060
irqhandler EZ80_UNUSED ; 9 0x064
irqhandler EZ80_UNUSED+1 ; 10 0x068
irqhandler EZ80_UNUSED ; 9 0x064
irqhandler EZ80_UNUSED+1 ; 10 0x068
irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C
irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070
irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074
@ -186,22 +186,22 @@ _ez80_handlers:
irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4
irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8
irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc
irqhandler EZ80_UNUSED+1 ; 48 0x100
irqhandler EZ80_UNUSED+2 ; 49 0x104
irqhandler EZ80_UNUSED+3 ; 50 0x108
irqhandler EZ80_UNUSED+4 ; 51 0x10c
irqhandler EZ80_UNUSED+5 ; 52 0x110
irqhandler EZ80_UNUSED+6 ; 53 0x114
irqhandler EZ80_UNUSED+7 ; 54 0x118
irqhandler EZ80_UNUSED+8 ; 55 0x11c
irqhandler EZ80_UNUSED+9 ; 56 0x120
irqhandler EZ80_UNUSED+10 ; 57 0x124
irqhandler EZ80_UNUSED+11 ; 58 0x128
irqhandler EZ80_UNUSED+12 ; 59 0x12c
irqhandler EZ80_UNUSED+13 ; 60 0x130
irqhandler EZ80_UNUSED+14 ; 61 0x134
irqhandler EZ80_UNUSED+15 ; 62 0x138
irqhandler EZ80_UNUSED+16 ; 63 0x13c
irqhandler EZ80_UNUSED+1 ; 48 0x100
irqhandler EZ80_UNUSED+2 ; 49 0x104
irqhandler EZ80_UNUSED+3 ; 50 0x108
irqhandler EZ80_UNUSED+4 ; 51 0x10c
irqhandler EZ80_UNUSED+5 ; 52 0x110
irqhandler EZ80_UNUSED+6 ; 53 0x114
irqhandler EZ80_UNUSED+7 ; 54 0x118
irqhandler EZ80_UNUSED+8 ; 55 0x11c
irqhandler EZ80_UNUSED+9 ; 56 0x120
irqhandler EZ80_UNUSED+10 ; 57 0x124
irqhandler EZ80_UNUSED+11 ; 58 0x128
irqhandler EZ80_UNUSED+12 ; 59 0x12c
irqhandler EZ80_UNUSED+13 ; 60 0x130
irqhandler EZ80_UNUSED+14 ; 61 0x134
irqhandler EZ80_UNUSED+15 ; 62 0x138
irqhandler EZ80_UNUSED+16 ; 63 0x13c
;**************************************************************************
; Common Interrupt handler
@ -216,72 +216,72 @@ _ez80_rstcommon:
;
; IRQ number is in A
push hl ; Offset 6: HL
ld hl, #(3*3) ; HL is the value of the stack pointer before
add hl, sp ; the interrupt occurred (3 for PC, AF, HL)
push hl ; Offset 5: Stack pointer
push iy ; Offset 4: IY
push ix ; Offset 3: IX
push de ; Offset 2: DE
push bc ; Offset 1: BC
push hl ; Offset 6: HL
ld hl, #(3*3) ; HL is the value of the stack pointer before
add hl, sp ; the interrupt occurred (3 for PC, AF, HL)
push hl ; Offset 5: Stack pointer
push iy ; Offset 4: IY
push ix ; Offset 3: IX
push de ; Offset 2: DE
push bc ; Offset 1: BC
; At this point, we know that interrupts were enabled (or we wouldn't be here
; so we can save a fake indicationn that will cause interrupts to restored when
; so we can save a fake indication that will cause interrupts to restored when
; this context is restored
ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1
push bc ; Offset 0: I with interrupt state in parity
di ; (not necessary)
ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1
push bc ; Offset 0: I with interrupt state in parity
di ; (not necessary)
; Call the interrupt decode logic. SP points to the beggining of the reg structure
ld hl, #0 ; Argument #2 is the beginning of the reg structure
add hl, sp ;
push hl ; Place argument #2 at the top of stack
ld bc, #0 ; BC = reset number
ld c, a ; Save the reset number in C
push bc ; Argument #1 is the Reset number
call _z80_doirq ; Decode the IRQ
ld hl, #0 ; Argument #2 is the beginning of the reg structure
add hl, sp ;
push hl ; Place argument #2 at the top of stack
ld bc, #0 ; BC = reset number
ld c, a ; Save the reset number in C
push bc ; Argument #1 is the Reset number
call _z80_doirq ; Decode the IRQ
; On return, HL points to the beginning of the reg structure to restore
; Note that (1) the arguments pushed on the stack are not popped, and (2) the
; original stack pointer is lost. In the normal case (no context switch),
; HL will contain the value of the SP before the arguments were pushed.
ld sp, hl ; Use the new stack pointer
ld sp, hl ; Use the new stack pointer
; Restore registers. HL points to the beginning of the reg structure to restore
ex af, af' ; Select alternate AF
pop af ; Offset 0: AF' = I with interrupt state in parity
ex af, af' ; Restore original AF
pop bc ; Offset 1: BC
pop de ; Offset 2: DE
pop ix ; Offset 3: IX
pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL
pop hl ; Offset 5: HL' = Stack pointer after return
exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL
pop af ; Offset 7: AF
ex af, af' ; Select alternate AF
pop af ; Offset 0: AF' = I with interrupt state in parity
ex af, af' ; Restore original AF
pop bc ; Offset 1: BC
pop de ; Offset 2: DE
pop ix ; Offset 3: IX
pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL
pop hl ; Offset 5: HL' = Stack pointer after return
exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL
pop af ; Offset 7: AF
; Restore the stack pointer
exx ; Use alternate BC/DE/HL
pop de ; Offset 8: Return address
ld sp, hl ; Set SP = saved stack pointer value before return
push de ; Set up for reti
exx ; Restore original BC/DE/HL
exx ; Use alternate BC/DE/HL
pop de ; Offset 8: Return address
ld sp, hl ; Set SP = saved stack pointer value before return
push de ; Set up for reti
exx ; Restore original BC/DE/HL
; Restore interrupt state
ex af, af' ; Recover interrupt state
jp po, nointenable ; Odd parity, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes
ex af, af' ; Recover interrupt state
jp po, nointenable ; Odd parity, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes
reti
nointenable:
ex af, af' ; Restore AF
ex af, af' ; Restore AF
reti
;**************************************************************************
@ -291,37 +291,37 @@ nointenable:
_ez80_initvectors:
; Initialize the vector table
ld iy, _ez80_vectable
ld ix, 4
ld bc, 4
ld b, NVECTORS
xor a, a ; Clear carry
ld hl, handlersize
ld de, _ez80_handlers
sbc hl, de ; Length of irq handler in hl
ld d, h
ld e, l
ld hl, _ez80_handlers ; Start of handlers in hl
ld iy, _ez80_vectable
ld ix, 4
ld bc, 4
ld b, NVECTORS
xor a, a ; Clear carry
ld hl, handlersize
ld de, _ez80_handlers
sbc hl, de ; Length of irq handler in hl
ld d, h
ld e, l
ld hl, _ez80_handlers ; Start of handlers in hl
ld a, 0
ld a, 0
$1:
ld (iy), hl ; Store IRQ handler
ld (iy+3), a ; Pad to 4 bytes
add hl, de ; Point to next handler
ld (iy), hl ; Store IRQ handler
ld (iy+3), a ; Pad to 4 bytes
add hl, de ; Point to next handler
push de
ld de, 4
add iy, de ; Point to next entry in vector table
pop de
djnz $1 ; Loop until all vectors have been written
ld de, 4
add iy, de ; Point to next entry in vector table
pop de
djnz $1 ; Loop until all vectors have been written
; Select interrupt mode 2
im 2 ; Interrupt mode 2
im 2 ; Interrupt mode 2
; Write the address of the vector table into the interrupt vector base
ld hl, _ez80_vectable >> 8
ld i, hl
ld hl, _ez80_vectable >> 8
ld i, hl
ret
;**************************************************************************

146
arch/z80/src/ez80/ez80f91_init.asm
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@ -78,35 +78,35 @@ PLL_ENABLE EQU %01
;**************************************************************************
; Exported symbols
xdef _ez80_init
xdef _ez80_initsysclk
xdef _ez80_init
xdef _ez80_initsysclk
; Imported symbols
xref __CS0_LBR_INIT_PARAM
xref __CS0_UBR_INIT_PARAM
xref __CS0_CTL_INIT_PARAM
xref __CS1_LBR_INIT_PARAM
xref __CS1_UBR_INIT_PARAM
xref __CS1_CTL_INIT_PARAM
xref __CS2_LBR_INIT_PARAM
xref __CS2_UBR_INIT_PARAM
xref __CS2_CTL_INIT_PARAM
xref __CS3_LBR_INIT_PARAM
xref __CS3_UBR_INIT_PARAM
xref __CS3_CTL_INIT_PARAM
xref __CS0_BMC_INIT_PARAM
xref __CS1_BMC_INIT_PARAM
xref __CS2_BMC_INIT_PARAM
xref __CS3_BMC_INIT_PARAM
xref __FLASH_CTL_INIT_PARAM
xref __FLASH_ADDR_U_INIT_PARAM
xref __RAM_CTL_INIT_PARAM
xref __RAM_ADDR_U_INIT_PARAM
xref _SYS_CLK_SRC
xref _SYS_CLK_FREQ
xref _OSC_FREQ
xref _OSC_FREQ_MULT
xref __PLL_CTL0_INIT_PARAM
xref __CS0_LBR_INIT_PARAM
xref __CS0_UBR_INIT_PARAM
xref __CS0_CTL_INIT_PARAM
xref __CS1_LBR_INIT_PARAM
xref __CS1_UBR_INIT_PARAM
xref __CS1_CTL_INIT_PARAM
xref __CS2_LBR_INIT_PARAM
xref __CS2_UBR_INIT_PARAM
xref __CS2_CTL_INIT_PARAM
xref __CS3_LBR_INIT_PARAM
xref __CS3_UBR_INIT_PARAM
xref __CS3_CTL_INIT_PARAM
xref __CS0_BMC_INIT_PARAM
xref __CS1_BMC_INIT_PARAM
xref __CS2_BMC_INIT_PARAM
xref __CS3_BMC_INIT_PARAM
xref __FLASH_CTL_INIT_PARAM
xref __FLASH_ADDR_U_INIT_PARAM
xref __RAM_CTL_INIT_PARAM
xref __RAM_ADDR_U_INIT_PARAM
xref _SYS_CLK_SRC
xref _SYS_CLK_FREQ
xref _OSC_FREQ
xref _OSC_FREQ_MULT
xref __PLL_CTL0_INIT_PARAM
;**************************************************************************
; Chip-specific initialization logic
@ -120,12 +120,12 @@ PLL_ENABLE EQU %01
_ez80_init:
; Disable internal peripheral interrupt sources
ld a, %ff
out0 (PA_DDR), a ; GPIO
ld a, %ff
out0 (PA_DDR), a ; GPIO
out0 (PB_DDR), a
out0 (PC_DDR), a
out0 (PD_DDR), a
ld a, %00
ld a, %00
out0 (PA_ALT1), a
out0 (PB_ALT1), a
out0 (PC_ALT1), a
@ -144,60 +144,60 @@ _ez80_init:
out0 (I2C_CTL), a ; I2C
out0 (EMAC_IEN), a ; EMAC
out0 (FLASH_IRQ), a ; Flash
ld a, %04
ld a, %04
out0 (SPI_CTL), a ; SPI
in0 a, (RTC_CTRL) ; RTC,
and a, %be
in0 a, (RTC_CTRL) ; RTC,
and a, %be
out0 (RTC_CTRL), a
; Configure external memory/io
ld a, __CS0_LBR_INIT_PARAM
ld a, __CS0_LBR_INIT_PARAM
out0 (CS0_LBR), a
ld a, __CS0_UBR_INIT_PARAM
ld a, __CS0_UBR_INIT_PARAM
out0 (CS0_UBR), a
ld a, __CS0_BMC_INIT_PARAM
ld a, __CS0_BMC_INIT_PARAM
out0 (CS0_BMC), a
ld a, __CS0_CTL_INIT_PARAM
ld a, __CS0_CTL_INIT_PARAM
out0 (CS0_CTL), a
ld a, __CS1_LBR_INIT_PARAM
ld a, __CS1_LBR_INIT_PARAM
out0 (CS1_LBR), a
ld a, __CS1_UBR_INIT_PARAM
ld a, __CS1_UBR_INIT_PARAM
out0 (CS1_UBR), a
ld a, __CS1_BMC_INIT_PARAM
ld a, __CS1_BMC_INIT_PARAM
out0 (CS1_BMC), a
ld a, __CS1_CTL_INIT_PARAM
ld a, __CS1_CTL_INIT_PARAM
out0 (CS1_CTL), a
ld a, __CS2_LBR_INIT_PARAM
ld a, __CS2_LBR_INIT_PARAM
out0 (CS2_LBR), a
ld a, __CS2_UBR_INIT_PARAM
ld a, __CS2_UBR_INIT_PARAM
out0 (CS2_UBR), a
ld a, __CS2_BMC_INIT_PARAM
ld a, __CS2_BMC_INIT_PARAM
out0 (CS2_BMC), a
ld a, __CS2_CTL_INIT_PARAM
ld a, __CS2_CTL_INIT_PARAM
out0 (CS2_CTL), a
ld a, __CS3_LBR_INIT_PARAM
ld a, __CS3_LBR_INIT_PARAM
out0 (CS3_LBR), a
ld a, __CS3_UBR_INIT_PARAM
ld a, __CS3_UBR_INIT_PARAM
out0 (CS3_UBR), a
ld a, __CS3_BMC_INIT_PARAM
ld a, __CS3_BMC_INIT_PARAM
out0 (CS3_BMC), a
ld a, __CS3_CTL_INIT_PARAM
ld a, __CS3_CTL_INIT_PARAM
out0 (CS3_CTL), a
; Enable internal memory
ld a, __FLASH_ADDR_U_INIT_PARAM
ld a, __FLASH_ADDR_U_INIT_PARAM
out0 (FLASH_ADDR_U), a
ld a, __FLASH_CTL_INIT_PARAM
ld a, __FLASH_CTL_INIT_PARAM
out0 (FLASH_CTRL), a
ld a, __RAM_ADDR_U_INIT_PARAM
ld a, __RAM_ADDR_U_INIT_PARAM
out0 (RAM_ADDR_U), a
ld a, __RAM_CTL_INIT_PARAM
ld a, __RAM_CTL_INIT_PARAM
out0 (RAM_CTL), a
ret
@ -207,51 +207,53 @@ _ez80_init:
_ez80_initsysclk:
; check if the PLL should be used
ld a, (_ez80_sysclksrc)
cp a, PLL
jr nz, _ez80_initsysclkdone
ld a, (_ez80_sysclksrc)
cp a, PLL
jr nz, _ez80_initsysclkdone
; Load PLL divider
ld a, (_ez80_oscfreqmult) ;CR 6202
ld a, (_ez80_oscfreqmult) ;CR 6202
out0 (PLL_DIV_L), a
ld a, (_ez80_oscfreqmult+1)
ld a, (_ez80_oscfreqmult+1)
out0 (PLL_DIV_H), a
; Set charge pump and lock criteria
ld a, __PLL_CTL0_INIT_PARAM
and a, %CC ; mask off reserved and clock source bits
ld a, __PLL_CTL0_INIT_PARAM
and a, %CC ; mask off reserved and clock source bits
out0 (PLL_CTL0), a
; Enable PLL
in0 a, (PLL_CTL1)
set 0, a
in0 a, (PLL_CTL1)
set 0, a
out0 (PLL_CTL1), a
; Wait for PLL to lock
_ez80_initsysclkwait:
in0 a, (PLL_CTL1)
and a, LCK_STATUS
cp a, LCK_STATUS
jr nz, _ez80_initsysclkwait
in0 a, (PLL_CTL1)
and a, LCK_STATUS
cp a, LCK_STATUS
jr nz, _ez80_initsysclkwait
; Select PLL as system clock source
ld a, __PLL_CTL0_INIT_PARAM
set 0, a
ld a, __PLL_CTL0_INIT_PARAM
set 0, a
out0 (PLL_CTL0), a
_ez80_initsysclkdone:
ret
;_ez80_oscfreq:
; dl _OSC_FREQ
; dl _OSC_FREQ
_ez80_oscfreqmult:
dw _OSC_FREQ_MULT
dw _OSC_FREQ_MULT
;_ez80_sysclkfreq:
; dl _SYS_CLK_FREQ
; dl _SYS_CLK_FREQ
_ez80_sysclksrc:
db _SYS_CLK_SRC
db _SYS_CLK_SRC
end

42
configs/makerlisp/scripts/makerlisp.linkcmd
View File

@ -34,14 +34,15 @@
/****************************************************************************/
-FORMAT=OMF695,INTEL32
-map -maxhexlen=64 -quiet -NOwarnoverlap -xref -unresolved=fatal
-sort ADDRESS=ascending -warn -NOdebug -NOigcase
-map -maxhexlen=64 -quiet -warnoverlap -xref -unresolved=fatal
-sort NAME=ascending -warn -debug -NOigcase
RANGE ROM $000000 : $03FFFF
RANGE RAM $B80000 : $BFFFFF
RANGE RAM $040000 : $13FFFF
RANGE EXTIO $000000 : $00FFFF
RANGE INTIO $000000 : $0000FF
CHANGE TEXT is CODE
CHANGE STRSECT is ROM
ORDER .RESET,.IVECTS,.STARTUP,CODE,DATA
@ -60,25 +61,26 @@ DEFINE __low_code = base of CODE
DEFINE __len_code = length of CODE
DEFINE __copy_code_to_ram = 0
DEFINE __crtl = 1
DEFINE __CS0_LBR_INIT_PARAM = $10
DEFINE __CS0_UBR_INIT_PARAM = $1f
DEFINE __CS0_CTL_INIT_PARAM = $a8
DEFINE __CS0_BMC_INIT_PARAM = $02
DEFINE __CS1_LBR_INIT_PARAM = $c0
DEFINE __CS1_UBR_INIT_PARAM = $c7
DEFINE __CS1_CTL_INIT_PARAM = $28
DEFINE __CS1_BMC_INIT_PARAM = $02
DEFINE __CS2_LBR_INIT_PARAM = $80
DEFINE __CS2_UBR_INIT_PARAM = $bf
DEFINE __CS2_CTL_INIT_PARAM = $28
DEFINE __CS2_BMC_INIT_PARAM = $81
DEFINE __CS0_LBR_INIT_PARAM = $04
DEFINE __CS0_UBR_INIT_PARAM = $0b
DEFINE __CS0_CTL_INIT_PARAM = $08
DEFINE __CS0_BMC_INIT_PARAM = $00
DEFINE __CS1_LBR_INIT_PARAM = $0c
DEFINE __CS1_UBR_INIT_PARAM = $13
DEFINE __CS1_CTL_INIT_PARAM = $08
DEFINE __CS1_BMC_INIT_PARAM = $00
DEFINE __CS2_LBR_INIT_PARAM = $20
DEFINE __CS2_UBR_INIT_PARAM = $9f
DEFINE __CS2_CTL_INIT_PARAM = $88
DEFINE __CS2_BMC_INIT_PARAM = $00
DEFINE __CS3_LBR_INIT_PARAM = $00
DEFINE __CS3_UBR_INIT_PARAM = $00
DEFINE __CS3_CTL_INIT_PARAM = $00
DEFINE __CS3_BMC_INIT_PARAM = $02
DEFINE __RAM_CTL_INIT_PARAM = $C0
DEFINE __RAM_ADDR_U_INIT_PARAM = $B7
DEFINE __FLASH_CTL_INIT_PARAM = $68
DEFINE __CS3_BMC_INIT_PARAM = $00
DEFINE __RAM_CTL_INIT_PARAM = $80
DEFINE __RAM_ADDR_U_INIT_PARAM = $AF
DEFINE __FLASH_CTL_INIT_PARAM = $88
DEFINE __FLASH_ADDR_U_INIT_PARAM = $00
define _SYS_CLK_FREQ = 50000000
@ -86,7 +88,7 @@ define _SYS_CLK_FREQ = 50000000
define _OSC_FREQ = 5000000
define _SYS_CLK_SRC = 1
define _OSC_FREQ_MULT = 10
define __PLL_CTL0_INIT_PARAM = $40
define __PLL_CTL0_INIT_PARAM = $41
define _zsl_g_clock_xdefine = 50000000