configs/makerlisp: Update external memory settings in linker script.
This commit is contained in:
Gregory Nutt
parent
cad6325589
commit
7e05bacd54
@ -43,23 +43,7 @@
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#include "arch/board/board.h"
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#include "arch/board/board.h"
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/****************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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****************************************************************************/
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uint32_t ez80_systemclock = EZ80_SYS_CLK_FREQ;
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uint32_t ez80_systemclock = EZ80_SYS_CLK_FREQ;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -77,7 +77,7 @@
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;**************************************************************************
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;**************************************************************************
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_ez80_startup:
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_ez80_startup:
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; Set up the stack pointer at the location determined the lincmd
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; Set up the stack pointer at the location determined the linkcmd
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; file
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; file
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ld sp, __stack
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ld sp, __stack
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@ -122,7 +122,7 @@ _ez80_bssdone:
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jr z, _ez80_datadone ; __len_data is zero-length ...
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jr z, _ez80_datadone ; __len_data is zero-length ...
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ld hl, __low_romdata ; [hl] = data_copy
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ld hl, __low_romdata ; [hl] = data_copy
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ld de, __low_data ; [de] = data
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ld de, __low_data ; [de] = data
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ldir ; Copy the data section
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ldir ; Copy the data section
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_ez80_datadone:
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_ez80_datadone:
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; Copy CODE (which may be in FLASH) to RAM if the
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; Copy CODE (which may be in FLASH) to RAM if the
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@ -134,8 +134,8 @@ _nmi:
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; Interrupt Vector Handling
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; Interrupt Vector Handling
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;**************************************************************************
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;**************************************************************************
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; Symbol Val VecNo Addr
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; Symbol Val VecNo Addr
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;----------------- --- ----- -----
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;----------------- --- ----- -----
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_ez80_handlers:
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_ez80_handlers:
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irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040
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irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040
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handlersize equ $-_ez80_handlers
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handlersize equ $-_ez80_handlers
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@ -147,8 +147,8 @@ _ez80_handlers:
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irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058
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irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058
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irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c
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irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c
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irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060
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irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060
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irqhandler EZ80_UNUSED ; 9 0x064
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irqhandler EZ80_UNUSED ; 9 0x064
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irqhandler EZ80_UNUSED+1 ; 10 0x068
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irqhandler EZ80_UNUSED+1 ; 10 0x068
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irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C
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irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C
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irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070
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irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070
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irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074
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irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074
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@ -186,22 +186,22 @@ _ez80_handlers:
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irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4
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irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4
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irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8
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irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8
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irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc
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irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc
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irqhandler EZ80_UNUSED+1 ; 48 0x100
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irqhandler EZ80_UNUSED+1 ; 48 0x100
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irqhandler EZ80_UNUSED+2 ; 49 0x104
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irqhandler EZ80_UNUSED+2 ; 49 0x104
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irqhandler EZ80_UNUSED+3 ; 50 0x108
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irqhandler EZ80_UNUSED+3 ; 50 0x108
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irqhandler EZ80_UNUSED+4 ; 51 0x10c
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irqhandler EZ80_UNUSED+4 ; 51 0x10c
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irqhandler EZ80_UNUSED+5 ; 52 0x110
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irqhandler EZ80_UNUSED+5 ; 52 0x110
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irqhandler EZ80_UNUSED+6 ; 53 0x114
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irqhandler EZ80_UNUSED+6 ; 53 0x114
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irqhandler EZ80_UNUSED+7 ; 54 0x118
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irqhandler EZ80_UNUSED+7 ; 54 0x118
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irqhandler EZ80_UNUSED+8 ; 55 0x11c
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irqhandler EZ80_UNUSED+8 ; 55 0x11c
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irqhandler EZ80_UNUSED+9 ; 56 0x120
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irqhandler EZ80_UNUSED+9 ; 56 0x120
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irqhandler EZ80_UNUSED+10 ; 57 0x124
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irqhandler EZ80_UNUSED+10 ; 57 0x124
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irqhandler EZ80_UNUSED+11 ; 58 0x128
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irqhandler EZ80_UNUSED+11 ; 58 0x128
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irqhandler EZ80_UNUSED+12 ; 59 0x12c
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irqhandler EZ80_UNUSED+12 ; 59 0x12c
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irqhandler EZ80_UNUSED+13 ; 60 0x130
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irqhandler EZ80_UNUSED+13 ; 60 0x130
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irqhandler EZ80_UNUSED+14 ; 61 0x134
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irqhandler EZ80_UNUSED+14 ; 61 0x134
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irqhandler EZ80_UNUSED+15 ; 62 0x138
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irqhandler EZ80_UNUSED+15 ; 62 0x138
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irqhandler EZ80_UNUSED+16 ; 63 0x13c
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irqhandler EZ80_UNUSED+16 ; 63 0x13c
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;**************************************************************************
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;**************************************************************************
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; Common Interrupt handler
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; Common Interrupt handler
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@ -216,72 +216,72 @@ _ez80_rstcommon:
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;
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;
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; IRQ number is in A
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; IRQ number is in A
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push hl ; Offset 6: HL
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push hl ; Offset 6: HL
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ld hl, #(3*3) ; HL is the value of the stack pointer before
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ld hl, #(3*3) ; HL is the value of the stack pointer before
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add hl, sp ; the interrupt occurred (3 for PC, AF, HL)
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add hl, sp ; the interrupt occurred (3 for PC, AF, HL)
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push hl ; Offset 5: Stack pointer
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push hl ; Offset 5: Stack pointer
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push iy ; Offset 4: IY
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push iy ; Offset 4: IY
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push ix ; Offset 3: IX
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push ix ; Offset 3: IX
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push de ; Offset 2: DE
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push de ; Offset 2: DE
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push bc ; Offset 1: BC
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push bc ; Offset 1: BC
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; At this point, we know that interrupts were enabled (or we wouldn't be here
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; At this point, we know that interrupts were enabled (or we wouldn't be here
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; so we can save a fake indicationn that will cause interrupts to restored when
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; so we can save a fake indication that will cause interrupts to restored when
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; this context is restored
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; this context is restored
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ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1
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ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1
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push bc ; Offset 0: I with interrupt state in parity
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push bc ; Offset 0: I with interrupt state in parity
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di ; (not necessary)
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di ; (not necessary)
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; Call the interrupt decode logic. SP points to the beggining of the reg structure
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; Call the interrupt decode logic. SP points to the beggining of the reg structure
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ld hl, #0 ; Argument #2 is the beginning of the reg structure
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ld hl, #0 ; Argument #2 is the beginning of the reg structure
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add hl, sp ;
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add hl, sp ;
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push hl ; Place argument #2 at the top of stack
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push hl ; Place argument #2 at the top of stack
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ld bc, #0 ; BC = reset number
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ld bc, #0 ; BC = reset number
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ld c, a ; Save the reset number in C
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ld c, a ; Save the reset number in C
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push bc ; Argument #1 is the Reset number
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push bc ; Argument #1 is the Reset number
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call _z80_doirq ; Decode the IRQ
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call _z80_doirq ; Decode the IRQ
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; On return, HL points to the beginning of the reg structure to restore
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; On return, HL points to the beginning of the reg structure to restore
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; Note that (1) the arguments pushed on the stack are not popped, and (2) the
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; Note that (1) the arguments pushed on the stack are not popped, and (2) the
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; original stack pointer is lost. In the normal case (no context switch),
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; original stack pointer is lost. In the normal case (no context switch),
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; HL will contain the value of the SP before the arguments were pushed.
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; HL will contain the value of the SP before the arguments were pushed.
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ld sp, hl ; Use the new stack pointer
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ld sp, hl ; Use the new stack pointer
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; Restore registers. HL points to the beginning of the reg structure to restore
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; Restore registers. HL points to the beginning of the reg structure to restore
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ex af, af' ; Select alternate AF
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ex af, af' ; Select alternate AF
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pop af ; Offset 0: AF' = I with interrupt state in parity
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pop af ; Offset 0: AF' = I with interrupt state in parity
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ex af, af' ; Restore original AF
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ex af, af' ; Restore original AF
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pop bc ; Offset 1: BC
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pop bc ; Offset 1: BC
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pop de ; Offset 2: DE
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pop de ; Offset 2: DE
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pop ix ; Offset 3: IX
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pop ix ; Offset 3: IX
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pop iy ; Offset 4: IY
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pop iy ; Offset 4: IY
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exx ; Use alternate BC/DE/HL
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exx ; Use alternate BC/DE/HL
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pop hl ; Offset 5: HL' = Stack pointer after return
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pop hl ; Offset 5: HL' = Stack pointer after return
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exx ; Restore original BC/DE/HL
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exx ; Restore original BC/DE/HL
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pop hl ; Offset 6: HL
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pop hl ; Offset 6: HL
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pop af ; Offset 7: AF
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pop af ; Offset 7: AF
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; Restore the stack pointer
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; Restore the stack pointer
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exx ; Use alternate BC/DE/HL
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exx ; Use alternate BC/DE/HL
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pop de ; Offset 8: Return address
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pop de ; Offset 8: Return address
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ld sp, hl ; Set SP = saved stack pointer value before return
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ld sp, hl ; Set SP = saved stack pointer value before return
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push de ; Set up for reti
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push de ; Set up for reti
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exx ; Restore original BC/DE/HL
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exx ; Restore original BC/DE/HL
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; Restore interrupt state
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; Restore interrupt state
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ex af, af' ; Recover interrupt state
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ex af, af' ; Recover interrupt state
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jp po, nointenable ; Odd parity, IFF2=0, means disabled
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jp po, nointenable ; Odd parity, IFF2=0, means disabled
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ex af, af' ; Restore AF (before enabling interrupts)
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ex af, af' ; Restore AF (before enabling interrupts)
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ei ; yes
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ei ; yes
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reti
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reti
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nointenable:
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nointenable:
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ex af, af' ; Restore AF
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ex af, af' ; Restore AF
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reti
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reti
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;**************************************************************************
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;**************************************************************************
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@ -291,37 +291,37 @@ nointenable:
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_ez80_initvectors:
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_ez80_initvectors:
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; Initialize the vector table
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; Initialize the vector table
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ld iy, _ez80_vectable
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ld iy, _ez80_vectable
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ld ix, 4
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ld ix, 4
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ld bc, 4
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ld bc, 4
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ld b, NVECTORS
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ld b, NVECTORS
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xor a, a ; Clear carry
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xor a, a ; Clear carry
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ld hl, handlersize
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ld hl, handlersize
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ld de, _ez80_handlers
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ld de, _ez80_handlers
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sbc hl, de ; Length of irq handler in hl
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sbc hl, de ; Length of irq handler in hl
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ld d, h
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ld d, h
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ld e, l
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ld e, l
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ld hl, _ez80_handlers ; Start of handlers in hl
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ld hl, _ez80_handlers ; Start of handlers in hl
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ld a, 0
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ld a, 0
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$1:
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$1:
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ld (iy), hl ; Store IRQ handler
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ld (iy), hl ; Store IRQ handler
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ld (iy+3), a ; Pad to 4 bytes
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ld (iy+3), a ; Pad to 4 bytes
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add hl, de ; Point to next handler
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add hl, de ; Point to next handler
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push de
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push de
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ld de, 4
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ld de, 4
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add iy, de ; Point to next entry in vector table
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add iy, de ; Point to next entry in vector table
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pop de
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pop de
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djnz $1 ; Loop until all vectors have been written
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djnz $1 ; Loop until all vectors have been written
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; Select interrupt mode 2
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; Select interrupt mode 2
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im 2 ; Interrupt mode 2
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im 2 ; Interrupt mode 2
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; Write the address of the vector table into the interrupt vector base
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; Write the address of the vector table into the interrupt vector base
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ld hl, _ez80_vectable >> 8
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ld hl, _ez80_vectable >> 8
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ld i, hl
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ld i, hl
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ret
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ret
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;**************************************************************************
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;**************************************************************************
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@ -78,35 +78,35 @@ PLL_ENABLE EQU %01
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;**************************************************************************
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;**************************************************************************
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; Exported symbols
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; Exported symbols
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xdef _ez80_init
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xdef _ez80_init
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xdef _ez80_initsysclk
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xdef _ez80_initsysclk
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; Imported symbols
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; Imported symbols
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xref __CS0_LBR_INIT_PARAM
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xref __CS0_LBR_INIT_PARAM
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xref __CS0_UBR_INIT_PARAM
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xref __CS0_UBR_INIT_PARAM
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xref __CS0_CTL_INIT_PARAM
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xref __CS0_CTL_INIT_PARAM
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xref __CS1_LBR_INIT_PARAM
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xref __CS1_LBR_INIT_PARAM
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xref __CS1_UBR_INIT_PARAM
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xref __CS1_UBR_INIT_PARAM
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xref __CS1_CTL_INIT_PARAM
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xref __CS1_CTL_INIT_PARAM
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xref __CS2_LBR_INIT_PARAM
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xref __CS2_LBR_INIT_PARAM
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xref __CS2_UBR_INIT_PARAM
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xref __CS2_UBR_INIT_PARAM
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xref __CS2_CTL_INIT_PARAM
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xref __CS2_CTL_INIT_PARAM
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xref __CS3_LBR_INIT_PARAM
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xref __CS3_LBR_INIT_PARAM
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xref __CS3_UBR_INIT_PARAM
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xref __CS3_UBR_INIT_PARAM
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xref __CS3_CTL_INIT_PARAM
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xref __CS3_CTL_INIT_PARAM
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xref __CS0_BMC_INIT_PARAM
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xref __CS0_BMC_INIT_PARAM
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xref __CS1_BMC_INIT_PARAM
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xref __CS1_BMC_INIT_PARAM
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xref __CS2_BMC_INIT_PARAM
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xref __CS2_BMC_INIT_PARAM
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xref __CS3_BMC_INIT_PARAM
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xref __CS3_BMC_INIT_PARAM
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xref __FLASH_CTL_INIT_PARAM
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xref __FLASH_CTL_INIT_PARAM
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xref __FLASH_ADDR_U_INIT_PARAM
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xref __FLASH_ADDR_U_INIT_PARAM
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xref __RAM_CTL_INIT_PARAM
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xref __RAM_CTL_INIT_PARAM
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xref __RAM_ADDR_U_INIT_PARAM
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xref __RAM_ADDR_U_INIT_PARAM
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xref _SYS_CLK_SRC
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xref _SYS_CLK_SRC
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xref _SYS_CLK_FREQ
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xref _SYS_CLK_FREQ
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xref _OSC_FREQ
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xref _OSC_FREQ
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xref _OSC_FREQ_MULT
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xref _OSC_FREQ_MULT
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xref __PLL_CTL0_INIT_PARAM
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xref __PLL_CTL0_INIT_PARAM
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;**************************************************************************
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;**************************************************************************
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; Chip-specific initialization logic
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; Chip-specific initialization logic
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@ -120,12 +120,12 @@ PLL_ENABLE EQU %01
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_ez80_init:
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_ez80_init:
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; Disable internal peripheral interrupt sources
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; Disable internal peripheral interrupt sources
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ld a, %ff
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ld a, %ff
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out0 (PA_DDR), a ; GPIO
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out0 (PA_DDR), a ; GPIO
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out0 (PB_DDR), a
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out0 (PB_DDR), a
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out0 (PC_DDR), a
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out0 (PC_DDR), a
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out0 (PD_DDR), a
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out0 (PD_DDR), a
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ld a, %00
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ld a, %00
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out0 (PA_ALT1), a
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out0 (PA_ALT1), a
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out0 (PB_ALT1), a
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out0 (PB_ALT1), a
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out0 (PC_ALT1), a
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out0 (PC_ALT1), a
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@ -144,60 +144,60 @@ _ez80_init:
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out0 (I2C_CTL), a ; I2C
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out0 (I2C_CTL), a ; I2C
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out0 (EMAC_IEN), a ; EMAC
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out0 (EMAC_IEN), a ; EMAC
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out0 (FLASH_IRQ), a ; Flash
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out0 (FLASH_IRQ), a ; Flash
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ld a, %04
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ld a, %04
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out0 (SPI_CTL), a ; SPI
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out0 (SPI_CTL), a ; SPI
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in0 a, (RTC_CTRL) ; RTC,
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in0 a, (RTC_CTRL) ; RTC,
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and a, %be
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and a, %be
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out0 (RTC_CTRL), a
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out0 (RTC_CTRL), a
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; Configure external memory/io
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; Configure external memory/io
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ld a, __CS0_LBR_INIT_PARAM
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ld a, __CS0_LBR_INIT_PARAM
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out0 (CS0_LBR), a
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out0 (CS0_LBR), a
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ld a, __CS0_UBR_INIT_PARAM
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ld a, __CS0_UBR_INIT_PARAM
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out0 (CS0_UBR), a
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out0 (CS0_UBR), a
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ld a, __CS0_BMC_INIT_PARAM
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ld a, __CS0_BMC_INIT_PARAM
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out0 (CS0_BMC), a
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out0 (CS0_BMC), a
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ld a, __CS0_CTL_INIT_PARAM
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ld a, __CS0_CTL_INIT_PARAM
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out0 (CS0_CTL), a
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out0 (CS0_CTL), a
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ld a, __CS1_LBR_INIT_PARAM
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ld a, __CS1_LBR_INIT_PARAM
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out0 (CS1_LBR), a
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out0 (CS1_LBR), a
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||||||
ld a, __CS1_UBR_INIT_PARAM
|
ld a, __CS1_UBR_INIT_PARAM
|
||||||
out0 (CS1_UBR), a
|
out0 (CS1_UBR), a
|
||||||
ld a, __CS1_BMC_INIT_PARAM
|
ld a, __CS1_BMC_INIT_PARAM
|
||||||
out0 (CS1_BMC), a
|
out0 (CS1_BMC), a
|
||||||
ld a, __CS1_CTL_INIT_PARAM
|
ld a, __CS1_CTL_INIT_PARAM
|
||||||
out0 (CS1_CTL), a
|
out0 (CS1_CTL), a
|
||||||
|
|
||||||
ld a, __CS2_LBR_INIT_PARAM
|
ld a, __CS2_LBR_INIT_PARAM
|
||||||
out0 (CS2_LBR), a
|
out0 (CS2_LBR), a
|
||||||
ld a, __CS2_UBR_INIT_PARAM
|
ld a, __CS2_UBR_INIT_PARAM
|
||||||
out0 (CS2_UBR), a
|
out0 (CS2_UBR), a
|
||||||
ld a, __CS2_BMC_INIT_PARAM
|
ld a, __CS2_BMC_INIT_PARAM
|
||||||
out0 (CS2_BMC), a
|
out0 (CS2_BMC), a
|
||||||
ld a, __CS2_CTL_INIT_PARAM
|
ld a, __CS2_CTL_INIT_PARAM
|
||||||
out0 (CS2_CTL), a
|
out0 (CS2_CTL), a
|
||||||
|
|
||||||
ld a, __CS3_LBR_INIT_PARAM
|
ld a, __CS3_LBR_INIT_PARAM
|
||||||
out0 (CS3_LBR), a
|
out0 (CS3_LBR), a
|
||||||
ld a, __CS3_UBR_INIT_PARAM
|
ld a, __CS3_UBR_INIT_PARAM
|
||||||
out0 (CS3_UBR), a
|
out0 (CS3_UBR), a
|
||||||
ld a, __CS3_BMC_INIT_PARAM
|
ld a, __CS3_BMC_INIT_PARAM
|
||||||
out0 (CS3_BMC), a
|
out0 (CS3_BMC), a
|
||||||
ld a, __CS3_CTL_INIT_PARAM
|
ld a, __CS3_CTL_INIT_PARAM
|
||||||
out0 (CS3_CTL), a
|
out0 (CS3_CTL), a
|
||||||
|
|
||||||
; Enable internal memory
|
; Enable internal memory
|
||||||
|
|
||||||
ld a, __FLASH_ADDR_U_INIT_PARAM
|
ld a, __FLASH_ADDR_U_INIT_PARAM
|
||||||
out0 (FLASH_ADDR_U), a
|
out0 (FLASH_ADDR_U), a
|
||||||
ld a, __FLASH_CTL_INIT_PARAM
|
ld a, __FLASH_CTL_INIT_PARAM
|
||||||
out0 (FLASH_CTRL), a
|
out0 (FLASH_CTRL), a
|
||||||
|
|
||||||
ld a, __RAM_ADDR_U_INIT_PARAM
|
ld a, __RAM_ADDR_U_INIT_PARAM
|
||||||
out0 (RAM_ADDR_U), a
|
out0 (RAM_ADDR_U), a
|
||||||
ld a, __RAM_CTL_INIT_PARAM
|
ld a, __RAM_CTL_INIT_PARAM
|
||||||
out0 (RAM_CTL), a
|
out0 (RAM_CTL), a
|
||||||
ret
|
ret
|
||||||
|
|
||||||
@ -207,51 +207,53 @@ _ez80_init:
|
|||||||
|
|
||||||
_ez80_initsysclk:
|
_ez80_initsysclk:
|
||||||
; check if the PLL should be used
|
; check if the PLL should be used
|
||||||
ld a, (_ez80_sysclksrc)
|
|
||||||
cp a, PLL
|
ld a, (_ez80_sysclksrc)
|
||||||
jr nz, _ez80_initsysclkdone
|
cp a, PLL
|
||||||
|
jr nz, _ez80_initsysclkdone
|
||||||
|
|
||||||
; Load PLL divider
|
; Load PLL divider
|
||||||
|
|
||||||
ld a, (_ez80_oscfreqmult) ;CR 6202
|
ld a, (_ez80_oscfreqmult) ;CR 6202
|
||||||
out0 (PLL_DIV_L), a
|
out0 (PLL_DIV_L), a
|
||||||
ld a, (_ez80_oscfreqmult+1)
|
ld a, (_ez80_oscfreqmult+1)
|
||||||
out0 (PLL_DIV_H), a
|
out0 (PLL_DIV_H), a
|
||||||
|
|
||||||
; Set charge pump and lock criteria
|
; Set charge pump and lock criteria
|
||||||
|
|
||||||
ld a, __PLL_CTL0_INIT_PARAM
|
ld a, __PLL_CTL0_INIT_PARAM
|
||||||
and a, %CC ; mask off reserved and clock source bits
|
and a, %CC ; mask off reserved and clock source bits
|
||||||
out0 (PLL_CTL0), a
|
out0 (PLL_CTL0), a
|
||||||
|
|
||||||
; Enable PLL
|
; Enable PLL
|
||||||
|
|
||||||
in0 a, (PLL_CTL1)
|
in0 a, (PLL_CTL1)
|
||||||
set 0, a
|
set 0, a
|
||||||
out0 (PLL_CTL1), a
|
out0 (PLL_CTL1), a
|
||||||
|
|
||||||
; Wait for PLL to lock
|
; Wait for PLL to lock
|
||||||
|
|
||||||
_ez80_initsysclkwait:
|
_ez80_initsysclkwait:
|
||||||
in0 a, (PLL_CTL1)
|
in0 a, (PLL_CTL1)
|
||||||
and a, LCK_STATUS
|
and a, LCK_STATUS
|
||||||
cp a, LCK_STATUS
|
cp a, LCK_STATUS
|
||||||
jr nz, _ez80_initsysclkwait
|
jr nz, _ez80_initsysclkwait
|
||||||
|
|
||||||
; Select PLL as system clock source
|
; Select PLL as system clock source
|
||||||
|
|
||||||
ld a, __PLL_CTL0_INIT_PARAM
|
ld a, __PLL_CTL0_INIT_PARAM
|
||||||
set 0, a
|
set 0, a
|
||||||
out0 (PLL_CTL0), a
|
out0 (PLL_CTL0), a
|
||||||
|
|
||||||
_ez80_initsysclkdone:
|
_ez80_initsysclkdone:
|
||||||
ret
|
ret
|
||||||
|
|
||||||
;_ez80_oscfreq:
|
;_ez80_oscfreq:
|
||||||
; dl _OSC_FREQ
|
; dl _OSC_FREQ
|
||||||
_ez80_oscfreqmult:
|
_ez80_oscfreqmult:
|
||||||
dw _OSC_FREQ_MULT
|
dw _OSC_FREQ_MULT
|
||||||
;_ez80_sysclkfreq:
|
;_ez80_sysclkfreq:
|
||||||
; dl _SYS_CLK_FREQ
|
; dl _SYS_CLK_FREQ
|
||||||
_ez80_sysclksrc:
|
_ez80_sysclksrc:
|
||||||
db _SYS_CLK_SRC
|
db _SYS_CLK_SRC
|
||||||
end
|
end
|
||||||
|
|||||||
@ -34,14 +34,15 @@
|
|||||||
/****************************************************************************/
|
/****************************************************************************/
|
||||||
|
|
||||||
-FORMAT=OMF695,INTEL32
|
-FORMAT=OMF695,INTEL32
|
||||||
-map -maxhexlen=64 -quiet -NOwarnoverlap -xref -unresolved=fatal
|
-map -maxhexlen=64 -quiet -warnoverlap -xref -unresolved=fatal
|
||||||
-sort ADDRESS=ascending -warn -NOdebug -NOigcase
|
-sort NAME=ascending -warn -debug -NOigcase
|
||||||
|
|
||||||
RANGE ROM $000000 : $03FFFF
|
RANGE ROM $000000 : $03FFFF
|
||||||
RANGE RAM $B80000 : $BFFFFF
|
RANGE RAM $040000 : $13FFFF
|
||||||
RANGE EXTIO $000000 : $00FFFF
|
RANGE EXTIO $000000 : $00FFFF
|
||||||
RANGE INTIO $000000 : $0000FF
|
RANGE INTIO $000000 : $0000FF
|
||||||
|
|
||||||
|
CHANGE TEXT is CODE
|
||||||
CHANGE STRSECT is ROM
|
CHANGE STRSECT is ROM
|
||||||
|
|
||||||
ORDER .RESET,.IVECTS,.STARTUP,CODE,DATA
|
ORDER .RESET,.IVECTS,.STARTUP,CODE,DATA
|
||||||
@ -60,25 +61,26 @@ DEFINE __low_code = base of CODE
|
|||||||
DEFINE __len_code = length of CODE
|
DEFINE __len_code = length of CODE
|
||||||
DEFINE __copy_code_to_ram = 0
|
DEFINE __copy_code_to_ram = 0
|
||||||
DEFINE __crtl = 1
|
DEFINE __crtl = 1
|
||||||
DEFINE __CS0_LBR_INIT_PARAM = $10
|
|
||||||
DEFINE __CS0_UBR_INIT_PARAM = $1f
|
DEFINE __CS0_LBR_INIT_PARAM = $04
|
||||||
DEFINE __CS0_CTL_INIT_PARAM = $a8
|
DEFINE __CS0_UBR_INIT_PARAM = $0b
|
||||||
DEFINE __CS0_BMC_INIT_PARAM = $02
|
DEFINE __CS0_CTL_INIT_PARAM = $08
|
||||||
DEFINE __CS1_LBR_INIT_PARAM = $c0
|
DEFINE __CS0_BMC_INIT_PARAM = $00
|
||||||
DEFINE __CS1_UBR_INIT_PARAM = $c7
|
DEFINE __CS1_LBR_INIT_PARAM = $0c
|
||||||
DEFINE __CS1_CTL_INIT_PARAM = $28
|
DEFINE __CS1_UBR_INIT_PARAM = $13
|
||||||
DEFINE __CS1_BMC_INIT_PARAM = $02
|
DEFINE __CS1_CTL_INIT_PARAM = $08
|
||||||
DEFINE __CS2_LBR_INIT_PARAM = $80
|
DEFINE __CS1_BMC_INIT_PARAM = $00
|
||||||
DEFINE __CS2_UBR_INIT_PARAM = $bf
|
DEFINE __CS2_LBR_INIT_PARAM = $20
|
||||||
DEFINE __CS2_CTL_INIT_PARAM = $28
|
DEFINE __CS2_UBR_INIT_PARAM = $9f
|
||||||
DEFINE __CS2_BMC_INIT_PARAM = $81
|
DEFINE __CS2_CTL_INIT_PARAM = $88
|
||||||
|
DEFINE __CS2_BMC_INIT_PARAM = $00
|
||||||
DEFINE __CS3_LBR_INIT_PARAM = $00
|
DEFINE __CS3_LBR_INIT_PARAM = $00
|
||||||
DEFINE __CS3_UBR_INIT_PARAM = $00
|
DEFINE __CS3_UBR_INIT_PARAM = $00
|
||||||
DEFINE __CS3_CTL_INIT_PARAM = $00
|
DEFINE __CS3_CTL_INIT_PARAM = $00
|
||||||
DEFINE __CS3_BMC_INIT_PARAM = $02
|
DEFINE __CS3_BMC_INIT_PARAM = $00
|
||||||
DEFINE __RAM_CTL_INIT_PARAM = $C0
|
DEFINE __RAM_CTL_INIT_PARAM = $80
|
||||||
DEFINE __RAM_ADDR_U_INIT_PARAM = $B7
|
DEFINE __RAM_ADDR_U_INIT_PARAM = $AF
|
||||||
DEFINE __FLASH_CTL_INIT_PARAM = $68
|
DEFINE __FLASH_CTL_INIT_PARAM = $88
|
||||||
DEFINE __FLASH_ADDR_U_INIT_PARAM = $00
|
DEFINE __FLASH_ADDR_U_INIT_PARAM = $00
|
||||||
|
|
||||||
define _SYS_CLK_FREQ = 50000000
|
define _SYS_CLK_FREQ = 50000000
|
||||||
@ -86,7 +88,7 @@ define _SYS_CLK_FREQ = 50000000
|
|||||||
define _OSC_FREQ = 5000000
|
define _OSC_FREQ = 5000000
|
||||||
define _SYS_CLK_SRC = 1
|
define _SYS_CLK_SRC = 1
|
||||||
define _OSC_FREQ_MULT = 10
|
define _OSC_FREQ_MULT = 10
|
||||||
define __PLL_CTL0_INIT_PARAM = $40
|
define __PLL_CTL0_INIT_PARAM = $41
|
||||||
|
|
||||||
define _zsl_g_clock_xdefine = 50000000
|
define _zsl_g_clock_xdefine = 50000000
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user