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arch/arm: Add CONTROL register bit field definition

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and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2021-08-06 14:25:25 +08:00 committed by Alan Carvalho de Assis
parent b815a2c3a8
commit 7e0db977cc
25 changed files with 67 additions and 44 deletions
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6
arch/arm/include/armv6-m/irq.h
View File

@ -131,6 +131,12 @@
#define REG_PIC REG_R10
/* CONTROL register */
#define CONTROL_FPCA (1 << 2) /* Bit 2: Floating-point context active */
#define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */
#define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */
/****************************************************************************
* Public Types
****************************************************************************/

6
arch/arm/include/armv7-m/irq.h
View File

@ -87,6 +87,12 @@
#define REG_PIC REG_R10
/* CONTROL register */
#define CONTROL_FPCA (1 << 2) /* Bit 2: Floating-point context active */
#define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */
#define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */
/****************************************************************************
* Public Types
****************************************************************************/

11
arch/arm/include/armv8-m/irq.h
View File

@ -87,6 +87,17 @@
#define REG_PIC REG_R10
/* CONTROL register */
#define CONTROL_UPAC_EN (1 << 7) /* Bit 7: Unprivileged pointer authentication enable */
#define CONTROL_PAC_EN (1 << 6) /* Bit 6: Privileged pointer authentication enable */
#define CONTROL_UBTI_EN (1 << 5) /* Bit 5: Unprivileged branch target identification enable */
#define CONTROL_BTI_EN (1 << 4) /* Bit 4: Privileged branch target identification enable */
#define CONTROL_SFPA (1 << 3) /* Bit 3: Secure Floating-point active */
#define CONTROL_FPCA (1 << 2) /* Bit 2: Floating-point context active */
#define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */
#define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */
/****************************************************************************
* Public Types
****************************************************************************/

4
arch/arm/src/cxd56xx/cxd56_start.c
View File

@ -147,7 +147,7 @@ void fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -177,7 +177,7 @@ void fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/efm32/efm32_start.c
View File

@ -139,7 +139,7 @@ static inline void efm32_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -169,7 +169,7 @@ static inline void efm32_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/eoss3/eoss3_start.c
View File

@ -137,7 +137,7 @@ static inline void eoss3_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -167,7 +167,7 @@ static inline void eoss3_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/imxrt/imxrt_start.c
View File

@ -121,7 +121,7 @@ static inline void imxrt_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -151,7 +151,7 @@ static inline void imxrt_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/kinetis/kinetis_start.c
View File

@ -133,7 +133,7 @@ static inline void kinetis_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -163,7 +163,7 @@ static inline void kinetis_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
View File

@ -122,7 +122,7 @@ static inline void lpc17_40_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -152,7 +152,7 @@ static inline void lpc17_40_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -190,7 +190,7 @@ static inline void lpc43_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -220,7 +220,7 @@ static inline void lpc43_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/lpc54xx/lpc54_start.c
View File

@ -120,7 +120,7 @@ static inline void lpc54_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -148,7 +148,7 @@ static inline void lpc54_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/max326xx/common/max326_start.c
View File

@ -120,7 +120,7 @@ static inline void max326_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -148,7 +148,7 @@ static inline void max326_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/nrf52/nrf52_start.c
View File

@ -107,7 +107,7 @@ static inline void nrf52_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -135,7 +135,7 @@ static inline void nrf52_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/s32k1xx/s32k1xx_start.c
View File

@ -160,7 +160,7 @@ static inline void s32k1xx_fpu_config(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -188,7 +188,7 @@ static inline void s32k1xx_fpu_config(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/sam34/sam_start.c
View File

@ -135,7 +135,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -165,7 +165,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/samd5e5/sam_start.c
View File

@ -137,7 +137,7 @@ static inline void sam_fpu_configure(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -167,7 +167,7 @@ static inline void sam_fpu_configure(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/samv7/sam_start.c
View File

@ -132,7 +132,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -162,7 +162,7 @@ static inline void sam_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/stm32/stm32_start.c
View File

@ -138,7 +138,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -168,7 +168,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/stm32f7/stm32_start.c
View File

@ -132,7 +132,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -162,7 +162,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/stm32h7/stm32_start.c
View File

@ -147,7 +147,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -177,7 +177,7 @@ static inline void stm32_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/stm32l4/stm32l4_start.c
View File

@ -147,7 +147,7 @@ static inline void stm32l4_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -177,7 +177,7 @@ static inline void stm32l4_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/stm32l5/stm32l5_start.c
View File

@ -150,7 +150,7 @@ static inline void stm32l5_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -180,7 +180,7 @@ static inline void stm32l5_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View File

@ -134,7 +134,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -164,7 +164,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/tiva/common/lmxx_tm4c_start.c
View File

@ -125,7 +125,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -155,7 +155,7 @@ static inline void tiva_fpuconfig(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend

4
arch/arm/src/xmc4/xmc4_start.c
View File

@ -156,7 +156,7 @@ static inline void xmc4_fpu_config(void)
*/
regval = getcontrol();
regval |= (1 << 2);
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
@ -186,7 +186,7 @@ static inline void xmc4_fpu_config(void)
*/
regval = getcontrol();
regval &= ~(1 << 2);
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend