SAMA5 EMAC and GMAC: More additions to register definition files
This commit is contained in:
Gregory Nutt
parent
f2f40f35bd
commit
7e33cee02f
@ -48,53 +48,53 @@
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************************************************************************************/
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/* EMAC Register Offsets ************************************************************/
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#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
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#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
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#define SAM_EMAC_NSR_OFFSET 0x0008 /* Network Status Register */
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#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
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#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
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#define SAM_EMAC_NSR_OFFSET 0x0008 /* Network Status Register */
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/* 0x000c-0x0010 Reserved */
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#define SAM_EMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
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#define SAM_EMAC_RBQP_OFFSET 0x0018 /* Receive Buffer Queue Pointer Register */
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#define SAM_EMAC_TBQP_OFFSET 0x001c /* Transmit Buffer Queue Pointer Register */
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#define SAM_EMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
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#define SAM_EMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
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#define SAM_EMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
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#define SAM_EMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
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#define SAM_EMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
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#define SAM_EMAC_MAN_OFFSET 0x0034 /* Phy Maintenance Register */
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#define SAM_EMAC_PTR_OFFSET 0x0038 /* Pause Time Register */
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#define SAM_EMAC_PFR_OFFSET 0x003c /* Pause Frames Received Register */
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#define SAM_EMAC_FTO_OFFSET 0x0040 /* Frames Transmitted Ok Register */
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#define SAM_EMAC_SCF_OFFSET 0x0044 /* Single Collision Frames Register */
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#define SAM_EMAC_MCF_OFFSET 0x0048 /* Multiple Collision Frames Register */
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#define SAM_EMAC_FRO_OFFSET 0x004c /* Frames Received Ok Register */
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#define SAM_EMAC_FCSE_OFFSET 0x0050 /* Frame Check Sequence Errors Register */
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#define SAM_EMAC_ALE_OFFSET 0x0054 /* Alignment Errors Register */
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#define SAM_EMAC_DTF_OFFSET 0x0058 /* Deferred Transmission Frames Register */
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#define SAM_EMAC_LCOL_OFFSET 0x005c /* Late Collisions Register */
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#define SAM_EMAC_ECOL_OFFSET 0x0060 /* Excessive Collisions Register */
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#define SAM_EMAC_TUND_OFFSET 0x0064 /* Transmit Underrun Errors Register */
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#define SAM_EMAC_CSE_OFFSET 0x0068 /* Carrier Sense Errors Register */
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#define SAM_EMAC_RRE_OFFSET 0x006c /* Receive Resource Errors Register */
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#define SAM_EMAC_ROV_OFFSET 0x0070 /* Receive Overrun Errors Register */
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#define SAM_EMAC_RSE_OFFSET 0x0074 /* Receive Symbol Errors Register */
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#define SAM_EMAC_ELE_OFFSET 0x0078 /* Excessive Length Errors Register */
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#define SAM_EMAC_RJA_OFFSET 0x007c /* Receive Jabbers Register */
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#define SAM_EMAC_USF_OFFSET 0x0080 /* Undersize Frames Register */
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#define SAM_EMAC_STE_OFFSET 0x0084 /* SQE Test Errors Register */
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#define SAM_EMAC_RLE_OFFSET 0x0088 /* Received Length Field Mismatch Register */
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#define SAM_EMAC_HRB_OFFSET 0x0090 /* Hash Register Bottom [31:0] Register */
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#define SAM_EMAC_HRT_OFFSET 0x0094 /* Hash Register Top [63:32] Register */
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#define SAM_EMAC_SA1B_OFFSET 0x0098 /* Specific Address 1 Bottom Register */
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#define SAM_EMAC_SA1T_OFFSET 0x009c /* Specific Address 1 Top Register */
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#define SAM_EMAC_SA2B_OFFSET 0x00a0 /* Specific Address 2 Bottom Register */
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#define SAM_EMAC_SA2T_OFFSET 0x00a4 /* Specific Address 2 Top Register */
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#define SAM_EMAC_SA3B_OFFSET 0x00a8 /* Specific Address 3 Bottom Register */
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#define SAM_EMAC_SA3T_OFFSET 0x00ac /* Specific Address 3 Top Register */
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#define SAM_EMAC_SA4B_OFFSET 0x00b0 /* Specific Address 4 Bottom Register */
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#define SAM_EMAC_SA4T_OFFSET 0x00b4 /* Specific Address 4 Top Register */
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#define SAM_EMAC_TID_OFFSET 0x00b8 /* Type ID Checking Register */
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#define SAM_EMAC_USRIO_OFFSET 0x00c0 /* User Input/Output Register */
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#define SAM_EMAC_WOL_OFFSET 0x00c4 /* Wake on LAN Register */
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#define SAM_EMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
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#define SAM_EMAC_RBQP_OFFSET 0x0018 /* Receive Buffer Queue Pointer Register */
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#define SAM_EMAC_TBQP_OFFSET 0x001c /* Transmit Buffer Queue Pointer Register */
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#define SAM_EMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
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#define SAM_EMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
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#define SAM_EMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
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#define SAM_EMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
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#define SAM_EMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
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#define SAM_EMAC_MAN_OFFSET 0x0034 /* Phy Maintenance Register */
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#define SAM_EMAC_PTR_OFFSET 0x0038 /* Pause Time Register */
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#define SAM_EMAC_PFR_OFFSET 0x003c /* Pause Frames Received Register */
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#define SAM_EMAC_FTO_OFFSET 0x0040 /* Frames Transmitted Ok Register */
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#define SAM_EMAC_SCF_OFFSET 0x0044 /* Single Collision Frames Register */
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#define SAM_EMAC_MCF_OFFSET 0x0048 /* Multiple Collision Frames Register */
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#define SAM_EMAC_FRO_OFFSET 0x004c /* Frames Received Ok Register */
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#define SAM_EMAC_FCSE_OFFSET 0x0050 /* Frame Check Sequence Errors Register */
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#define SAM_EMAC_ALE_OFFSET 0x0054 /* Alignment Errors Register */
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#define SAM_EMAC_DTF_OFFSET 0x0058 /* Deferred Transmission Frames Register */
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#define SAM_EMAC_LCOL_OFFSET 0x005c /* Late Collisions Register */
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#define SAM_EMAC_ECOL_OFFSET 0x0060 /* Excessive Collisions Register */
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#define SAM_EMAC_TUND_OFFSET 0x0064 /* Transmit Underrun Errors Register */
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#define SAM_EMAC_CSE_OFFSET 0x0068 /* Carrier Sense Errors Register */
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#define SAM_EMAC_RRE_OFFSET 0x006c /* Receive Resource Errors Register */
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#define SAM_EMAC_ROV_OFFSET 0x0070 /* Receive Overrun Errors Register */
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#define SAM_EMAC_RSE_OFFSET 0x0074 /* Receive Symbol Errors Register */
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#define SAM_EMAC_ELE_OFFSET 0x0078 /* Excessive Length Errors Register */
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#define SAM_EMAC_RJA_OFFSET 0x007c /* Receive Jabbers Register */
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#define SAM_EMAC_USF_OFFSET 0x0080 /* Undersize Frames Register */
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#define SAM_EMAC_STE_OFFSET 0x0084 /* SQE Test Errors Register */
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#define SAM_EMAC_RLE_OFFSET 0x0088 /* Received Length Field Mismatch Register */
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#define SAM_EMAC_HRB_OFFSET 0x0090 /* Hash Register Bottom [31:0] Register */
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#define SAM_EMAC_HRT_OFFSET 0x0094 /* Hash Register Top [63:32] Register */
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#define SAM_EMAC_SA1B_OFFSET 0x0098 /* Specific Address 1 Bottom Register */
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#define SAM_EMAC_SA1T_OFFSET 0x009c /* Specific Address 1 Top Register */
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#define SAM_EMAC_SA2B_OFFSET 0x00a0 /* Specific Address 2 Bottom Register */
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#define SAM_EMAC_SA2T_OFFSET 0x00a4 /* Specific Address 2 Top Register */
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#define SAM_EMAC_SA3B_OFFSET 0x00a8 /* Specific Address 3 Bottom Register */
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#define SAM_EMAC_SA3T_OFFSET 0x00ac /* Specific Address 3 Top Register */
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#define SAM_EMAC_SA4B_OFFSET 0x00b0 /* Specific Address 4 Bottom Register */
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#define SAM_EMAC_SA4T_OFFSET 0x00b4 /* Specific Address 4 Top Register */
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#define SAM_EMAC_TID_OFFSET 0x00b8 /* Type ID Checking Register */
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#define SAM_EMAC_USRIO_OFFSET 0x00c0 /* User Input/Output Register */
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#define SAM_EMAC_WOL_OFFSET 0x00c4 /* Wake on LAN Register */
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/* 0x00c8-0x00fc Reserved */
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/* EMAC Register Addresses **********************************************************/
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@ -148,97 +148,239 @@
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/* EMAC Register Bit Definitions ****************************************************/
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/* Network Control Register */
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#define EMAC_NCR_
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/* Network Configuration Register */
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#define EMAC_NCFGR_
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/* Network Status Register */
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#define EMAC_NSR_
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/* Transmit Status Register */
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#define EMAC_TSR_
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/* Receive Buffer Queue Pointer Register */
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#define EMAC_RBQP_
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/* Transmit Buffer Queue Pointer Register */
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#define EMAC_TBQP_
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/* Receive Status Register */
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#define EMAC_RSR_
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/* Interrupt Status Register */
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#define EMAC_ISR_
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/* Interrupt Enable Register */
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#define EMAC_IER_
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/* Interrupt Disable Register */
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#define EMAC_IDR_
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/* Interrupt Mask Register */
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#define EMAC_IMR_
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/* Phy Maintenance Register */
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#define EMAC_MAN_
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/* Pause Time Register */
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#define EMAC_PTR_
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/* Pause Frames Received Register */
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#define EMAC_PFR_
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/* Frames Transmitted Ok Register */
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#define EMAC_FTO_
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/* Single Collision Frames Register */
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#define EMAC_SCF_
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/* Multiple Collision Frames Register */
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#define EMAC_MCF_
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/* Frames Received Ok Register */
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#define EMAC_FRO_
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/* Frame Check Sequence Errors Register */
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#define EMAC_FCSE_
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/* Alignment Errors Register */
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#define EMAC_ALE_
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/* Deferred Transmission Frames Register */
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#define EMAC_DTF_
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/* Late Collisions Register */
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#define EMAC_LCOL_
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/* Excessive Collisions Register */
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#define EMAC_ECOL_
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/* Transmit Underrun Errors Register */
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#define EMAC_TUND_
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/* Carrier Sense Errors Register */
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#define EMAC_CSE_
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/* Receive Resource Errors Register */
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#define EMAC_RRE_
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/* Receive Overrun Errors Register */
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#define EMAC_ROV_
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/* Receive Symbol Errors Register */
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#define EMAC_RSE_
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/* Excessive Length Errors Register */
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#define EMAC_ELE_
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/* Receive Jabbers Register */
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#define EMAC_RJA_
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/* Undersize Frames Register */
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#define EMAC_USF_
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/* SQE Test Errors Register */
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#define EMAC_STE_
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/* Received Length Field Mismatch Register */
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#define EMAC_RLE_
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/* Hash Register Bottom [31:0] Register */
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#define EMAC_HRB_
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/* Hash Register Top [63:32] Register */
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#define EMAC_HRT_
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/* Specific Address 1 Bottom Register */
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#define EMAC_SA1B_
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/* Specific Address 1 Top Register */
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#define EMAC_SA1T_
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/* Specific Address 2 Bottom Register */
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#define EMAC_SA2B_
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/* Specific Address 2 Top Register */
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#define EMAC_SA2T_
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/* Specific Address 3 Bottom Register */
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#define EMAC_SA3B_
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/* Specific Address 3 Top Register */
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#define EMAC_SA3T_
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/* Specific Address 4 Bottom Register */
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#define EMAC_SA4B_
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/* Specific Address 4 Top Register */
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#define EMAC_SA4T_
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/* Type ID Checking Register */
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#define EMAC_TID_
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/* User Input/Output Register */
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#define EMAC_USRIO_
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/* Wake on LAN Register */
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#define EMAC_WOL_
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/* Network Control Register */
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#define EMAC_NCR_LB (1 << 0) /* Bit 0: LoopBack */
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#define EMAC_NCR_LLB (1 << 1) /* Bit 1: Loopback local */
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#define EMAC_NCR_RE (1 << 2) /* Bit 2: Receive enable */
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#define EMAC_NCR_TE (1 << 3) /* Bit 3: Transmit enable */
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#define EMAC_NCR_MPE (1 << 4) /* Bit 4: Management port enable */
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#define EMAC_NCR_CLRSTAT (1 << 5) /* Bit 5: Clear statistics registers */
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#define EMAC_NCR_INCSTAT (1 << 6) /* Bit 6: Increment statistics registers */
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#define EMAC_NCR_WESTAT (1 << 7) /* Bit 7: Write enable for statistics registers */
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#define EMAC_NCR_BP (1 << 8) /* Bit 8: Back pressure */
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#define EMAC_NCR_TSTART (1 << 9) /* Bit 9: Start transmission */
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#define EMAC_NCR_THALT (1 << 10) /* Bit 10: Transmit halt */
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/* Network Configuration Register */
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#define EMAC_NCFGR_SPD (1 << 0) /* Bit 0: Speed */
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#define EMAC_NCFGR_FD (1 << 1) /* Bit 1: Full Duplex */
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#define EMAC_NCFGR_JFRAME (1 << 3) /* Bit 3: Jumbo Frames */
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#define EMAC_NCFGR_CAF (1 << 4) /* Bit 4: Copy All Frames */
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#define EMAC_NCFGR_NBC (1 << 5) /* Bit 5: No Broadcast */
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#define EMAC_NCFGR_MTI (1 << 6) /* Bit 6: Multicast Hash Enable */
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#define EMAC_NCFGR_UNI (1 << 7) /* Bit 7: Unicast Hash Enable */
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#define EMAC_NCFGR_BIG (1 << 8) /* Bit 8: Receive 1536 bytes frames */
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#define EMAC_NCFGR_CLK_SHIFT (10) /* Bits 10-11: MDC clock divider */
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#define EMAC_NCFGR_CLK_MASK (3 << EMAC_NCFGR_CLK_SHIFT)
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# define EMAC_NCFGR_CLK_DIV8 (0 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 8 (MCK up to 20 MHz) */
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# define EMAC_NCFGR_CLK_DIV16 (1 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 16 (MCK up to 40 MHz) */
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# define EMAC_NCFGR_CLK_DIV32 (2 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */
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# define EMAC_NCFGR_CLK_DIV64 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
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#define EMAC_NCFGR_RTY (1 << 12) /* Bit 12: Retry test */
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#define EMAC_NCFGR_PAE (1 << 13) /* Bit 13: Pause Enable */
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#define EMAC_NCFGR_RBOF_SHIFT (14) /* Bits 14-15: Receive Buffer Offset */
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#define EMAC_NCFGR_RBOF_MASK (3 << EMAC_NCFGR_RBOF_SHIFT)
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# define EMAC_NCFGR_RBOF_NONE (0 << EMAC_NCFGR_RBOF_SHIFT) /* No offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_1 (1 << EMAC_NCFGR_RBOF_SHIFT) /* One-byte offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_2 (2 << EMAC_NCFGR_RBOF_SHIFT) /* Two-byte offset from RX buffer start */
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# define EMAC_NCFGR_RBOF_3 (3 << EMAC_NCFGR_RBOF_SHIFT) /* Three-byte offset fromRX buffer start */
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#define EMAC_NCFGR_RLCE (1 << 16) /* Bit 16: Receive Length field Checking Enable */
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#define EMAC_NCFGR_DRFCS (1 << 17) /* Bit 17: Discard Receive FCS */
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#define EMAC_NCFGR_EFRHD (1 << 18) /* Bit 18: Enable RX frames in HD mode while transmitting */
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#define EMAC_NCFGR_IRXFCS (1 << 19) /* Bit 19: Ignore RX FCS */
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/* Network Status Register */
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#define EMAC_NSR_MDIO (1 << 0) /* Bit 0: Status of the mdio_in pin */
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#define EMAC_NSR_IDLE (1 << 1) /* Bit 1: PHY management logic is idle */
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/* Transmit Status Register */
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#define EMAC_TSR_UBR (1 << 0) /* Bit 0: Used Bit Read */
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#define EMAC_TSR_COL (1 << 1) /* Bit 1: Collision Occurred */
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#define EMAC_TSR_RLES (1 << 2) /* Bit 2: Retry Limit exceeded */
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#define EMAC_TSR_TGO (1 << 3) /* Bit 3: Transmit Go */
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#define EMAC_TSR_BEX (1 << 4) /* Bit 4: Buffers exhausted mid frame */
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#define EMAC_TSR_COMP (1 << 5) /* Bit 5: Transmit Complete */
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#define EMAC_TSR_UND (1 << 6) /* Bit 6: Transmit Underrun */
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/* Receive Buffer Queue Pointer Register */
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#define EMAC_RBQP_MASK (0xfffffffc) /* Bits 2-31: Receive buffer queue pointer address */
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/* Transmit Buffer Queue Pointer Register */
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#define EMAC_TBQP_MASK (0xfffffffc) /* Bits 2-31: Transmit buffer queue pointer address */
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/* Receive Status Register */
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#define EMAC_RSR_BNA (1 << 0) /* Bit 0: Buffer Not Available */
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#define EMAC_RSR_REC (1 << 1) /* Bit 1: Frame Received */
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#define EMAC_RSR_OVR (1 << 2) /* Bit 2: Receive Overrun */
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/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */
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#define EMAC_INT_MFD (1 << 0) /* Bit 0: Management Frame Done */
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#define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */
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#define EMAC_INT_RXUBR (1 << 2) /* Bit 2: Receive Used Bit Read */
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#define EMAC_INT_TXUBR (1 << 3) /* Bit 3: Transmit Used Bit Read */
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#define EMAC_INT_TUND (1 << 4) /* Bit 4: Ethernet Transmit Buffer Underrun */
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#define EMAC_INT_RLE (1 << 5) /* Bit 5: Retry Limit Exceeded */
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#define EMAC_INT_TXERR (1 << 6) /* Bit 6: Transmit Error */
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#define EMAC_INT_TCOMP (1 << 7) /* Bit 7: Transmit Complete */
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#define EMAC_INT_ROVR (1 << 10) /* Bit 10: Receive Overrun */
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#define EMAC_INT_HRESP (1 << 11) /* Bit 11: Hresp not OK */
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#define EMAC_INT_PFR (1 << 12) /* Bit 12: Pause Frame Received */
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#define EMAC_INT_PTZ (1 << 13) /* Bit 13: Pause Time Zero */
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#define EMAC_INT_WOL (1 << 14) /* Bit 14: Wake On LAN */
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/* Phy Maintenance Register */
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#define EMAC_MAN_DATA_SHIFT (0) /* Bits 0-15: Read/write data */
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#define EMAC_MAN_DATA_MASK (0x0000ffff << EMAC_MAN_DATA_SHIFT)
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# define EMAC_MAN_DATA(n) ((n) << EMAC_MAN_DATA_SHIFT)
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#define EMAC_MAN_CODE_SHIFT (16) /* Bits 16-17: Must be written to b10 */
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#define EMAC_MAN_CODE_MASK (3 << EMAC_MAN_CODE_SHIFT)
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# define EMAC_MAN_CODE (2 << EMAC_MAN_CODE_SHIFT)
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#define EMAC_MAN_REGA_SHIFT (18) /* Bits 18-22: Register Address */
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#define EMAC_MAN_REGA_MASK (31 << EMAC_MAN_REGA_SHIFT)
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# define EMAC_MAN_REGA(n) ((n) << EMAC_MAN_REGA_SHIFT)
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#define EMAC_MAN_PHYA_SHIFT (23) /* Bits 23-27: PHY Address */
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#define EMAC_MAN_PHYA_MASK (31 << EMAC_MAN_PHYA_SHIFT)
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# define EMAC_MAN_PHYA(n) ((n) << EMAC_MAN_PHYA_SHIFT)
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#define EMAC_MAN_RW_SHIFT (28) /* Bits 28-29: Read-write */
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#define EMAC_MAN_RW_MASK (3 << EMAC_MAN_RW_SHIFT)
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# define EMAC_MAN_READ (2 << EMAC_MAN_RW_SHIFT)
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# define EMAC_MAN_WRITE (1 << EMAC_MAN_RW_SHIFT)
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#define EMAC_MAN_SOF_SHIFT (30) /* Bits 30-31: Start of frame */
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#define EMAC_MAN_SOF_MASK (3 << EMAC_MAN_SOF_SHIFT)
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# define EMAC_MAN_SOF_MASK (1 << EMAC_MAN_SOF_SHIFT) /* Must be written b01 */
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/* Pause Time Register */
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#define EMAC_PTR_MASK (0x0000ffff) /* Bits 0-15: Pause Time */
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/* Pause Frames Received Register */
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#define EMAC_PFR_MASK (0x0000ffff) /* Bits 0-15: Pause Frames received OK */
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/* Frames Transmitted Ok Register */
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#define EMAC_FTO_MASK (0x00ffffff) /* Bits 0-23: Frames Transmitted OK */
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/* Single Collision Frames Register */
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#define EMAC_SCF_MASK (0x0000ffff) /* Bits 0-15: Single Collision Frames */
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/* Multiple Collision Frames Register */
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#define EMAC_MCF_MASK (0x0000ffff) /* Bits 0-15: Multicollision Frames */
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||||
/* Frames Received Ok Register */
|
||||
|
||||
#define EMAC_FRO_MASK (0x00ffffff) /* Bits 0-23: Frames received OK */
|
||||
|
||||
/* Frame Check Sequence Errors Register */
|
||||
|
||||
#define EMAC_FCSE_MASK (0x000000ff) /* Bits 0-7:Frame Check Sequence Errors */
|
||||
|
||||
/* Alignment Errors Register */
|
||||
|
||||
#define EMAC_ALE_MASK (0x000000ff) /* Bits 0-7:Alignment Errors */
|
||||
|
||||
/* Deferred Transmission Frames Register */
|
||||
|
||||
#define EMAC_DTF_MASK (0x0000ffff) /* Bits 0-15: Deferred Transmission Frames */
|
||||
|
||||
/* Late Collisions Register */
|
||||
|
||||
#define EMAC_LCOL_MASK (0x000000ff) /* Bits 0-7: Late Collisions */
|
||||
|
||||
/* Excessive Collisions Register */
|
||||
|
||||
#define EMAC_ECOL_MASK (0x000000ff) /* Bits 0-7: Excessive Collisions Register */
|
||||
|
||||
/* Transmit Underrun Errors Register */
|
||||
|
||||
#define EMAC_TUND_MASK (0x000000ff) /* Bits 0-7: Transmit Underruns */
|
||||
|
||||
/* Carrier Sense Errors Register */
|
||||
|
||||
#define EMAC_CSE_MASK (0x000000ff) /* Bits 0-7: Carrier Sense Errors */
|
||||
|
||||
/* Receive Resource Errors Register */
|
||||
|
||||
#define EMAC_RRE_MASK (0x0000ffff) /* Bits 0-15: Receive Resource Errors */
|
||||
|
||||
/* Receive Overrun Errors Register */
|
||||
|
||||
#define EMAC_ROV_MASK (0x000000ff) /* Bits 0-7: Receive Overrun */
|
||||
|
||||
/* Receive Symbol Errors Register */
|
||||
|
||||
#define EMAC_RSE_MASK (0x000000ff) /* Bits 0-7: Receive Symbol Errors */
|
||||
|
||||
/* Excessive Length Errors Register */
|
||||
|
||||
#define EMAC_ELE_MASK (0x000000ff) /* Bits 0-7: Excessive Length Errors */
|
||||
|
||||
/* Receive Jabbers Register */
|
||||
|
||||
#define EMAC_RJA_MASK (0x000000ff) /* Bits 0-7: Receive Jabbers */
|
||||
|
||||
/* Undersize Frames Register */
|
||||
|
||||
#define EMAC_USF_MASK (0x000000ff) /* Bits 0-7: Undersize frames */
|
||||
|
||||
/* SQE Test Errors Register */
|
||||
|
||||
#define EMAC_STE_MASK (0x000000ff) /* Bits 0-7: SQE test errors */
|
||||
|
||||
/* Received Length Field Mismatch Register */
|
||||
|
||||
#define EMAC_RLE_MASK (0x000000ff) /* Bits 0-7: Receive Length Field Mismatch */
|
||||
|
||||
/* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */
|
||||
/* Hash Register Top [63:32] Register (MS 32-bit hash address) */
|
||||
|
||||
/* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 1 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA1T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 2 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA2T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 3 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA3T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */
|
||||
/* Specific Address 4 Top [47:32] Register */
|
||||
|
||||
#define EMAC_SA4T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
|
||||
|
||||
/* Type ID Checking Register */
|
||||
|
||||
#define EMAC_TID_MASK (0x0000ffff) /* Bits 0-15: For comparisons with received frames TypeID/Length field. */
|
||||
|
||||
/* User Input/Output Register */
|
||||
|
||||
#define EMAC_USRIO_RMII (1 << 0) /* Bit 0: Reduce MII */
|
||||
#define EMAC_USRIO_CLKEN (1 << 1) /* Bit 1: Clock Enable */
|
||||
|
||||
/* Wake on LAN Register */
|
||||
|
||||
#define EMAC_WOL_IP_SHIFT (0) /* Bits 0-15: ARP request IP address */
|
||||
#define EMAC_WOL_IP_MASK (0x0000ffff << EMAC_WOL_IP_SHIFT)
|
||||
#define EMAC_WOL_MAG (1 << 16) /* Bit 16: Magic packet event enable */
|
||||
#define EMAC_WOL_ARP (1 << 17) /* Bit 17: ARP request event enable */
|
||||
#define EMAC_WOL_SA1 (1 << 18) /* Bit 18: Specific address register 1 event enable */
|
||||
#define EMAC_WOL_MTI (1 << 19) /* Bit 19: Multicast hash event enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */
|
||||
|
||||
@ -48,14 +48,611 @@
|
||||
************************************************************************************/
|
||||
/* GMAC Register Offsets ************************************************************/
|
||||
|
||||
#define SAM_GMAC_
|
||||
#define SAM_GMAC_NCR_OFFSET 0x0000 /* Network Control Register */
|
||||
#define SAM_GMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
|
||||
#define SAM_GMAC_NSR_OFFSET 0x0008 /* Network Status Register */
|
||||
#define SAM_GMAC_UR_OFFSET 0x000c /* User Register */
|
||||
#define SAM_GMAC_DCFGR_OFFSET 0x0010 /* DMA Configuration Register */
|
||||
#define SAM_GMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
|
||||
#define SAM_GMAC_RBQB_OFFSET 0x0018 /* Receive Buffer Queue Base Address */
|
||||
#define SAM_GMAC_TBQB_OFFSET 0x001c /* Transmit Buffer Queue Base Address */
|
||||
#define SAM_GMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
|
||||
#define SAM_GMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
|
||||
#define SAM_GMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
|
||||
#define SAM_GMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
|
||||
#define SAM_GMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
|
||||
#define SAM_GMAC_MAN_OFFSET 0x0034 /* PHY Maintenance Register */
|
||||
#define SAM_GMAC_RPQ_OFFSET 0x0038 /* Received Pause Quantum Register */
|
||||
#define SAM_GMAC_TPQ_OFFSET 0x003c /* Transmit Pause Quantum Register */
|
||||
#define SAM_GMAC_TPSF_OFFSET 0x0040 /* TX Partial Store and Forward Register */
|
||||
#define SAM_GMAC_RPSF_OFFSET 0x0044 /* RX Partial Store and Forward Register */
|
||||
/* 0x0048-0x007c Reserved */
|
||||
#define SAM_GMAC_HRB_OFFSET 0x0080 /* Hash Register Bottom [31:0] */
|
||||
#define SAM_GMAC_HRT_OFFSET 0x0084 /* Hash Register Top [63:32] */
|
||||
#define SAM_GMAC_SAB_OFFSET(n) (0x0088 + (((n)-1) << 3)) /* n=1..4 */
|
||||
#define SAM_GMAC_SAT_OFFSET(n) (0x008c + (((n)-1) << 3)) /* n=1..4 */
|
||||
#define SAM_GMAC_SAB1_OFFSET 0x0088 /* Specific Address 1 Bottom [31:0] Register */
|
||||
#define SAM_GMAC_SAT1_OFFSET 0x008c /* Specific Address 1 Top [47:32] Register */
|
||||
#define SAM_GMAC_SAB2_OFFSET 0x0090 /* Specific Address 2 Bottom [31:0] Register */
|
||||
#define SAM_GMAC_SAT2_OFFSET 0x0094 /* Specific Address 2 Top [47:32] Register */
|
||||
#define SAM_GMAC_SAB3_OFFSET 0x0098 /* Specific Address 3 Bottom [31:0] Register */
|
||||
#define SAM_GMAC_SAT3_OFFSET 0x009c /* Specific Address 3 Top [47:32] Register */
|
||||
#define SAM_GMAC_SAB4_OFFSET 0x00a0 /* Specific Address 4 Bottom [31:0] Register */
|
||||
#define SAM_GMAC_SAT4_OFFSET 0x00a4 /* Specific Address 4 Top [47:32] Register */
|
||||
#define SAM_GMAC_TIDM_OFFSET(n) (0x00a8 + (((n)-1) << 2)) /* n=1..4 */
|
||||
#define SAM_GMAC_TIDM1_OFFSET 0x00a8 /* Type ID Match 1 Register */
|
||||
#define SAM_GMAC_TIDM2_OFFSET 0x00ac /* Type ID Match 2 Register */
|
||||
#define SAM_GMAC_TIDM3_OFFSET 0x00b0 /* Type ID Match 3 Register */
|
||||
#define SAM_GMAC_TIDM4_OFFSET 0x00b4 /* Type ID Match 4 Register */
|
||||
#define SAM_GMAC_WOL_OFFSET 0x00b8 /* Wake on LAN Register */
|
||||
#define SAM_GMAC_IPGS_OFFSET 0x00bc /* IPG Stretch Register */
|
||||
#define SAM_GMAC_SVLAN_OFFSET 0x00c0 /* Stacked VLAN Register */
|
||||
#define SAM_GMAC_TPFCP_OFFSET 0x00c4 /* Transmit PFC Pause Register */
|
||||
#define SAM_GMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */
|
||||
#define SAM_GMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */
|
||||
/* 0x00fc Reserved */
|
||||
#define SAM_GMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */
|
||||
#define SAM_GMAC_OTHI_OFFSET 0x0104 /* Octets Transmitted [47:32] Register */
|
||||
#define SAM_GMAC_FT_OFFSET 0x0108 /* Frames Transmitted Register */
|
||||
#define SAM_GMAC_BCFT_OFFSET 0x010c /* Broadcast Frames Transmitted Register */
|
||||
#define SAM_GMAC_MFT_OFFSET 0x0110 /* Multicast Frames Transmitted Register */
|
||||
#define SAM_GMAC_PFT_OFFSET 0x0114 /* Pause Frames Transmitted Register */
|
||||
#define SAM_GMAC_BFT64_OFFSET 0x0118 /* 64 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TBFT127_OFFSET 0x011c /* 65 to 127 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TBFT255_OFFSET 0x0120 /* 128 to 255 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TBFT511_OFFSET 0x0124 /* 256 to 511 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TBFT1023_OFFSET 0x0128 /* 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TBFT1518_OFFSET 0x012c /* 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_GTBFT1518_OFFSET 0x0130 /* Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define SAM_GMAC_TUR_OFFSET 0x0134 /* Transmit Under Runs Register */
|
||||
#define SAM_GMAC_SCF_OFFSET 0x0138 /* Single Collision Frames Register */
|
||||
#define SAM_GMAC_MCF_OFFSET 0x013c /* Multiple Collision Frames Register */
|
||||
#define SAM_GMAC_EC_OFFSET 0x0140 /* Excessive Collisions Register */
|
||||
#define SAM_GMAC_LC_OFFSET 0x0144 /* Late Collisions Register */
|
||||
#define SAM_GMAC_DTF_OFFSET 0x0148 /* Deferred Transmission Frames Register */
|
||||
#define SAM_GMAC_CSE_OFFSET 0x014c /* Carrier Sense Errors Register */
|
||||
#define SAM_GMAC_ORLO_OFFSET 0x0150 /* Octets Received [31:0] Received */
|
||||
#define SAM_GMAC_ORHI_OFFSET 0x0154 /* Octets Received [47:32] Received */
|
||||
#define SAM_GMAC_FR_OFFSET 0x0158 /* Frames Received Register */
|
||||
#define SAM_GMAC_BCFR_OFFSET 0x015c /* Broadcast Frames Received Register */
|
||||
#define SAM_GMAC_MFR_OFFSET 0x0160 /* Multicast Frames Received Register */
|
||||
#define SAM_GMAC_PFR_OFFSET 0x0164 /* Pause Frames Received Register */
|
||||
#define SAM_GMAC_BFR64_OFFSET 0x0168 /* 64 Byte Frames Received Register */
|
||||
#define SAM_GMAC_TBFR127_OFFSET 0x016c /* 65 to 127 Byte Frames Received Register */
|
||||
#define SAM_GMAC_TBFR255_OFFSET 0x0170 /* 128 to 255 Byte Frames Received Register */
|
||||
#define SAM_GMAC_TBFR511_OFFSET 0x0174 /* 256 to 511Byte Frames Received Register */
|
||||
#define SAM_GMAC_TBFR1023_OFFSET 0x0178 /* 512 to 1023 Byte Frames Received Register */
|
||||
#define SAM_GMAC_TBFR1518_OFFSET 0x017c /* 1024 to 1518 Byte Frames Received Register */
|
||||
#define SAM_GMAC_TMXBFR_OFFSET 0x0180 /* 1519 to Maximum Byte Frames Received Register */
|
||||
#define SAM_GMAC_UFR_OFFSET 0x0184 /* Undersize Frames Received Register */
|
||||
#define SAM_GMAC_OFR_OFFSET 0x0188 /* Oversize Frames Received Register */
|
||||
#define SAM_GMAC_JR_OFFSET 0x018c /* Jabbers Received Register */
|
||||
#define SAM_GMAC_FCSE_OFFSET 0x0190 /* Frame Check Sequence Errors Register */
|
||||
#define SAM_GMAC_LFFE_OFFSET 0x0194 /* Length Field Frame Errors Register */
|
||||
#define SAM_GMAC_RSE_OFFSET 0x0198 /* Receive Symbol Errors Register */
|
||||
#define SAM_GMAC_AE_OFFSET 0x019c /* Alignment Errors Register */
|
||||
#define SAM_GMAC_RRE_OFFSET 0x01a0 /* Receive Resource Errors Register */
|
||||
#define SAM_GMAC_ROE_OFFSET 0x01a4 /* Receive Overrun Register */
|
||||
#define SAM_GMAC_IHCE_OFFSET 0x01a8 /* IP Header Checksum Errors Register */
|
||||
#define SAM_GMAC_TCE_OFFSET 0x01ac /* TCP Checksum Errors Register */
|
||||
#define SAM_GMAC_UCE_OFFSET 0x01b0 /* UDP Checksum Errors Register */
|
||||
#define SAM_GMAC_TSSS_OFFSET 0x01c8 /* 1588 Timer Sync Strobe Seconds Register */
|
||||
#define SAM_GMAC_TSSN_OFFSET 0x01cc /* 1588 Timer Sync Strobe Nanoseconds Register */
|
||||
#define SAM_GMAC_TS_OFFSET 0x01d0 /* 1588 Timer Seconds Register */
|
||||
#define SAM_GMAC_TN_OFFSET 0x01d4 /* 1588 Timer Nanoseconds Register */
|
||||
#define SAM_GMAC_TA_OFFSET 0x01d8 /* 1588 Timer Adjust Register */
|
||||
#define SAM_GMAC_TI_OFFSET 0x01dc /* 1588 Timer Increment Register */
|
||||
#define SAM_GMAC_EFTS_OFFSET 0x01e0 /* PTP Event Frame Transmitted Seconds */
|
||||
#define SAM_GMAC_EFTN_OFFSET 0x01e4 /* PTP Event Frame Transmitted Nanoseconds */
|
||||
#define SAM_GMAC_EFRS_OFFSET 0x01e8 /* PTP Event Frame Received Seconds */
|
||||
#define SAM_GMAC_EFRN_OFFSET 0x01ec /* PTP Event Frame Received Nanoseconds */
|
||||
#define SAM_GMAC_PEFTS_OFFSET 0x01f0 /* PTP Peer Event Frame Transmitted Seconds */
|
||||
#define SAM_GMAC_PEFTN_OFFSET 0x01f4 /* PTP Peer Event Frame Transmitted Nanoseconds */
|
||||
#define SAM_GMAC_PEFRS_OFFSET 0x01f8 /* PTP Peer Event Frame ReceiveGMAC_PEFRNd Seconds */
|
||||
#define SAM_GMAC_PEFRS_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
|
||||
/* 0x0200-0x023c Reserved */
|
||||
/* 0x0280-0x0298 Reserved */
|
||||
#define SAM_GMAC_ISRPQ_OFFSET(n) (0x400 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_ISRPQ0_OFFSET 0x400 /* Interrupt Status Register Priority Queue 0 */
|
||||
#define SAM_GMAC_ISRPQ1_OFFSET 0x404 /* Interrupt Status Register Priority Queue 1 */
|
||||
#define SAM_GMAC_ISRPQ2_OFFSET 0x408 /* Interrupt Status Register Priority Queue 2 */
|
||||
#define SAM_GMAC_ISRPQ3_OFFSET 0x40c /* Interrupt Status Register Priority Queue 3 */
|
||||
#define SAM_GMAC_ISRPQ4_OFFSET 0x410 /* Interrupt Status Register Priority Queue 4 */
|
||||
#define SAM_GMAC_ISRPQ5_OFFSET 0x414 /* Interrupt Status Register Priority Queue 5 */
|
||||
#define SAM_GMAC_ISRPQ6_OFFSET 0x418 /* Interrupt Status Register Priority Queue 6 */
|
||||
#define SAM_GMAC_TBQBAPQ_OFFSET(n) (0x440 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_TBQBAPQ0_OFFSET 0x440 /* Transmit Buffer Queue Base Address Priority Queue 0 */
|
||||
#define SAM_GMAC_TBQBAPQ1_OFFSET 0x444 /* Transmit Buffer Queue Base Address Priority Queue 1 */
|
||||
#define SAM_GMAC_TBQBAPQ2_OFFSET 0x448 /* Transmit Buffer Queue Base Address Priority Queue 2 */
|
||||
#define SAM_GMAC_TBQBAPQ3_OFFSET 0x44c /* Transmit Buffer Queue Base Address Priority Queue 3 */
|
||||
#define SAM_GMAC_TBQBAPQ4_OFFSET 0x450 /* Transmit Buffer Queue Base Address Priority Queue 4 */
|
||||
#define SAM_GMAC_TBQBAPQ5_OFFSET 0x454 /* Transmit Buffer Queue Base Address Priority Queue 5 */
|
||||
#define SAM_GMAC_TBQBAPQ6_OFFSET 0x458 /* Transmit Buffer Queue Base Address Priority Queue 6 */
|
||||
#define SAM_GMAC_RBQBAPQ_OFFSET(n) (0x480 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_RBQBAPQ0_OFFSET 0x480 /* Receive Buffer Queue Base Address Priority Queue 0 */
|
||||
#define SAM_GMAC_RBQBAPQ1_OFFSET 0x484 /* Receive Buffer Queue Base Address Priority Queue 1 */
|
||||
#define SAM_GMAC_RBQBAPQ2_OFFSET 0x488 /* Receive Buffer Queue Base Address Priority Queue 2 */
|
||||
#define SAM_GMAC_RBQBAPQ3_OFFSET 0x48c /* Receive Buffer Queue Base Address Priority Queue 3 */
|
||||
#define SAM_GMAC_RBQBAPQ4_OFFSET 0x490 /* Receive Buffer Queue Base Address Priority Queue 4 */
|
||||
#define SAM_GMAC_RBQBAPQ5_OFFSET 0x494 /* Receive Buffer Queue Base Address Priority Queue 5 */
|
||||
#define SAM_GMAC_RBQBAPQ6_OFFSET 0x498 /* Receive Buffer Queue Base Address Priority Queue 6 */
|
||||
#define SAM_GMAC_RBSRPQ_OFFSET(n) (0x4a0 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_RBSRPQ0_OFFSET 0x4a0 /* Receive Buffer Size Register Priority Queue 0 */
|
||||
#define SAM_GMAC_RBSRPQ1_OFFSET 0x4a4 /* Receive Buffer Size Register Priority Queue 1 */
|
||||
#define SAM_GMAC_RBSRPQ2_OFFSET 0x4a8 /* Receive Buffer Size Register Priority Queue 2 */
|
||||
#define SAM_GMAC_RBSRPQ3_OFFSET 0x4ac /* Receive Buffer Size Register Priority Queue 3 */
|
||||
#define SAM_GMAC_RBSRPQ4_OFFSET 0x4b0 /* Receive Buffer Size Register Priority Queue 4 */
|
||||
#define SAM_GMAC_RBSRPQ5_OFFSET 0x4b4 /* Receive Buffer Size Register Priority Queue 5 */
|
||||
#define SAM_GMAC_RBSRPQ6_OFFSET 0x4b8 /* Receive Buffer Size Register Priority Queue 6 */
|
||||
#define SAM_GMAC_ST1RPQ_OFFSET(n) (0x500 + ((n) << 2)) /* n=0..15 */
|
||||
#define SAM_GMAC_ST1RPQ0_OFFSET 0x500 /* Screening Type1 Register Priority Queue 0 */
|
||||
#define SAM_GMAC_ST1RPQ1_OFFSET 0x504 /* Screening Type1 Register Priority Queue 1 */
|
||||
#define SAM_GMAC_ST1RPQ2_OFFSET 0x508 /* Screening Type1 Register Priority Queue 2 */
|
||||
#define SAM_GMAC_ST1RPQ3_OFFSET 0x50c /* Screening Type1 Register Priority Queue 3 */
|
||||
#define SAM_GMAC_ST1RPQ4_OFFSET 0x510 /* Screening Type1 Register Priority Queue 4 */
|
||||
#define SAM_GMAC_ST1RPQ5_OFFSET 0x514 /* Screening Type1 Register Priority Queue 5 */
|
||||
#define SAM_GMAC_ST1RPQ6_OFFSET 0x518 /* Screening Type1 Register Priority Queue 6 */
|
||||
#define SAM_GMAC_ST1RPQ7_OFFSET 0x51c /* Screening Type1 Register Priority Queue 7 */
|
||||
#define SAM_GMAC_ST1RPQ8_OFFSET 0x520 /* Screening Type1 Register Priority Queue 8 */
|
||||
#define SAM_GMAC_ST1RPQ9_OFFSET 0x524 /* Screening Type1 Register Priority Queue 9 */
|
||||
#define SAM_GMAC_ST1RPQ10_OFFSET 0x528 /* Screening Type1 Register Priority Queue 10 */
|
||||
#define SAM_GMAC_ST1RPQ11_OFFSET 0x52c /* Screening Type1 Register Priority Queue 11 */
|
||||
#define SAM_GMAC_ST1RPQ12_OFFSET 0x530 /* Screening Type1 Register Priority Queue 12 */
|
||||
#define SAM_GMAC_ST1RPQ13_OFFSET 0x534 /* Screening Type1 Register Priority Queue 13 */
|
||||
#define SAM_GMAC_ST1RPQ14_OFFSET 0x538 /* Screening Type1 Register Priority Queue 14 */
|
||||
#define SAM_GMAC_ST1RPQ15_OFFSET 0x53c /* Screening Type1 Register Priority Queue 15 */
|
||||
#define SAM_GMAC_ST2RPQ_OFFSET(n) (0x540 + ((n) << 2)) /* n=0..15 */
|
||||
#define SAM_GMAC_ST2RPQ0_OFFSET 0x540 /* Screening Type2 Register Priority Queue 0 */
|
||||
#define SAM_GMAC_ST2RPQ1_OFFSET 0x544 /* Screening Type2 Register Priority Queue 1 */
|
||||
#define SAM_GMAC_ST2RPQ2_OFFSET 0x548 /* Screening Type2 Register Priority Queue 2 */
|
||||
#define SAM_GMAC_ST2RPQ3_OFFSET 0x54c /* Screening Type2 Register Priority Queue 3 */
|
||||
#define SAM_GMAC_ST2RPQ4_OFFSET 0x550 /* Screening Type2 Register Priority Queue 4 */
|
||||
#define SAM_GMAC_ST2RPQ5_OFFSET 0x554 /* Screening Type2 Register Priority Queue 5 */
|
||||
#define SAM_GMAC_ST2RPQ6_OFFSET 0x558 /* Screening Type2 Register Priority Queue 6 */
|
||||
#define SAM_GMAC_ST2RPQ7_OFFSET 0x55c /* Screening Type2 Register Priority Queue 7 */
|
||||
#define SAM_GMAC_ST2RPQ8_OFFSET 0x560 /* Screening Type2 Register Priority Queue 8 */
|
||||
#define SAM_GMAC_ST2RPQ9_OFFSET 0x564 /* Screening Type2 Register Priority Queue 9 */
|
||||
#define SAM_GMAC_ST2RPQ10_OFFSET 0x568 /* Screening Type2 Register Priority Queue 10 */
|
||||
#define SAM_GMAC_ST2RPQ11_OFFSET 0x56c /* Screening Type2 Register Priority Queue 11 */
|
||||
#define SAM_GMAC_ST2RPQ12_OFFSET 0x570 /* Screening Type2 Register Priority Queue 12 */
|
||||
#define SAM_GMAC_ST2RPQ13_OFFSET 0x574 /* Screening Type2 Register Priority Queue 13 */
|
||||
#define SAM_GMAC_ST2RPQ14_OFFSET 0x578 /* Screening Type2 Register Priority Queue 14 */
|
||||
#define SAM_GMAC_ST2RPQ15_OFFSET 0x57c /* Screening Type2 Register Priority Queue 15 */
|
||||
#define SAM_GMAC_IERPQ_OFFSET(n) (0x600 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_IERPQ0_OFFSET 0x600 /* Interrupt Enable Register Priority Queue 0 */
|
||||
#define SAM_GMAC_IERPQ1_OFFSET 0x604 /* Interrupt Enable Register Priority Queue 1 */
|
||||
#define SAM_GMAC_IERPQ2_OFFSET 0x608 /* Interrupt Enable Register Priority Queue 2 */
|
||||
#define SAM_GMAC_IERPQ3_OFFSET 0x60c /* Interrupt Enable Register Priority Queue 3 */
|
||||
#define SAM_GMAC_IERPQ4_OFFSET 0x610 /* Interrupt Enable Register Priority Queue 4 */
|
||||
#define SAM_GMAC_IERPQ5_OFFSET 0x614 /* Interrupt Enable Register Priority Queue 5 */
|
||||
#define SAM_GMAC_IERPQ6_OFFSET 0x618 /* Interrupt Enable Register Priority Queue 6 */
|
||||
#define SAM_GMAC_IDRPQ_OFFSET(n) (0x620 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_IDRPQ0_OFFSET 0x620 /* Interrupt Disable Register Priority Queue 0 */
|
||||
#define SAM_GMAC_IDRPQ1_OFFSET 0x624 /* Interrupt Disable Register Priority Queue 1 */
|
||||
#define SAM_GMAC_IDRPQ2_OFFSET 0x628 /* Interrupt Disable Register Priority Queue 2 */
|
||||
#define SAM_GMAC_IDRPQ3_OFFSET 0x62c /* Interrupt Disable Register Priority Queue 3 */
|
||||
#define SAM_GMAC_IDRPQ4_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 4 */
|
||||
#define SAM_GMAC_IDRPQ5_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 5 */
|
||||
#define SAM_GMAC_IDRPQ6_OFFSET 0x638 /* Interrupt Disable Register Priority Queue 6 */
|
||||
#define SAM_GMAC_IMRPQ_OFFSET(n) (0x640 + ((n) << 2)) /* n=0..6 */
|
||||
#define SAM_GMAC_IMRPQ0_OFFSET 0x640 /* Interrupt Mask Register Priority Queue 0 */
|
||||
#define SAM_GMAC_IMRPQ1_OFFSET 0x644 /* Interrupt Mask Register Priority Queue 1 */
|
||||
#define SAM_GMAC_IMRPQ2_OFFSET 0x648 /* Interrupt Mask Register Priority Queue 2 */
|
||||
#define SAM_GMAC_IMRPQ3_OFFSET 0x64c /* Interrupt Mask Register Priority Queue 3 */
|
||||
#define SAM_GMAC_IMRPQ4_OFFSET 0x650 /* Interrupt Mask Register Priority Queue 4 */
|
||||
#define SAM_GMAC_IMRPQ5_OFFSET 0x654 /* Interrupt Mask Register Priority Queue 5 */
|
||||
#define SAM_GMAC_IMRPQ6_OFFSET 0x658 /* Interrupt Mask Register Priority Queue 6 */
|
||||
|
||||
/* GMAC Register Addresses *********************************************************/
|
||||
|
||||
#define SAM_GMAC_
|
||||
#define SAM_GMAC_NCR (SAM_GMAC_VBASE+SAM_GMAC_NCR_OFFSET)
|
||||
#define SAM_GMAC_NCFGR (SAM_GMAC_VBASE+SAM_GMAC_NCFGR_OFFSET)
|
||||
#define SAM_GMAC_NSR (SAM_GMAC_VBASE+SAM_GMAC_NSR_OFFSET)
|
||||
#define SAM_GMAC_UR (SAM_GMAC_VBASE+SAM_GMAC_UR_OFFSET)
|
||||
#define SAM_GMAC_DCFGR (SAM_GMAC_VBASE+SAM_GMAC_DCFGR_OFFSET)
|
||||
#define SAM_GMAC_TSR (SAM_GMAC_VBASE+SAM_GMAC_TSR_OFFSET)
|
||||
#define SAM_GMAC_RBQB (SAM_GMAC_VBASE+SAM_GMAC_RBQB_OFFSET)
|
||||
#define SAM_GMAC_TBQB (SAM_GMAC_VBASE+SAM_GMAC_TBQB_OFFSET)
|
||||
#define SAM_GMAC_RSR (SAM_GMAC_VBASE+SAM_GMAC_RSR_OFFSET)
|
||||
#define SAM_GMAC_ISR (SAM_GMAC_VBASE+SAM_GMAC_ISR_OFFSET)
|
||||
#define SAM_GMAC_IER (SAM_GMAC_VBASE+SAM_GMAC_IER_OFFSET)
|
||||
#define SAM_GMAC_IDR (SAM_GMAC_VBASE+SAM_GMAC_IDR_OFFSET)
|
||||
#define SAM_GMAC_IMR (SAM_GMAC_VBASE+SAM_GMAC_IMR_OFFSET)
|
||||
#define SAM_GMAC_MAN (SAM_GMAC_VBASE+SAM_GMAC_MAN_OFFSET)
|
||||
#define SAM_GMAC_RPQ (SAM_GMAC_VBASE+SAM_GMAC_RPQ_OFFSET)
|
||||
#define SAM_GMAC_TPQ (SAM_GMAC_VBASE+SAM_GMAC_TPQ_OFFSET)
|
||||
#define SAM_GMAC_TPSF (SAM_GMAC_VBASE+SAM_GMAC_TPSF_OFFSET)
|
||||
#define SAM_GMAC_RPSF (SAM_GMAC_VBASE+SAM_GMAC_RPSF_OFFSET)
|
||||
#define SAM_GMAC_HRB (SAM_GMAC_VBASE+SAM_GMAC_HRB_OFFSET)
|
||||
#define SAM_GMAC_HRT (SAM_GMAC_VBASE+SAM_GMAC_HRT_OFFSET)
|
||||
#define SAM_GMAC_SAB(n) (SAM_GMAC_VBASE+SAM_GMAC_SAB_OFFSET(n))
|
||||
#define SAM_GMAC_SAT(n) (SAM_GMAC_VBASE+SAM_GMAC_SAT_OFFSET(n))
|
||||
#define SAM_GMAC_SAB1 (SAM_GMAC_VBASE+SAM_GMAC_SAB1_OFFSET)
|
||||
#define SAM_GMAC_SAT1 (SAM_GMAC_VBASE+SAM_GMAC_SAT1_OFFSET)
|
||||
#define SAM_GMAC_SAB2 (SAM_GMAC_VBASE+SAM_GMAC_SAB2_OFFSET)
|
||||
#define SAM_GMAC_SAT2 (SAM_GMAC_VBASE+SAM_GMAC_SAT2_OFFSET)
|
||||
#define SAM_GMAC_SAB3 (SAM_GMAC_VBASE+SAM_GMAC_SAB3_OFFSET)
|
||||
#define SAM_GMAC_SAT3 (SAM_GMAC_VBASE+SAM_GMAC_SAT3_OFFSET)
|
||||
#define SAM_GMAC_SAB4 (SAM_GMAC_VBASE+SAM_GMAC_SAB4_OFFSET)
|
||||
#define SAM_GMAC_SAT4 (SAM_GMAC_VBASE+SAM_GMAC_SAT4_OFFSET)
|
||||
#define SAM_GMAC_TIDM(n) (SAM_GMAC_VBASE+SAM_GMAC_TIDM_OFFSET(n))
|
||||
#define SAM_GMAC_TIDM1 (SAM_GMAC_VBASE+SAM_GMAC_TIDM1_OFFSET)
|
||||
#define SAM_GMAC_TIDM2 (SAM_GMAC_VBASE+SAM_GMAC_TIDM2_OFFSET)
|
||||
#define SAM_GMAC_TIDM3 (SAM_GMAC_VBASE+SAM_GMAC_TIDM3_OFFSET)
|
||||
#define SAM_GMAC_TIDM4 (SAM_GMAC_VBASE+SAM_GMAC_TIDM4_OFFSET)
|
||||
#define SAM_GMAC_WOL (SAM_GMAC_VBASE+SAM_GMAC_WOL_OFFSET)
|
||||
#define SAM_GMAC_IPGS (SAM_GMAC_VBASE+SAM_GMAC_IPGS_OFFSET)
|
||||
#define SAM_GMAC_SVLAN (SAM_GMAC_VBASE+SAM_GMAC_SVLAN_OFFSET)
|
||||
#define SAM_GMAC_TPFCP (SAM_GMAC_VBASE+SAM_GMAC_TPFCP_OFFSET)
|
||||
#define SAM_GMAC_SAMB1 (SAM_GMAC_VBASE+SAM_GMAC_SAMB1_OFFSET)
|
||||
#define SAM_GMAC_SAMT1 (SAM_GMAC_VBASE+SAM_GMAC_SAMT1_OFFSET)
|
||||
#define SAM_GMAC_OTLO (SAM_GMAC_VBASE+SAM_GMAC_OTLO_OFFSET)
|
||||
#define SAM_GMAC_OTHI (SAM_GMAC_VBASE+SAM_GMAC_OTHI_OFFSET)
|
||||
#define SAM_GMAC_FT (SAM_GMAC_VBASE+SAM_GMAC_FT_OFFSET)
|
||||
#define SAM_GMAC_BCFT (SAM_GMAC_VBASE+SAM_GMAC_BCFT_OFFSET)
|
||||
#define SAM_GMAC_MFT (SAM_GMAC_VBASE+SAM_GMAC_MFT_OFFSET)
|
||||
#define SAM_GMAC_PFT (SAM_GMAC_VBASE+SAM_GMAC_PFT_OFFSET)
|
||||
#define SAM_GMAC_BFT64 (SAM_GMAC_VBASE+SAM_GMAC_BFT64_OFFSET)
|
||||
#define SAM_GMAC_TBFT127 (SAM_GMAC_VBASE+SAM_GMAC_TBFT127_OFFSET)
|
||||
#define SAM_GMAC_TBFT255 (SAM_GMAC_VBASE+SAM_GMAC_TBFT255_OFFSET)
|
||||
#define SAM_GMAC_TBFT511 (SAM_GMAC_VBASE+SAM_GMAC_TBFT511_OFFSET)
|
||||
#define SAM_GMAC_TBFT1023 (SAM_GMAC_VBASE+SAM_GMAC_TBFT1023_OFFSET)
|
||||
#define SAM_GMAC_TBFT1518 (SAM_GMAC_VBASE+SAM_GMAC_TBFT1518_OFFSET)
|
||||
#define SAM_GMAC_GTBFT1518 (SAM_GMAC_VBASE+SAM_GMAC_GTBFT1518_OFFSET)
|
||||
#define SAM_GMAC_TUR (SAM_GMAC_VBASE+SAM_GMAC_TUR_OFFSET)
|
||||
#define SAM_GMAC_SCF (SAM_GMAC_VBASE+SAM_GMAC_SCF_OFFSET)
|
||||
#define SAM_GMAC_MCF (SAM_GMAC_VBASE+SAM_GMAC_MCF_OFFSET)
|
||||
#define SAM_GMAC_EC (SAM_GMAC_VBASE+SAM_GMAC_EC_OFFSET)
|
||||
#define SAM_GMAC_LC (SAM_GMAC_VBASE+SAM_GMAC_LC_OFFSET)
|
||||
#define SAM_GMAC_DTF (SAM_GMAC_VBASE+SAM_GMAC_DTF_OFFSET)
|
||||
#define SAM_GMAC_CSE (SAM_GMAC_VBASE+SAM_GMAC_CSE_OFFSET)
|
||||
#define SAM_GMAC_ORLO (SAM_GMAC_VBASE+SAM_GMAC_ORLO_OFFSET)
|
||||
#define SAM_GMAC_ORHI (SAM_GMAC_VBASE+SAM_GMAC_ORHI_OFFSET)
|
||||
#define SAM_GMAC_FR (SAM_GMAC_VBASE+SAM_GMAC_FR_OFFSET)
|
||||
#define SAM_GMAC_BCFR (SAM_GMAC_VBASE+SAM_GMAC_BCFR_OFFSET)
|
||||
#define SAM_GMAC_MFR (SAM_GMAC_VBASE+SAM_GMAC_MFR_OFFSET)
|
||||
#define SAM_GMAC_PFR (SAM_GMAC_VBASE+SAM_GMAC_PFR_OFFSET)
|
||||
#define SAM_GMAC_BFR64 (SAM_GMAC_VBASE+SAM_GMAC_BFR64_OFFSET)
|
||||
#define SAM_GMAC_TBFR127 (SAM_GMAC_VBASE+SAM_GMAC_TBFR127_OFFSET)
|
||||
#define SAM_GMAC_TBFR255 (SAM_GMAC_VBASE+SAM_GMAC_TBFR255_OFFSET)
|
||||
#define SAM_GMAC_TBFR511 (SAM_GMAC_VBASE+SAM_GMAC_TBFR511_OFFSET)
|
||||
#define SAM_GMAC_TBFR1023 (SAM_GMAC_VBASE+SAM_GMAC_TBFR1023_OFFSET)
|
||||
#define SAM_GMAC_TBFR1518 (SAM_GMAC_VBASE+SAM_GMAC_TBFR1518_OFFSET)
|
||||
#define SAM_GMAC_TMXBFR (SAM_GMAC_VBASE+SAM_GMAC_TMXBFR_OFFSET)
|
||||
#define SAM_GMAC_UFR (SAM_GMAC_VBASE+SAM_GMAC_UFR_OFFSET)
|
||||
#define SAM_GMAC_OFR (SAM_GMAC_VBASE+SAM_GMAC_OFR_OFFSET)
|
||||
#define SAM_GMAC_JR (SAM_GMAC_VBASE+SAM_GMAC_JR_OFFSET)
|
||||
#define SAM_GMAC_FCSE (SAM_GMAC_VBASE+SAM_GMAC_FCSE_OFFSET)
|
||||
#define SAM_GMAC_LFFE (SAM_GMAC_VBASE+SAM_GMAC_LFFE_OFFSET)
|
||||
#define SAM_GMAC_RSE (SAM_GMAC_VBASE+SAM_GMAC_RSE_OFFSET)
|
||||
#define SAM_GMAC_AE (SAM_GMAC_VBASE+SAM_GMAC_AE_OFFSET)
|
||||
#define SAM_GMAC_RRE (SAM_GMAC_VBASE+SAM_GMAC_RRE_OFFSET)
|
||||
#define SAM_GMAC_ROE (SAM_GMAC_VBASE+SAM_GMAC_ROE_OFFSET)
|
||||
#define SAM_GMAC_IHCE (SAM_GMAC_VBASE+SAM_GMAC_IHCE_OFFSET)
|
||||
#define SAM_GMAC_TCE (SAM_GMAC_VBASE+SAM_GMAC_TCE_OFFSET)
|
||||
#define SAM_GMAC_UCE (SAM_GMAC_VBASE+SAM_GMAC_UCE_OFFSET)
|
||||
#define SAM_GMAC_TSSS (SAM_GMAC_VBASE+SAM_GMAC_TSSS_OFFSET)
|
||||
#define SAM_GMAC_TSSN (SAM_GMAC_VBASE+SAM_GMAC_TSSN_OFFSET)
|
||||
#define SAM_GMAC_TS (SAM_GMAC_VBASE+SAM_GMAC_TS_OFFSET)
|
||||
#define SAM_GMAC_TN (SAM_GMAC_VBASE+SAM_GMAC_TN_OFFSET)
|
||||
#define SAM_GMAC_TA (SAM_GMAC_VBASE+SAM_GMAC_TA_OFFSET)
|
||||
#define SAM_GMAC_TI (SAM_GMAC_VBASE+SAM_GMAC_TI_OFFSET)
|
||||
#define SAM_GMAC_EFTS (SAM_GMAC_VBASE+SAM_GMAC_EFTS_OFFSET)
|
||||
#define SAM_GMAC_EFTN (SAM_GMAC_VBASE+SAM_GMAC_EFTN_OFFSET)
|
||||
#define SAM_GMAC_EFRS (SAM_GMAC_VBASE+SAM_GMAC_EFRS_OFFSET)
|
||||
#define SAM_GMAC_EFRN (SAM_GMAC_VBASE+SAM_GMAC_EFRN_OFFSET)
|
||||
#define SAM_GMAC_PEFTS (SAM_GMAC_VBASE+SAM_GMAC_PEFTS_OFFSET)
|
||||
#define SAM_GMAC_PEFTN (SAM_GMAC_VBASE+SAM_GMAC_PEFTN_OFFSET)
|
||||
#define SAM_GMAC_PEFRS (SAM_GMAC_VBASE+SAM_GMAC_PEFRS_OFFSET)
|
||||
#define SAM_GMAC_PEFRS (SAM_GMAC_VBASE+SAM_GMAC_PEFRS_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ_OFFSET(n))
|
||||
#define SAM_GMAC_ISRPQ0 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ0_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ1 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ1_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ2 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ2_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ3 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ3_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ4 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ4_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ5 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ5_OFFSET)
|
||||
#define SAM_GMAC_ISRPQ6 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ6_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ_OFFSET(n))
|
||||
#define SAM_GMAC_TBQBAPQ0 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ0_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ1 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ1_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ2 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ2_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ3 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ3_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ4 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ4_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ5 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ5_OFFSET)
|
||||
#define SAM_GMAC_TBQBAPQ6 (SAM_GMAC_VBASE+SAM_GMAC_TBQBAPQ6_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ_OFFSET(n))
|
||||
#define SAM_GMAC_RBQBAPQ0 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ0_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ1 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ1_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ2 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ2_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ3 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ3_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ4 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ4_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ5 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ5_OFFSET)
|
||||
#define SAM_GMAC_RBQBAPQ6 (SAM_GMAC_VBASE+SAM_GMAC_RBQBAPQ6_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ_OFFSET(n))
|
||||
#define SAM_GMAC_RBSRPQ0 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ0_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ1 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ1_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ2 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ2_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ3 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ3_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ4 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ4_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ5 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ5_OFFSET)
|
||||
#define SAM_GMAC_RBSRPQ6 (SAM_GMAC_VBASE+SAM_GMAC_RBSRPQ6_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ_OFFSET(n))
|
||||
#define SAM_GMAC_ST1RPQ0 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ0_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ1 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ1_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ2 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ2_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ3 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ3_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ4 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ4_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ5 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ5_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ6 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ6_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ7 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ7_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ8 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ8_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ9 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ9_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ10 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ10_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ11 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ11_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ12 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ12_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ13 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ13_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ14 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ14_OFFSET)
|
||||
#define SAM_GMAC_ST1RPQ15 (SAM_GMAC_VBASE+SAM_GMAC_ST1RPQ15_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ_OFFSET(n))
|
||||
#define SAM_GMAC_ST2RPQ0 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ0_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ1 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ1_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ2 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ2_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ3 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ3_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ4 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ4_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ5 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ5_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ6 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ6_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ7 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ7_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ8 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ8_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ9 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ9_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ10 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ10_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ11 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ11_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ12 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ12_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ13 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ13_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ14 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ14_OFFSET)
|
||||
#define SAM_GMAC_ST2RPQ15 (SAM_GMAC_VBASE+SAM_GMAC_ST2RPQ15_OFFSET)
|
||||
#define SAM_GMAC_IERPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_IERPQ_OFFSET(n))
|
||||
#define SAM_GMAC_IERPQ0 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ0_OFFSET)
|
||||
#define SAM_GMAC_IERPQ1 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ1_OFFSET)
|
||||
#define SAM_GMAC_IERPQ2 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ2_OFFSET)
|
||||
#define SAM_GMAC_IERPQ3 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ3_OFFSET)
|
||||
#define SAM_GMAC_IERPQ4 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ4_OFFSET)
|
||||
#define SAM_GMAC_IERPQ5 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ5_OFFSET)
|
||||
#define SAM_GMAC_IERPQ6 (SAM_GMAC_VBASE+SAM_GMAC_IERPQ6_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ_OFFSET(n))
|
||||
#define SAM_GMAC_IDRPQ0 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ0_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ1 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ1_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ2 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ2_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ3 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ3_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ4 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ4_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ5 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ5_OFFSET)
|
||||
#define SAM_GMAC_IDRPQ6 (SAM_GMAC_VBASE+SAM_GMAC_IDRPQ6_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ_OFFSET(n))
|
||||
#define SAM_GMAC_IMRPQ0 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ0_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ1 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ1_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ2 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ2_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ3 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ3_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ4 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ4_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ5 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ5_OFFSET)
|
||||
#define SAM_GMAC_IMRPQ6 (SAM_GMAC_VBASE+SAM_GMAC_IMRPQ6_OFFSET)
|
||||
|
||||
/* GMAC Register Bit Definitions ***************************************************/
|
||||
|
||||
#define GMAC_
|
||||
/* Network Control Register */
|
||||
#define GMAC_NCR_
|
||||
/* Network Configuration Register */
|
||||
#define GMAC_NCFGR_
|
||||
/* Network Status Register */
|
||||
#define GMAC_NSR_
|
||||
/* User Register */
|
||||
#define GMAC_UR_
|
||||
/* DMA Configuration Register */
|
||||
#define GMAC_DCFGR_
|
||||
/* Transmit Status Register */
|
||||
#define GMAC_TSR_
|
||||
/* Receive Buffer Queue Base Address */
|
||||
#define GMAC_RBQB_
|
||||
/* Transmit Buffer Queue Base Address */
|
||||
#define GMAC_TBQB_
|
||||
/* Receive Status Register */
|
||||
#define GMAC_RSR_
|
||||
/* Interrupt Status Register */
|
||||
#define GMAC_ISR_
|
||||
/* Interrupt Enable Register */
|
||||
#define GMAC_IER_
|
||||
/* Interrupt Disable Register */
|
||||
#define GMAC_IDR_
|
||||
/* Interrupt Mask Register */
|
||||
#define GMAC_IMR_
|
||||
/* PHY Maintenance Register */
|
||||
#define GMAC_MAN_
|
||||
/* Received Pause Quantum Register */
|
||||
#define GMAC_RPQ_
|
||||
/* Transmit Pause Quantum Register */
|
||||
#define GMAC_TPQ_
|
||||
/* TX Partial Store and Forward Register */
|
||||
#define GMAC_TPSF_
|
||||
/* RX Partial Store and Forward Register */
|
||||
#define GMAC_RPSF_
|
||||
/* Hash Register Bottom [31:0] */
|
||||
#define GMAC_HRB_
|
||||
/* Hash Register Top [63:32] */
|
||||
#define GMAC_HRT_
|
||||
/* Specific Address 1 Bottom [31:0] Register */
|
||||
#define GMAC_SAB1_
|
||||
/* Specific Address 1 Top [47:32] Register */
|
||||
#define GMAC_SAT1_
|
||||
/* Specific Address 2 Bottom [31:0] Register */
|
||||
#define GMAC_SAB2_
|
||||
/* Specific Address 2 Top [47:32] Register */
|
||||
#define GMAC_SAT2_
|
||||
/* Specific Address 3 Bottom [31:0] Register */
|
||||
#define GMAC_SAB3_
|
||||
/* Specific Address 3 Top [47:32] Register */
|
||||
#define GMAC_SAT3_
|
||||
/* Specific Address 4 Bottom [31:0] Register */
|
||||
#define GMAC_SAB4_
|
||||
/* Specific Address 4 Top [47:32] Register */
|
||||
#define GMAC_SAT4_
|
||||
/* Type ID Match 1 Register */
|
||||
#define GMAC_TIDM1_
|
||||
/* Type ID Match 2 Register */
|
||||
#define GMAC_TIDM2_
|
||||
/* Type ID Match 3 Register */
|
||||
#define GMAC_TIDM3_
|
||||
/* Type ID Match 4 Register */
|
||||
#define GMAC_TIDM4_
|
||||
/* Wake on LAN Register */
|
||||
#define GMAC_WOL_
|
||||
/* IPG Stretch Register */
|
||||
#define GMAC_IPGS_
|
||||
/* Stacked VLAN Register */
|
||||
#define GMAC_SVLAN_
|
||||
/* Transmit PFC Pause Register */
|
||||
#define GMAC_TPFCP_
|
||||
/* Specific Address 1 Mask Bottom [31:0] Register */
|
||||
#define GMAC_SAMB1_
|
||||
/* Specific Address 1 Mask Top [47:32] Register */
|
||||
#define GMAC_SAMT1_
|
||||
/* Octets Transmitted [31:0] Register */
|
||||
#define GMAC_OTLO_
|
||||
/* Octets Transmitted [47:32] Register */
|
||||
#define GMAC_OTHI_
|
||||
/* Frames Transmitted Register */
|
||||
#define GMAC_FT_
|
||||
/* Broadcast Frames Transmitted Register */
|
||||
#define GMAC_BCFT_
|
||||
/* Multicast Frames Transmitted Register */
|
||||
#define GMAC_MFT_
|
||||
/* Pause Frames Transmitted Register */
|
||||
#define GMAC_PFT_
|
||||
/* 64 Byte Frames Transmitted Register */
|
||||
#define GMAC_BFT64_
|
||||
/* 65 to 127 Byte Frames Transmitted Register */
|
||||
#define GMAC_TBFT127_
|
||||
/* 128 to 255 Byte Frames Transmitted Register */
|
||||
#define GMAC_TBFT255_
|
||||
/* 256 to 511 Byte Frames Transmitted Register */
|
||||
#define GMAC_TBFT511_
|
||||
/* 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define GMAC_TBFT1023_
|
||||
/* 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define GMAC_TBFT1518_
|
||||
/* Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define GMAC_GTBFT1518_
|
||||
/* Transmit Under Runs Register */
|
||||
#define GMAC_TUR_
|
||||
/* Single Collision Frames Register */
|
||||
#define GMAC_SCF_
|
||||
/* Multiple Collision Frames Register */
|
||||
#define GMAC_MCF_
|
||||
/* Excessive Collisions Register */
|
||||
#define GMAC_EC_
|
||||
/* Late Collisions Register */
|
||||
#define GMAC_LC_
|
||||
/* Deferred Transmission Frames Register */
|
||||
#define GMAC_DTF_
|
||||
/* Carrier Sense Errors Register */
|
||||
#define GMAC_CSE_
|
||||
/* Octets Received [31:0] Received */
|
||||
#define GMAC_ORLO_
|
||||
/* Octets Received [47:32] Received */
|
||||
#define GMAC_ORHI_
|
||||
/* Frames Received Register */
|
||||
#define GMAC_FR_
|
||||
/* Broadcast Frames Received Register */
|
||||
#define GMAC_BCFR_
|
||||
/* Multicast Frames Received Register */
|
||||
#define GMAC_MFR_
|
||||
/* Pause Frames Received Register */
|
||||
#define GMAC_PFR_
|
||||
/* 64 Byte Frames Received Register */
|
||||
#define GMAC_BFR64_
|
||||
/* 65 to 127 Byte Frames Received Register */
|
||||
#define GMAC_TBFR127_
|
||||
/* 128 to 255 Byte Frames Received Register */
|
||||
#define GMAC_TBFR255_
|
||||
/* 256 to 511Byte Frames Received Register */
|
||||
#define GMAC_TBFR511_
|
||||
/* 512 to 1023 Byte Frames Received Register */
|
||||
#define GMAC_TBFR1023_
|
||||
/* 1024 to 1518 Byte Frames Received Register */
|
||||
#define GMAC_TBFR1518_
|
||||
/* 1519 to Maximum Byte Frames Received Register */
|
||||
#define GMAC_TMXBFR_
|
||||
/* Undersize Frames Received Register */
|
||||
#define GMAC_UFR_
|
||||
/* Oversize Frames Received Register */
|
||||
#define GMAC_OFR_
|
||||
/* Jabbers Received Register */
|
||||
#define GMAC_JR_
|
||||
/* Frame Check Sequence Errors Register */
|
||||
#define GMAC_FCSE_
|
||||
/* Length Field Frame Errors Register */
|
||||
#define GMAC_LFFE_
|
||||
/* Receive Symbol Errors Register */
|
||||
#define GMAC_RSE_
|
||||
/* Alignment Errors Register */
|
||||
#define GMAC_AE_
|
||||
/* Receive Resource Errors Register */
|
||||
#define GMAC_RRE_
|
||||
/* Receive Overrun Register */
|
||||
#define GMAC_ROE_
|
||||
/* IP Header Checksum Errors Register */
|
||||
#define GMAC_IHCE_
|
||||
/* TCP Checksum Errors Register */
|
||||
#define GMAC_TCE_
|
||||
/* UDP Checksum Errors Register */
|
||||
#define GMAC_UCE_
|
||||
/* 1588 Timer Sync Strobe Seconds Register */
|
||||
#define GMAC_TSSS_
|
||||
/* 1588 Timer Sync Strobe Nanoseconds Register */
|
||||
#define GMAC_TSSN_
|
||||
/* 1588 Timer Seconds Register */
|
||||
#define GMAC_TS_
|
||||
/* 1588 Timer Nanoseconds Register */
|
||||
#define GMAC_TN_
|
||||
/* 1588 Timer Adjust Register */
|
||||
#define GMAC_TA_
|
||||
/* 1588 Timer Increment Register */
|
||||
#define GMAC_TI_
|
||||
/* PTP Event Frame Transmitted Seconds */
|
||||
#define GMAC_EFTS_
|
||||
/* PTP Event Frame Transmitted Nanoseconds */
|
||||
#define GMAC_EFTN_
|
||||
/* PTP Event Frame Received Seconds */
|
||||
#define GMAC_EFRS_
|
||||
/* PTP Event Frame Received Nanoseconds */
|
||||
#define GMAC_EFRN_
|
||||
/* PTP Peer Event Frame Transmitted Seconds */
|
||||
#define GMAC_PEFTS_
|
||||
/* PTP Peer Event Frame Transmitted Nanoseconds */
|
||||
#define GMAC_PEFTN_
|
||||
/* PTP Peer Event Frame ReceiveGMAC_PEFRNd Seconds */
|
||||
#define GMAC_PEFRS_
|
||||
/* PTP Peer Event Frame Received Nanoseconds */
|
||||
#define GMAC_PEFRS_
|
||||
/* Interrupt Status Register Priority Queue 0-6 */
|
||||
#define GMAC_ISRPQ0_
|
||||
/* Transmit Buffer Queue Base Address Priority Queue 0-6 */
|
||||
#define GMAC_TBQBAPQ0_
|
||||
/* Receive Buffer Queue Base Address Priority Queue 0-6 */
|
||||
#define GMAC_RBQBAPQ0_
|
||||
/* Receive Buffer Size Register Priority Queue 0-6 */
|
||||
#define GMAC_RBSRPQ0_
|
||||
/* Screening Type1 Register Priority Queue 0-15 */
|
||||
#define GMAC_ST1RPQ0_
|
||||
/* Screening Type2 Register Priority Queue 0-15 */
|
||||
#define GMAC_ST2RPQ0_
|
||||
/* Interrupt Enable Register Priority Queue 0-6 */
|
||||
#define GMAC_IERPQ0_
|
||||
/* Interrupt Disable Register Priority Queue 0-6 */
|
||||
#define GMAC_IDRPQ0_
|
||||
/* Interrupt Mask Register Priority Queue 0-6 */
|
||||
#define GMAC_IMRPQ0_
|
||||
|
||||
(1 << nn) /* Bit nn:
|
||||
_SHIFT (nn) /* Bits nn-nn:
|
||||
_MASK (xx << yy)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H */
|
||||
|
||||
@ -891,6 +891,33 @@ Configurations
|
||||
|
||||
Configuration sub-directories
|
||||
-----------------------------
|
||||
Summary: Some of the descriptions below are long and wordy. Here is the
|
||||
concise summary of the available SAMA5D3x-EK configurations:
|
||||
|
||||
demo: This is an NSH configuration that supports as much functionality
|
||||
as possible. That is why it gets its name: It attempts to show as
|
||||
much as possible
|
||||
hello: The tiniest configuration possible (almost). It just says
|
||||
"Hello, World!" On the serial console. It is so tiny that it is
|
||||
able to run entirely out of internal SRAM (all of the other
|
||||
configurations except norboot use NOR FLASH for .text and internal
|
||||
SRAM for .data and .bass). This configuration is only useful for
|
||||
bring-up.
|
||||
norboot:
|
||||
This is a little program to help debug of code in NOR flash. I wrote
|
||||
it because I don't yet understand how to get the SAMA5 to boot from
|
||||
NOR FLASH. See the description below and the section above entitled
|
||||
"Creating and Using NORBOOT" for more information
|
||||
nsh: This is another NSH configuration, not too different from the
|
||||
demo configuration. The nsh configuration is, however, bare bones.
|
||||
It is the simplest possible NSH configuration and is useful as a
|
||||
platform for debugging and integrating new features in isolation.
|
||||
ostest: This is another configuration that is only useful for bring-up.
|
||||
It executes an exhaustive OS test to verify a correct port of NuttX
|
||||
to the SAMA5D3-EK. Since it now passes that test, the configuration
|
||||
has little further use other than for reference.
|
||||
|
||||
Now for the gory details:
|
||||
|
||||
demo:
|
||||
This configuration directory provide the NuttShell (NSH). There are
|
||||
|
||||
Loading…
Reference in New Issue
Block a user