arm64/a64: add driver for Allwinner A64 I2C bus
arm64/a64: add driver for Allwinner A64 I2C bus arm64/a64: add driver for Allwinner A64 I2C bus arm64/a64: add driver for Allwinner A64 I2C bus
This commit is contained in:
zouboan
Xiang Xiao
parent
1cee890aa7
commit
7e81dce71c
@ -166,5 +166,6 @@ PIO Yes
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PMIC (AXP803) Yes
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RSB Yes
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TCON0 Yes
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TWI Yes
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UART Yes Only UART0 is supported
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======================= ======= =====
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@ -41,6 +41,30 @@ config A64_UART
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---help---
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Select to enable support for UART.
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config A64_RTWI
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bool "Two-wire Master Controller R"
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default n
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---help---
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Select to enable support for R_TWI.
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config A64_TWI0
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bool "Two-wire Master Controller 0"
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default n
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---help---
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Select to enable support for TWI0.
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config A64_TWI1
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bool "Two-wire Master Controller 1"
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default n
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---help---
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Select to enable support for TWI1.
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config A64_TWI2
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bool "Two-wire Master Controller 2"
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default n
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---help---
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Select to enable support for TWI2.
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endmenu # Allwinner A64 Peripheral Selection
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endif # ARCH_CHIP_A64
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@ -21,7 +21,7 @@
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include common/Make.defs
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# Allwinner A64 specific C source files
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CHIP_CSRCS = a64_boot.c a64_pio.c a64_serial.c
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CHIP_CSRCS = a64_boot.c a64_pio.c a64_serial.c a64_twi.c
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ifeq ($(CONFIG_A64_DE),y)
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CHIP_CSRCS += a64_de.c
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73
arch/arm64/src/a64/a64_pinmux.h
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73
arch/arm64/src/a64/a64_pinmux.h
Normal file
@ -0,0 +1,73 @@
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/****************************************************************************
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* arch/arm64/src/a64/a64_pinmux.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_A64_A64_PINMUX_H
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#define __ARCH_ARM64_SRC_A64_A64_PINMUX_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/a64_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* I2Cs *********************************************************************/
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/* TWI0_SCK for PH0 */
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#define PIO_TWI0_SCK (PIO_PERIPH2 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOH | PIO_PIN0)
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/* TWI0_SDA for PH1 */
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#define PIO_TWI0_SDA (PIO_PERIPH2 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOH | PIO_PIN1)
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/* TWI1_SCK for PH2 */
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#define PIO_TWI1_SCK (PIO_PERIPH2 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOH | PIO_PIN2)
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/* TWI1_SDA for PH3 */
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#define PIO_TWI1_SDA (PIO_PERIPH2 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOH | PIO_PIN3)
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/* TWI2_SCK for PE14 */
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#define PIO_TWI2_SCK (PIO_PERIPH3 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOE | PIO_PIN14)
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/* TWI2_SDA for PE15 */
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#define PIO_TWI2_SDA (PIO_PERIPH3 | PIO_PULL_NONE | \
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PIO_DRIVE_MEDLOW | PIO_INT_NONE | \
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PIO_OUTPUT_CLEAR | PIO_PORT_PIOE | PIO_PIN15)
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#endif /* __ARCH_ARM64_SRC_A64_A64_PINMUX_H */
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1961
arch/arm64/src/a64/a64_twi.c
Normal file
1961
arch/arm64/src/a64/a64_twi.c
Normal file
File diff suppressed because it is too large
Load Diff
72
arch/arm64/src/a64/a64_twi.h
Normal file
72
arch/arm64/src/a64/a64_twi.h
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@ -0,0 +1,72 @@
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/****************************************************************************
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* arch/arm64/src/a64/a64_twi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A64_A64_TWI_H
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#define __ARCH_ARM_SRC_A64_A64_TWI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/i2c/i2c_master.h>
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#include "hardware/a64_twi.h"
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: a64_i2cbus_initialize
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*
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* Description:
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* Initialize the selected TWI port. And return a unique instance of struct
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* struct i2c_master_s. This function may be called to obtain multiple
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* instances of the interface, each of which may be set up with a
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* different frequency and slave address.
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*
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* Input Parameters:
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* Port number (for hardware that has multiple TWI interfaces)
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*
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* Returned Value:
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* Valid I2C device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct i2c_master_s *a64_i2cbus_initialize(int port);
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/****************************************************************************
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* Name: a64_i2cbus_uninitialize
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*
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* Description:
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* De-initialize the selected TWI port, and power down the device.
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*
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* Input Parameters:
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* Device structure as returned by the a64_i2cbus_initialize()
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*
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* Returned Value:
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* OK on success, ERROR when internal reference count mismatch or dev
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* points to invalid hardware device.
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*
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****************************************************************************/
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int a64_i2cbus_uninitialize(struct i2c_master_s *dev);
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#endif /* __ARCH_ARM_SRC_A64_A64_TWI_H */
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@ -39,8 +39,12 @@
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#define A64_CCU_ADDR 0x01c20000 /* CCU 0x01c2:0000-0x01c2:03ff 1K */
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#define A64_PIO_ADDR 0x01c20800 /* PIO 0x01c2:0800-0x01c2:0bff 1K */
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#define A64_PWM_ADDR 0x01c21400 /* PWM 0x01c2:1400-0x01c2:17ff 1K */
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#define A64_TWI0_ADDR 0x01c2ac00 /* TWI 0 0x01c2:ac00-0x01c2:afff 1K */
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#define A64_TWI1_ADDR 0x01c2b000 /* TWI 1 0x01c2:b000-0x01c2:B3ff 1K */
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#define A64_TWI2_ADDR 0x01c2b400 /* TWI 2 0x01c2:b400-0x01c2:b7ff 1K */
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#define A64_DSI_ADDR 0x01ca0000 /* MIPI DSI 0x01ca:0000-0x01ca:0fff 4K */
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#define A64_DPHY_ADDR 0x01ca1000 /* MIPI DSI-PHY 0x01ca:1000-0x01ca:1fff 4K */
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#define A64_RTWI_ADDR 0x01f02400 /* R_TWI 0x01f0:2400-0x01f0:27ff 1K */
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#define A64_RPIO_ADDR 0x01f02c00 /* R_PIO 0x01f0:2c00-0x01f0:2fff 1K */
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#define A64_RSB_ADDR 0x01f03400 /* R_RSB 0x01f0:3400-0x01f0:37ff 1K */
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#define A64_RPWM_ADDR 0x01f03800 /* R_PWM 0x01f0:3800-0x01f0-3bff 1K */
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203
arch/arm64/src/a64/hardware/a64_twi.h
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203
arch/arm64/src/a64/hardware/a64_twi.h
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@ -0,0 +1,203 @@
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/****************************************************************************
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* arch/arm64/src/a64/hardware/a64_twi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A64_HARDWARE_A64_TWI_H
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#define __ARCH_ARM_SRC_A64_HARDWARE_A64_TWI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "hardware/a64_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* TWI register offsets *****************************************************/
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#define A64_TWI_ADDR_OFFSET (0x00) /* 31:8 bit reserved,7-1 bit for slave addr,0 bit for GCE */
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#define A64_TWI_XADDR_OFFSET (0x04) /* 31:8 bit reserved,7-0 bit for second addr in 10bit addr */
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#define A64_TWI_DATA_OFFSET (0x08) /* 31:8 bit reserved,7-0 bit send or receive data byte */
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#define A64_TWI_CNTR_OFFSET (0x0c) /* 31:8 bit reserved, INT_EN, BUS_EN, M_STA, INT_FLAG, A_ACK */
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#define A64_TWI_STAT_OFFSET (0x10) /* 28 interrupt types + 0xF8 normal type = 29 */
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#define A64_TWI_CCR_OFFSET (0x14) /* 31:7 bit reserved,6-3bit,CLK_M,2-0bit CLK_N */
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#define A64_TWI_SRST_OFFSET (0x18) /* 31:1 bit reserved;0bit,write 1 to clear 0. */
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#define A64_TWI_EFR_OFFSET (0x1c) /* 31:2 bit reserved,1:0 bit data byte follow read comand */
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#define A64_TWI_LCR_OFFSET (0x20) /* 31:6 bits reserved 5:0 bit for sda&scl control*/
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#define A64_TWI_DVFS_OFFSET (0x24) /* 31:3 bits reserved 2:0 bit for dvfs control. only A10 support */
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/* TWI register addresses ***************************************************/
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#define A64_TWI0_SADDR (A64_TWI0_ADDR+A64_TWI_SADDR_OFFSET)
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#define A64_TWI0_XADDR (A64_TWI0_ADDR+A64_TWI_XADDR_OFFSET)
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#define A64_TWI0_DATA (A64_TWI0_ADDR+A64_TWI_DATA_OFFSET)
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#define A64_TWI0_CNTR (A64_TWI0_ADDR+A64_TWI_CNTR_OFFSET)
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#define A64_TWI0_STAT (A64_TWI0_ADDR+A64_TWI_STAT_OFFSET)
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#define A64_TWI0_CCR (A64_TWI0_ADDR+A64_TWI_CCR_OFFSET)
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#define A64_TWI0_SRST (A64_TWI0_ADDR+A64_TWI_SRST_OFFSET)
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#define A64_TWI0_EFR (A64_TWI0_ADDR+A64_TWI_EFR_OFFSET)
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#define A64_TWI0_LCR (A64_TWI0_ADDR+A64_TWI_LCR_OFFSET)
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#define A64_TWI1_SADDR (A64_TWI1_ADDR+A64_TWI_SADDR_OFFSET)
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#define A64_TWI1_XADDR (A64_TWI1_ADDR+A64_TWI_XADDR_OFFSET)
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#define A64_TWI1_DATA (A64_TWI1_ADDR+A64_TWI_DATA_OFFSET)
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#define A64_TWI1_CNTR (A64_TWI1_ADDR+A64_TWI_CNTR_OFFSET)
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#define A64_TWI1_STAT (A64_TWI1_ADDR+A64_TWI_STAT_OFFSET)
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#define A64_TWI1_CCR (A64_TWI1_ADDR+A64_TWI_CCR_OFFSET)
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#define A64_TWI1_SRST (A64_TWI1_ADDR+A64_TWI_SRST_OFFSET)
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#define A64_TWI1_EFR (A64_TWI1_ADDR+A64_TWI_EFR_OFFSET)
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#define A64_TWI1_LCR (A64_TWI1_ADDR+A64_TWI_LCR_OFFSET)
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#define A64_TWI2_SADDR (A64_TWI2_ADDR+A64_TWI_SADDR_OFFSET)
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#define A64_TWI2_XADDR (A64_TWI2_ADDR+A64_TWI_XADDR_OFFSET)
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#define A64_TWI2_DATA (A64_TWI2_ADDR+A64_TWI_DATA_OFFSET)
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#define A64_TWI2_CNTR (A64_TWI2_ADDR+A64_TWI_CNTR_OFFSET)
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#define A64_TWI2_STAT (A64_TWI2_ADDR+A64_TWI_STAT_OFFSET)
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#define A64_TWI2_CCR (A64_TWI2_ADDR+A64_TWI_CCR_OFFSET)
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#define A64_TWI2_SRST (A64_TWI2_ADDR+A64_TWI_SRST_OFFSET)
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#define A64_TWI2_EFR (A64_TWI2_ADDR+A64_TWI_EFR_OFFSET)
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#define A64_TWI2_LCR (A64_TWI2_ADDR+A64_TWI_LCR_OFFSET)
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#define A64_RTWI_SADDR (A64_RTWI_ADDR+A64_TWI_SADDR_OFFSET)
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#define A64_RTWI_XADDR (A64_RTWI_ADDR+A64_TWI_XADDR_OFFSET)
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#define A64_RTWI_DATA (A64_RTWI_ADDR+A64_TWI_DATA_OFFSET)
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#define A64_RTWI_CNTR (A64_RTWI_ADDR+A64_TWI_CNTR_OFFSET)
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#define A64_RTWI_STAT (A64_RTWI_ADDR+A64_TWI_STAT_OFFSET)
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#define A64_RTWI_CCR (A64_RTWI_ADDR+A64_TWI_CCR_OFFSET)
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#define A64_RTWI_SRST (A64_RTWI_ADDR+A64_TWI_SRST_OFFSET)
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#define A64_RTWI_EFR (A64_RTWI_ADDR+A64_TWI_EFR_OFFSET)
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#define A64_RTWI_LCR (A64_RTWI_ADDR+A64_TWI_LCR_OFFSET)
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/* TWI register bit definitions *********************************************/
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/* TWI address register */
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#define TWI_GCE_EN (0x1<<0) /* general call address enable for slave mode */
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#define TWI_ADDR_MASK (0x7f<<1) /* 7:1 bits */
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/* TWI extend address register */
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#define TWI_XADDR_MASK (0xff) /* 7:0 bits for extend slave address */
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/* TWI Data register default is 0x0000_0000 */
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#define TWI_DATA_MASK (0xff) /* 7:0 bits for send or received */
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/* TWI Control Register Bit Fields & Masks, default value: 0x0000_0000 */
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#define TWI_CNTR_ACK (0x1<<2) /* set 1 to send A_ACK */
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#define TWI_CNTR_INTFLG (0x1<<3) /* INT_FLAG,interrupt status flag */
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#define TWI_CNTR_STP (0x1<<4) /* M_STP,Automatic clear 0 */
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#define TWI_CNTR_STA (0x1<<5) /* M_STA,atutomatic clear 0 */
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#define TWI_CNTR_BUSEN (0x1<<6) /* BUS_EN, master mode should be set 1 */
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#define TWI_CNTR_INTEN (0x1<<7) /* INT_EN */
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/* TWI Clock Register Bit Fields & Masks,default value:0x0000_0000 */
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#define TWI_CLK_DIV_M (0xf<<3) /* 6:3 bit */
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#define TWI_CLK_DIV_N (0x7<<0) /* 2:0 bit */
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/* TWI Soft Reset Register Bit Fields & Masks */
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#define TWI_SRST_SRST (0x1<<0) /* write 1 to clear 0, when complete soft reset clear 0 */
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/* TWI Enhance Feature Register Bit Fields & Masks */
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#define TWI_EFR_MASK (0x3<<0) /* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */
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#define TWI_EFR_WARC_0 (0x0<<0)
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#define TWI_EFR_WARC_1 (0x1<<0)
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#define TWI_EFR_WARC_2 (0x2<<0)
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#define TWI_EFR_WARC_3 (0x3<<0)
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/* twi line control register -default value: 0x0000_003a */
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#define TWI_LCR_SDA_EN (0x01<<0) /* SDA line state control enable ,1:enable;0:disable */
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#define TWI_LCR_SDA_CTL (0x01<<1) /* SDA line state control bit, 1:high level;0:low level */
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#define TWI_LCR_SCL_EN (0x01<<2) /* SCL line state control enable ,1:enable;0:disable */
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#define TWI_LCR_SCL_CTL (0x01<<3) /* SCL line state control bit, 1:high level;0:low level */
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#define TWI_LCR_SDA_STATE_MASK (0x01<<4) /* current state of SDA,readonly bit */
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#define TWI_LCR_SCL_STATE_MASK (0x01<<5) /* current state of SCL,readonly bit */
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/* 31:6bits reserved */
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#define TWI_LCR_MASK (0x3f)
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#define TWI_LCR_IDLE_STATUS (0x3a)
|
||||
|
||||
/* TWI Status Register Bit Fields & Masks */
|
||||
|
||||
#define TWI_STAT_MASK (0xff)
|
||||
|
||||
/* 7:0 bits use only,default is 0xF8 */
|
||||
|
||||
#define TWI_STAT_BUS_ERR (0x00) /* BUS ERROR */
|
||||
|
||||
/* Master mode use only */
|
||||
|
||||
#define TWI_STAT_TX_STA (0x08) /* START condition transmitted */
|
||||
#define TWI_STAT_TX_RESTA (0x10) /* Repeated START condition transmitted */
|
||||
#define TWI_STAT_TX_AW_ACK (0x18) /* Address+Write bit transmitted, ACK received */
|
||||
#define TWI_STAT_TX_AW_NAK (0x20) /* Address+Write bit transmitted, ACK not received */
|
||||
#define TWI_STAT_TXD_ACK (0x28) /* data byte transmitted in master mode,ack received */
|
||||
#define TWI_STAT_TXD_NAK (0x30) /* data byte transmitted in master mode ,ack not received */
|
||||
#define TWI_STAT_ARBLOST (0x38) /* arbitration lost in address or data byte */
|
||||
#define TWI_STAT_TX_AR_ACK (0x40) /* Address+Read bit transmitted, ACK received */
|
||||
#define TWI_STAT_TX_AR_NAK (0x48) /* Address+Read bit transmitted, ACK not received */
|
||||
#define TWI_STAT_RXD_ACK (0x50) /* data byte received in master mode ,ack transmitted */
|
||||
#define TWI_STAT_RXD_NAK (0x58) /* date byte received in master mode,not ack transmitted */
|
||||
|
||||
/* Slave mode use only */
|
||||
|
||||
#define TWI_STAT_RXWS_ACK (0x60) /* Slave address+Write bit received, ACK transmitted */
|
||||
#define TWI_STAT_ARBLOST_RXWS_ACK (0x68)
|
||||
#define TWI_STAT_RXGCAS_ACK (0x70) /* General Call address received, ACK transmitted */
|
||||
#define TWI_STAT_ARBLOST_RXGCAS_ACK (0x78)
|
||||
#define TWI_STAT_RXDS_ACK (0x80)
|
||||
#define TWI_STAT_RXDS_NAK (0x88)
|
||||
#define TWI_STAT_RXDGCAS_ACK (0x90)
|
||||
#define TWI_STAT_RXDGCAS_NAK (0x98)
|
||||
#define TWI_STAT_RXSTPS_RXRESTAS (0xa0)
|
||||
#define TWI_STAT_RXRS_ACK (0xa8)
|
||||
|
||||
#define TWI_STAT_ARBLOST_SLAR_ACK (0xb0)
|
||||
|
||||
/* 10bit Address, second part of address */
|
||||
|
||||
#define TWI_STAT_TX_SAW_ACK (0xd0) /* Second Address byte+Write bit transmitted,ACK received */
|
||||
#define TWI_STAT_TX_SAW_NAK (0xd8) /* Second Address byte+Write bit transmitted,ACK not received */
|
||||
|
||||
#define TWI_STAT_IDLE (0xf8) /* No relevant status infomation,INT_FLAG = 0 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_A64_HARDWARE_A64_TWI_H */
|
||||
Loading…
Reference in New Issue
Block a user