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STM32F746G-DISCO: Getting closer to a build

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This commit is contained in:
Gregory Nutt 2015-07-17 11:47:16 -06:00
parent 7f7082f938
commit 7eb5e7f9ec
8 changed files with 246 additions and 161 deletions
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3
arch/arm/Kconfig
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@ -210,7 +210,8 @@ config ARCH_CHIP_STM32F7
select ARMV7M_CMNVECTOR select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
STMicro STM32 architectures (ARM Cortex-M7). STMicro STM32 architectures (ARM Cortex-M7).

1
arch/arm/include/stm32f7/chip.h
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@ -99,7 +99,6 @@
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ # define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#endif #endif
#endif
# define STM32F7_SRAM1 (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ # define STM32F7_SRAM1 (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2 (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # define STM32F7_SRAM2 (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */

7
arch/arm/include/stm32f7/irq.h
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@ -45,8 +45,6 @@
************************************************************************************/ ************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32/chip.h>
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@ -76,11 +74,10 @@
/* External interrupts (vectors >= 16). These definitions are chip-specific */ /* External interrupts (vectors >= 16). These definitions are chip-specific */
#define STM32_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include <arch/stm32/stm32f74xx75xx_irq.h> # include <arch/stm32f7/stm32f74xx75xx_irq.h>
#elif
#else #else
# error "Unsupported STM32 F7 chip" # error "Unsupported STM32 F7 chip"
#endif #endif

289
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
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@ -1,5 +1,5 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32s/stm32f74xx75xx_irq.h.h * arch/arm/include/stm32f7/stm32f74xx75xx_irq.h.h
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,9 +33,7 @@
* *
****************************************************************************************************/ ****************************************************************************************************/
/* This file should never be included directed but, rather, /* This file should never be included directed but, rather, only indirectly through arch/irq.h */
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H #ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H #define __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
@ -45,7 +43,6 @@
****************************************************************************************************/ ****************************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/irq.h>
/**************************************************************************************************** /****************************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@ -60,119 +57,179 @@
* External interrupts (vectors >= 16) * External interrupts (vectors >= 16)
*/ */
#define STM32_IRQ_WWDG (STM32_IRQ_INTERRUPTS+0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_INTERRUPTS+1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_INTERRUPTS+2) /* 2: Tamper and time stamp interrupts */ #define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_INTERRUPTS+2) /* 2: Tamper and time stamp interrupts */ #define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_INTERRUPTS+3) /* 3: RTC global interrupt */ #define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_INTERRUPTS+4) /* 4: Flash global interrupt */ #define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_INTERRUPTS+5) /* 5: RCC global interrupt */ #define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_INTERRUPTS+6) /* 6: EXTI Line 0 interrupt */ #define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_INTERRUPTS+7) /* 7: EXTI Line 1 interrupt */ #define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_INTERRUPTS+8) /* 8: EXTI Line 2 interrupt */ #define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_INTERRUPTS+9) /* 9: EXTI Line 3 interrupt */ #define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_INTERRUPTS+10) /* 10: EXTI Line 4 interrupt */ #define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_INTERRUPTS+11) /* 11: DMA1 Stream 0 global interrupt */ #define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_INTERRUPTS+12) /* 12: DMA1 Stream 1 global interrupt */ #define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_INTERRUPTS+13) /* 13: DMA1 Stream 2 global interrupt */ #define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_INTERRUPTS+14) /* 14: DMA1 Stream 3 global interrupt */ #define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_INTERRUPTS+15) /* 15: DMA1 Stream 4 global interrupt */ #define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_INTERRUPTS+16) /* 16: DMA1 Stream 5 global interrupt */ #define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_INTERRUPTS+17) /* 17: DMA1 Stream 6 global interrupt */ #define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_INTERRUPTS+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ #define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_INTERRUPTS+19) /* 19: CAN1 TX interrupts */ #define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_INTERRUPTS+20) /* 20: CAN1 RX0 interrupts */ #define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_INTERRUPTS+21) /* 21: CAN1 RX1 interrupt */ #define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_INTERRUPTS+22) /* 22: CAN1 SCE interrupt */ #define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_INTERRUPTS+23) /* 23: EXTI Line[9:5] interrupts */ #define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_INTERRUPTS+24) /* 24: TIM1 Break interrupt */ #define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_INTERRUPTS+24) /* 24: TIM9 global interrupt */ #define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_INTERRUPTS+25) /* 25: TIM1 Update interrupt */ #define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_INTERRUPTS+25) /* 25: TIM10 global interrupt */ #define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_INTERRUPTS+26) /* 26: TIM1 Trigger and Commutation interrupts */ #define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_INTERRUPTS+26) /* 26: TIM11 global interrupt */ #define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_INTERRUPTS+27) /* 27: TIM1 Capture Compare interrupt */ #define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_INTERRUPTS+28) /* 28: TIM2 global interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_INTERRUPTS+29) /* 29: TIM3 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_INTERRUPTS+30) /* 30: TIM4 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_INTERRUPTS+31) /* 31: I2C1 event interrupt */ #define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_INTERRUPTS+32) /* 32: I2C1 error interrupt */ #define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_INTERRUPTS+33) /* 33: I2C2 event interrupt */ #define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_INTERRUPTS+34) /* 34: I2C2 error interrupt */ #define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_INTERRUPTS+35) /* 35: SPI1 global interrupt */ #define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_INTERRUPTS+36) /* 36: SPI2 global interrupt */ #define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_INTERRUPTS+37) /* 37: USART1 global interrupt */ #define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_INTERRUPTS+38) /* 38: USART2 global interrupt */ #define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_INTERRUPTS+39) /* 39: USART3 global interrupt */ #define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_INTERRUPTS+40) /* 40: EXTI Line[15:10] interrupts */ #define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_INTERRUPTS+41) /* 41: RTC alarm through EXTI line interrupt */ #define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_INTERRUPTS+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ #define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_INTERRUPTS+43) /* 43: TIM8 Break interrupt */ #define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_INTERRUPTS+43) /* 43: TIM12 global interrupt */ #define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_INTERRUPTS+44) /* 44: TIM8 Update interrupt */ #define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_INTERRUPTS+44) /* 44: TIM13 global interrupt */ #define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_INTERRUPTS+45) /* 45: TIM8 Trigger and Commutation interrupts */ #define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_INTERRUPTS+45) /* 45: TIM14 global interrupt */ #define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_INTERRUPTS+46) /* 46: TIM8 Capture Compare interrupt */ #define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_INTERRUPTS+47) /* 47: DMA1 Stream 7 global interrupt */ #define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_INTERRUPTS+48) /* 48: FSMC global interrupt */ #define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_INTERRUPTS+49) /* 49: SDMMC1 global interrupt */ #define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_INTERRUPTS+50) /* 50: TIM5 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_INTERRUPTS+51) /* 51: SPI3 global interrupt */ #define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_INTERRUPTS+52) /* 52: UART4 global interrupt */ #define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_INTERRUPTS+53) /* 53: UART5 global interrupt */ #define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_INTERRUPTS+54) /* 54: TIM6 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_INTERRUPTS+54) /* 54: DAC1 and DAC2 underrun error interrupts */ #define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_INTERRUPTS+55) /* 55: TIM7 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_INTERRUPTS+56) /* 56: DMA2 Stream 0 global interrupt */ #define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_INTERRUPTS+57) /* 57: DMA2 Stream 1 global interrupt */ #define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_INTERRUPTS+58) /* 58: DMA2 Stream 2 global interrupt */ #define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_INTERRUPTS+59) /* 59: DMA2 Stream 3 global interrupt */ #define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_INTERRUPTS+60) /* 60: DMA2 Stream 4 global interrupt */ #define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_INTERRUPTS+61) /* 61: Ethernet global interrupt */ #define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_INTERRUPTS+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ #define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_INTERRUPTS+63) /* 63: CAN2 TX interrupts */ #define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_INTERRUPTS+64) /* 64: CAN2 RX0 interrupts */ #define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_INTERRUPTS+65) /* 65: CAN2 RX1 interrupt */ #define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_INTERRUPTS+66) /* 66: CAN2 SCE interrupt */ #define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_INTERRUPTS+67) /* 67: USB On The Go FS global interrupt */ #define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_INTERRUPTS+68) /* 68: DMA2 Stream 5 global interrupt */ #define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_INTERRUPTS+69) /* 69: DMA2 Stream 6 global interrupt */ #define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_INTERRUPTS+70) /* 70: DMA2 Stream 7 global interrupt */ #define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_INTERRUPTS+71) /* 71: USART6 global interrupt */ #define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_INTERRUPTS+72) /* 72: I2C3 event interrupt */ #define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_INTERRUPTS+73) /* 73: I2C3 error interrupt */ #define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_INTERRUPTS+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ #define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_INTERRUPTS+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ #define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_INTERRUPTS+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ #define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_INTERRUPTS+77) /* 77: USB On The Go HS global interrupt */ #define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_INTERRUPTS+78) /* 78: DCMI global interrupt */ #define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_INTERRUPTS+79) /* 79: CRYP crypto global interrupt */ #define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_INTERRUPTS+80) /* 80: Hash and Rng global interrupt */ #define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_INTERRUPTS+80) /* 80: Hash and Rng global interrupt */ #define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_INTERRUPTS+82) /* 82: UART7 global interrupt */ #define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_INTERRUPTS+83) /* 83: UART8 global interrupt */ #define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_INTERRUPTS+84) /* 84: SPI4 global interrupt */ #define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_INTERRUPTS+85) /* 85: SPI5 global interrupt */ #define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_INTERRUPTS+86) /* 86: SPI6 global interrupt */ #define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_INTERRUPTS+87) /* 87: SAI1 global interrupt */ #define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_INTERRUPTS+88) /* 88: LCD-TFT global interrupt */ #define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_INTERRUPTS+89) /* 89: LCD-TFT global Error interrupt */ #define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_INTERRUPTS+90) /* 90: DMA2D global interrupt */ #define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_INTERRUPTS+91) /* 91: SAI2 global interrupt */ #define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_INTERRUPTS+92) /* 92: QuadSPI global interrupt */ #define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_INTERRUPTS+93) /* 93: LP Timer1 global interrupt */ #define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_INTERRUPTS+94) /* 94: HDMI-CEC global interrupt */ #define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_INTERRUPTS+95) /* 95: I2C4 event interrupt */ #define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_INTERRUPTS+96) /* 96: I2C4 Error interrupt */ #define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_INTERRUPTS+97) /* 97: SPDIFRX global interrupt */ #define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
#define STM32_IRQ_NEXTINT 98 #define NR_INTERRUPTS 98
#define STM32_NR_IRQS (STM32_IRQ_INTERRUPTS+STM32_IRQ_NEXTINT) #define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define NR_VECTORS (STM32_IRQ_INTERRUPTS+STM32_IRQ_NEXTINT) /* EXTI events */
#define NR_IRQS (STM32_IRQ_INTERRUPTS+STM32_IRQ_NEXTINT)
#define STM32_EVENT_PIN0 0 /* Port n, pin 0 */
#define STM32_EVENT_PIN1 1 /* Port n, pin 1 */
#define STM32_EVENT_PIN2 2 /* Port n, pin 2 */
#define STM32_EVENT_PIN3 3 /* Port n, pin 3 */
#define STM32_EVENT_PIN4 4 /* Port n, pin 4 */
#define STM32_EVENT_PIN5 5 /* Port n, pin 5 */
#define STM32_EVENT_PIN6 6 /* Port n, pin 6 */
#define STM32_EVENT_PIN7 7 /* Port n, pin 7 */
#define STM32_EVENT_PIN8 8 /* Port n, pin 8 */
#define STM32_EVENT_PIN9 9 /* Port n, pin 9 */
#define STM32_EVENT_PIN10 10 /* Port n, pin 10 */
#define STM32_EVENT_PIN11 11 /* Port n, pin 11 */
#define STM32_EVENT_PIN12 12 /* Port n, pin 12 */
#define STM32_EVENT_PIN13 13 /* Port n, pin 13 */
#define STM32_EVENT_PIN14 14 /* Port n, pin 14 */
#define STM32_EVENT_PIN15 15 /* Port n, pin 15 */
#define STM32_EVENT_PVD 16 /* PVD output */
#define STM32_EVENT_RTCALM 17 /* RTC Alarm event */
#define STM32_EVENT_OTGFSWU 18 /* USB OTG FS Wakeup event */
#define STM32_EVENT_ETHWU 19 /* Ethernet Wakeup event */
#define STM32_EVENT_OTGHSWU 20 /* USB OTG HS (FS mode) Wakeup event */
#define STM32_EVENT_TAMPER 21 /* RTC Tamper and TimeStamp events */
#define STM32_EVENT_TIMESTAP 21 /* RTC Tamper and TimeStamp events */
#define STM32_EVENT_RTCWU 22 /* RTC Wakeup event */
#define STM32_EVENT_LPTIM1 23 /* LPTIM1 asynchronous event */
#define NR_EVENTS 24
/* EXTI interrupts */
#define STM32_IRQ_EXTI NR_VECTORS
#define STM32_IRQ_PIN0 (STM32_IRQ_EXTI+0) /* 98: Port n, pin 0 */
#define STM32_IRQ_PIN1 (STM32_IRQ_EXTI+1) /* 99: Port n, pin 1 */
#define STM32_IRQ_PIN2 (STM32_IRQ_EXTI+2) /* 100: Port n, pin 2 */
#define STM32_IRQ_PIN3 (STM32_IRQ_EXTI+3) /* 101: Port n, pin 3 */
#define STM32_IRQ_PIN4 (STM32_IRQ_EXTI+4) /* 102: Port n, pin 4 */
#define STM32_IRQ_PIN5 (STM32_IRQ_EXTI+5) /* 103: Port n, pin 5 */
#define STM32_IRQ_PIN6 (STM32_IRQ_EXTI+6) /* 104: Port n, pin 6 */
#define STM32_IRQ_PIN7 (STM32_IRQ_EXTI+7) /* 105: Port n, pin 7 */
#define STM32_IRQ_PIN8 (STM32_IRQ_EXTI+8) /* 106: Port n, pin 8 */
#define STM32_IRQ_PIN9 (STM32_IRQ_EXTI+9) /* 107: Port n, pin 9 */
#define STM32_IRQ_PIN10 (STM32_IRQ_EXTI+10) /* 108: Port n, pin 10 */
#define STM32_IRQ_PIN11 (STM32_IRQ_EXTI+11) /* 109: Port n, pin 11 */
#define STM32_IRQ_PIN12 (STM32_IRQ_EXTI+12) /* 110: Port n, pin 12 */
#define STM32_IRQ_PIN13 (STM32_IRQ_EXTI+13) /* 111: Port n, pin 13 */
#define STM32_IRQ_PIN14 (STM32_IRQ_EXTI+14) /* 112: Port n, pin 14 */
#define STM32_IRQ_PIN15 (STM32_IRQ_EXTI+15) /* 113: Port n, pin 15 */
#define STM32_IRQ_PVD (STM32_IRQ_EXTI+16) /* 114: PVD output */
#define STM32_IRQ_RTCALM (STM32_IRQ_EXTI+17) /* 115: RTC Alarm event */
#define STM32_IRQ_OTGFSWU (STM32_IRQ_EXTI+18) /* 116: USB OTG FS Wakeup event */
#define STM32_IRQ_ETHWU (STM32_IRQ_EXTI+19) /* 117: Ethernet Wakeup event */
#define STM32_IRQ_OTGHSWU (STM32_IRQ_EXTI+20) /* 118: USB OTG HS (FS mode) Wakeup event */
#define STM32_IRQ_TAMPER (STM32_IRQ_EXTI+21) /* 119: RTC Tamper and TimeStamp events */
#define STM32_IRQ_TIMESTAP (STM32_IRQ_EXTI+21) /* 119: RTC Tamper and TimeStamp events */
#define STM32_IRQ_RTCWU (STM32_IRQ_EXTI+22) /* 120: RTC Wakeup event */
#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTI+23) /* 121: LPTIM1 asynchronous event */
#define NR_IRQS (NR_VECTORS+NR_EVENTS)
/**************************************************************************************************** /****************************************************************************************************
* Public Types * Public Types

20
arch/arm/src/stm32/stm32_irq.c
View File

@ -234,22 +234,22 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
/* Check for external interrupt */ /* Check for external interrupt */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
if (irq < STM32_IRQ_INTERRUPTS + 32) if (irq < STM32_IRQ_FIRST + 32)
{ {
*regaddr = (NVIC_IRQ0_31_ENABLE + offset); *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_INTERRUPTS); *bit = 1 << (irq - STM32_IRQ_FIRST);
} }
else if (irq < STM32_IRQ_INTERRUPTS + 64) else if (irq < STM32_IRQ_FIRST + 64)
{ {
*regaddr = (NVIC_IRQ32_63_ENABLE + offset); *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_INTERRUPTS - 32); *bit = 1 << (irq - STM32_IRQ_FIRST - 32);
} }
else if (irq < NR_IRQS) else if (irq < NR_IRQS)
{ {
*regaddr = (NVIC_IRQ64_95_ENABLE + offset); *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - STM32_IRQ_INTERRUPTS - 64); *bit = 1 << (irq - STM32_IRQ_FIRST - 64);
} }
else else
{ {
@ -434,7 +434,7 @@ void up_disable_irq(int irq)
* clear the bit in the System Handler Control and State Register. * clear the bit in the System Handler Control and State Register.
*/ */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
putreg32(bit, regaddr); putreg32(bit, regaddr);
} }
@ -471,7 +471,7 @@ void up_enable_irq(int irq)
* set the bit in the System Handler Control and State Register. * set the bit in the System Handler Control and State Register.
*/ */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
putreg32(bit, regaddr); putreg32(bit, regaddr);
} }
@ -519,7 +519,7 @@ int up_prioritize_irq(int irq, int priority)
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < STM32_IRQ_INTERRUPTS) if (irq < STM32_IRQ_FIRST)
{ {
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid) * registers (0-3 are invalid)
@ -532,7 +532,7 @@ int up_prioritize_irq(int irq, int priority)
{ {
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= STM32_IRQ_INTERRUPTS; irq -= STM32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq); regaddr = NVIC_IRQ_PRIORITY(irq);
} }

2
arch/arm/src/stm32f7/chip.h
View File

@ -56,7 +56,7 @@
* header file. * header file.
*/ */
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32F7_IRQ_NEXTINT #define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
/* Cache line sizes (in bytes)for the STM32F7 */ /* Cache line sizes (in bytes)for the STM32F7 */

17
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
View File

@ -46,19 +46,16 @@
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */ #define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ #define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ # define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ # define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */ #define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ # define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ # define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */
#define STM32_AHB3_BASE 0xa0000000 /* 0xa0000000-0xa0001fff: 512Mb AHB3 peripheral block */ #define STM32_AHB3_BASE 0xa0000000 /* 0xa0000000-0xa0001fff: 256Mb AHB3 peripheral block */
#define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 512Mb FSMC */ #define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */
#define STM32_FSMC_BASE6 0xc0000000 /* 0xd0000000-0xdfffffff: 512Mb FSMC */ #define STM32_FSMC_BASE6 0xc0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ #define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: 512Mb AHB3 peripheral block */
#define STM32_REGION_MASK 0xf0000000 #define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) #define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) #define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)

68
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -44,7 +44,9 @@
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <arch/irq.h> #include <arch/irq.h>
#include <arch/stm32f7/chip.h>
#include "nvic.h" #include "nvic.h"
#include "ram_vectors.h" #include "ram_vectors.h"
@ -120,27 +122,37 @@ static void stm32_dumpnvic(const char *msg, int irq)
lldbg(" IRQ PRIO: %08x %08x %08x %08x\n", lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if STM32_IRQ_NEXTINT > 15 #if NR_INTERRUPTS > 15
lldbg(" %08x %08x %08x %08x\n", lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif #endif
#if STM32_IRQ_NEXTINT > 31 #if NR_INTERRUPTS > 31
lldbg(" %08x %08x %08x %08x\n", lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif #endif
#if STM32_IRQ_NEXTINT > 47 #if NR_INTERRUPTS > 47
lldbg(" %08x %08x %08x %08x\n", lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif #endif
#if STM32_IRQ_NEXTINT > 63 #if NR_INTERRUPTS > 63
lldbg(" %08x %08x %08x %08x\n", lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY), getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY)); getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif #endif
#if STM32_IRQ_NEXTINT > 79 #if NR_INTERRUPTS > 79
lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
# warning Missing logic # warning Missing logic
#endif #endif
irqrestore(flags); irqrestore(flags);
@ -245,34 +257,34 @@ static inline void stm32_prioritize_syscall(int priority)
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset) uintptr_t offset)
{ {
unsigned int extint = irq - STM32_IRQ_INTERRUPTS; unsigned int extint = irq - STM32_IRQ_FIRST;
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */ /* Check for external interrupt */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
#if STM32_IRQ_NEXTINT <= 32 #if NR_INTERRUPTS <= 32
if (extint < STM32_IRQ_NEXTINT) if (extint < NR_INTERRUPTS)
{ {
*regaddr = (NVIC_IRQ0_31_ENABLE + offset); *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint; *bit = 1 << extint;
} }
else else
#elif STM32_IRQ_NEXTINT <= 64 #elif NR_INTERRUPTS <= 64
if (extint < 32) if (extint < 32)
{ {
*regaddr = (NVIC_IRQ0_31_ENABLE + offset); *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint; *bit = 1 << extint;
} }
else if (extint < STM32_IRQ_NEXTINT) else if (extint < NR_INTERRUPTS)
{ {
*regaddr = (NVIC_IRQ32_63_ENABLE + offset); *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32); *bit = 1 << (extint - 32);
} }
else else
#elif STM32_IRQ_NEXTINT <= 96 #elif NR_INTERRUPTS <= 96
if (extint < 32) if (extint < 32)
{ {
*regaddr = (NVIC_IRQ0_31_ENABLE + offset); *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -283,12 +295,34 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ32_63_ENABLE + offset); *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32); *bit = 1 << (extint - 32);
} }
else if (extint < STM32_IRQ_NEXTINT) else if (extint < NR_INTERRUPTS)
{ {
*regaddr = (NVIC_IRQ64_95_ENABLE + offset); *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64); *bit = 1 << (extint - 64);
} }
else else
#elif NR_INTERRUPTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < NR_INTERRUPTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else
#else #else
# warning Missing logic # warning Missing logic
#endif #endif
@ -502,7 +536,7 @@ void up_disable_irq(int irq)
* clear the bit in the System Handler Control and State Register. * clear the bit in the System Handler Control and State Register.
*/ */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
putreg32(bit, regaddr); putreg32(bit, regaddr);
} }
@ -549,7 +583,7 @@ void up_enable_irq(int irq)
* set the bit in the System Handler Control and State Register. * set the bit in the System Handler Control and State Register.
*/ */
if (irq >= STM32_IRQ_INTERRUPTS) if (irq >= STM32_IRQ_FIRST)
{ {
putreg32(bit, regaddr); putreg32(bit, regaddr);
} }
@ -607,7 +641,7 @@ int up_prioritize_irq(int irq, int priority)
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < STM32_IRQ_NIRQS && DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < STM32_IRQ_NIRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < STM32_IRQ_INTERRUPTS) if (irq < STM32_IRQ_FIRST)
{ {
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid) * registers (0-3 are invalid)
@ -620,7 +654,7 @@ int up_prioritize_irq(int irq, int priority)
{ {
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= STM32_IRQ_INTERRUPTS; irq -= STM32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq); regaddr = NVIC_IRQ_PRIORITY(irq);
} }