From 7ecafdd6e41d9ae10abfb8d94a714126492a5d11 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 6 Jun 2012 01:44:57 +0000 Subject: [PATCH] Fix a bad interrupt state in the PIC32 IDLE loop when the work queue is enabled git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4805 42af7a65-404d-4744-a932-0658087f49c3 --- arch/mips/src/common/up_idle.c | 24 +++++++++++++++++++++--- arch/mips/src/mips32/up_initialstate.c | 2 +- arch/mips/src/mips32/up_irq.c | 2 +- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/mips/src/common/up_idle.c b/arch/mips/src/common/up_idle.c index 239aa3c308..4e2cc542be 100644 --- a/arch/mips/src/common/up_idle.c +++ b/arch/mips/src/common/up_idle.c @@ -1,8 +1,8 @@ /**************************************************************************** * arch/mips/src/common/up_idle.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -81,9 +81,27 @@ void up_idle(void) sched_process_timer(); #else - /* This would be an appropriate place to put some MCU-specific logig to + /* This would be an appropriate place to put some MCU-specific logic to * sleep in a reduced power mode until an interrupt occurs to save power */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = irqsave(); + irqrestore(flags); +#endif #endif } diff --git a/arch/mips/src/mips32/up_initialstate.c b/arch/mips/src/mips32/up_initialstate.c index cc0cd227e1..0c24d1ee03 100644 --- a/arch/mips/src/mips32/up_initialstate.c +++ b/arch/mips/src/mips32/up_initialstate.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_irq.c b/arch/mips/src/mips32/up_irq.c index 80ab7f78af..b13ae6294e 100644 --- a/arch/mips/src/mips32/up_irq.c +++ b/arch/mips/src/mips32/up_irq.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_irq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions