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SAMA5 GMAC: Various fixes from initial debug

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This commit is contained in:
Gregory Nutt 2013-09-29 15:03:57 -06:00
parent dc4c6bcb57
commit 7ee6ded1c2
5 changed files with 37 additions and 39 deletions
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24
arch/arm/src/sama5/chip/sam_gmac.h
View File

@ -525,7 +525,7 @@
#define GMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */ #define GMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */
#define GMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */ #define GMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */
#define GMAC_DCFGR_DRBS_MASK (0xff << GMAC_DCFGR_DRBS_SHIFT) #define GMAC_DCFGR_DRBS_MASK (0xff << GMAC_DCFGR_DRBS_SHIFT)
# define GMAC_DCFGR_DRBS(n) ((n) << GMAC_DCFGR_DRBS_SHIFT) # define GMAC_DCFGR_DRBS(n) ((uint32_t)(n) << GMAC_DCFGR_DRBS_SHIFT)
#define GMAC_DCFGR_DDRP (1 << 24) /* Bit 24: DMA Discard Receive Packets */ #define GMAC_DCFGR_DDRP (1 << 24) /* Bit 24: DMA Discard Receive Packets */
/* Transmit Status Register */ /* Transmit Status Register */
@ -618,14 +618,14 @@
#define GMAC_TPSF_TPB1ADR_SHIFT (0) /* Bits 0-11: Transmit Partial Store and Forward Address */ #define GMAC_TPSF_TPB1ADR_SHIFT (0) /* Bits 0-11: Transmit Partial Store and Forward Address */
#define GMAC_TPSF_TPB1ADR_MASK (0xfff << GMAC_TPSF_TPB1ADR_SHIFT) #define GMAC_TPSF_TPB1ADR_MASK (0xfff << GMAC_TPSF_TPB1ADR_SHIFT)
# define GMAC_TPSF_TPB1ADR(n) ((n) << GMAC_TPSF_TPB1ADR_SHIFT) # define GMAC_TPSF_TPB1ADR(n) ((uint32_t)(n) << GMAC_TPSF_TPB1ADR_SHIFT)
#define GMAC_TPSF_ENTXP (1 << 31) /* Bit 31: Enable TX Partial Store and Forward Operation */ #define GMAC_TPSF_ENTXP (1 << 31) /* Bit 31: Enable TX Partial Store and Forward Operation */
/* RX Partial Store and Forward Register */ /* RX Partial Store and Forward Register */
#define GMAC_RPSF_RPB1ADR_SHIFT (0) /* Bits 0-11: Receive Partial Store and Forward Address */ #define GMAC_RPSF_RPB1ADR_SHIFT (0) /* Bits 0-11: Receive Partial Store and Forward Address */
#define GMAC_RPSF_RPB1ADR_MASK (0xfff << GMAC_RPSF_RPB1ADR_SHIFT) #define GMAC_RPSF_RPB1ADR_MASK (0xfff << GMAC_RPSF_RPB1ADR_SHIFT)
# define GMAC_RPSF_RPB1ADR(n) ((n) << GMAC_RPSF_RPB1ADR_SHIFT) # define GMAC_RPSF_RPB1ADR(n) ((uint32_t)(n) << GMAC_RPSF_RPB1ADR_SHIFT)
#define GMAC_RPSF_ENRXP (1 << 31) /* Bit 31: Enable RX Partial Store and Forward Operation */ #define GMAC_RPSF_ENRXP (1 << 31) /* Bit 31: Enable RX Partial Store and Forward Operation */
/* Hash Register Bottom [31:0] (32-bit value) */ /* Hash Register Bottom [31:0] (32-bit value) */
@ -684,7 +684,7 @@
#define GMAC_SVLAN_VLANTYP_SHIFT (0) /* Bits 0-15: User Defined VLAN_TYPE Field */ #define GMAC_SVLAN_VLANTYP_SHIFT (0) /* Bits 0-15: User Defined VLAN_TYPE Field */
#define GMAC_SVLAN_VLANTYP_MASK (0xffff << GMAC_SVLAN_VLANTYP_SHIFT) #define GMAC_SVLAN_VLANTYP_MASK (0xffff << GMAC_SVLAN_VLANTYP_SHIFT)
# define GMAC_SVLAN_VLANTYP(n) ((n) << GMAC_SVLAN_VLANTYP_SHIFT) # define GMAC_SVLAN_VLANTYP(n) ((uint32_t)(n) << GMAC_SVLAN_VLANTYP_SHIFT)
#define GMAC_SVLAN_ESVLAN (1 << 31) /* Bit 31: Enable Stacked VLAN Processing Mode */ #define GMAC_SVLAN_ESVLAN (1 << 31) /* Bit 31: Enable Stacked VLAN Processing Mode */
/* Transmit PFC Pause Register */ /* Transmit PFC Pause Register */
@ -836,13 +836,13 @@
#define GMAC_TI_CNS_SHIFT (0) /* Bits 0-7: Count Nanoseconds */ #define GMAC_TI_CNS_SHIFT (0) /* Bits 0-7: Count Nanoseconds */
#define GMAC_TI_CNS_MASK (0xff << GMAC_TI_CNS_SHIFT) #define GMAC_TI_CNS_MASK (0xff << GMAC_TI_CNS_SHIFT)
# define GMAC_TI_CNS(n) ((n) << GMAC_TI_CNS_SHIFT) # define GMAC_TI_CNS(n) ((uint32_t)(n) << GMAC_TI_CNS_SHIFT)
#define GMAC_TI_ACNS_SHIFT (8) /* Bits 8-15: Alternative Count Nanoseconds */ #define GMAC_TI_ACNS_SHIFT (8) /* Bits 8-15: Alternative Count Nanoseconds */
#define GMAC_TI_ACNS_MASK (0xff << GMAC_TI_ACNS_SHIFT) #define GMAC_TI_ACNS_MASK (0xff << GMAC_TI_ACNS_SHIFT)
# define GMAC_TI_ACNS(n) ((n) << GMAC_TI_ACNS_SHIFT) # define GMAC_TI_ACNS(n) ((uint32_t)(n) << GMAC_TI_ACNS_SHIFT)
#define GMAC_TI_NIT_SHIFT (16) /* Bits 16-23: Number of Increments */ #define GMAC_TI_NIT_SHIFT (16) /* Bits 16-23: Number of Increments */
#define GMAC_TI_NIT_MASK (0xff << GMAC_TI_NIT_SHIFT) #define GMAC_TI_NIT_MASK (0xff << GMAC_TI_NIT_SHIFT)
# define GMAC_TI_NIT(n) ((n) << GMAC_TI_NIT_SHIFT) # define GMAC_TI_NIT(n) ((uint32_t)(n) << GMAC_TI_NIT_SHIFT)
/* PTP Event Frame Transmitted Seconds (32-bit value) */ /* PTP Event Frame Transmitted Seconds (32-bit value) */
/* PTP Event Frame Transmitted Nanoseconds */ /* PTP Event Frame Transmitted Nanoseconds */
@ -896,13 +896,13 @@
#define GMAC_ST1RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */ #define GMAC_ST1RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */
#define GMAC_ST1RPQ0_QNB_MASK (15 << GMAC_ST1RPQ0_QNB_SHIFT) #define GMAC_ST1RPQ0_QNB_MASK (15 << GMAC_ST1RPQ0_QNB_SHIFT)
# define GMAC_ST1RPQ0_QNB(n) ((n) << GMAC_ST1RPQ0_QNB_SHIFT) # define GMAC_ST1RPQ0_QNB(n) ((uint32_t)(n) << GMAC_ST1RPQ0_QNB_SHIFT)
#define GMAC_ST1RPQ0_DSTCM_SHIFT (4) /* Bits 4-11: Differentiated Services or Traffic Class Match */ #define GMAC_ST1RPQ0_DSTCM_SHIFT (4) /* Bits 4-11: Differentiated Services or Traffic Class Match */
#define GMAC_ST1RPQ0_DSTCM_MASK (0xff << GMAC_ST1RPQ0_DSTCM_SHIFT) #define GMAC_ST1RPQ0_DSTCM_MASK (0xff << GMAC_ST1RPQ0_DSTCM_SHIFT)
# define GMAC_ST1RPQ0_DSTCM(n) ((n) << GMAC_ST1RPQ0_DSTCM_SHIFT) # define GMAC_ST1RPQ0_DSTCM(n) ((uint32_t)(n) << GMAC_ST1RPQ0_DSTCM_SHIFT)
#define GMAC_ST1RPQ0_UDPM_SHIFT (12) /* Bits 12-27: UDP Port Match */ #define GMAC_ST1RPQ0_UDPM_SHIFT (12) /* Bits 12-27: UDP Port Match */
#define GMAC_ST1RPQ0_UDPM_MASK (0xffff << GMAC_ST1RPQ0_UDPM_SHIFT) #define GMAC_ST1RPQ0_UDPM_MASK (0xffff << GMAC_ST1RPQ0_UDPM_SHIFT)
# define GMAC_ST1RPQ0_UDPM(n) ((n) << GMAC_ST1RPQ0_UDPM_SHIFT) # define GMAC_ST1RPQ0_UDPM(n) ((uint32_t)(n) << GMAC_ST1RPQ0_UDPM_SHIFT)
#define GMAC_ST1RPQ0_DSTCE (1 << 28) /* Bit 28: Differentiated Services or Traffic Class Match Enable */ #define GMAC_ST1RPQ0_DSTCE (1 << 28) /* Bit 28: Differentiated Services or Traffic Class Match Enable */
#define GMAC_ST1RPQ0_UDPE (1 << 29) /* Bit 29: UDP Port Match Enable */ #define GMAC_ST1RPQ0_UDPE (1 << 29) /* Bit 29: UDP Port Match Enable */
@ -910,10 +910,10 @@
#define GMAC_ST2RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */ #define GMAC_ST2RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */
#define GMAC_ST2RPQ0_QNB_MASK (15 << GMAC_ST2RPQ0_QNB_SHIFT) #define GMAC_ST2RPQ0_QNB_MASK (15 << GMAC_ST2RPQ0_QNB_SHIFT)
# define GMAC_ST2RPQ0_QNB(n) ((n) << GMAC_ST2RPQ0_QNB_SHIFT) # define GMAC_ST2RPQ0_QNB(n) ((uint32_t)(n) << GMAC_ST2RPQ0_QNB_SHIFT)
#define GMAC_ST2RPQ0_VLANP_SHIFT (4) /* Bits 4-7: VLAN Priority */ #define GMAC_ST2RPQ0_VLANP_SHIFT (4) /* Bits 4-7: VLAN Priority */
#define GMAC_ST2RPQ0_VLANP_MASK (15 << GMAC_ST2RPQ0_VLANP_SHIFT) #define GMAC_ST2RPQ0_VLANP_MASK (15 << GMAC_ST2RPQ0_VLANP_SHIFT)
# define GMAC_ST2RPQ0_VLANP(n) ((n) << GMAC_ST2RPQ0_VLANP_SHIFT) # define GMAC_ST2RPQ0_VLANP(n) ((uint32_t)(n) << GMAC_ST2RPQ0_VLANP_SHIFT)
#define GMAC_ST2RPQ0_VLANE (1 << 8) /* Bit 8: VLAN Enable */ #define GMAC_ST2RPQ0_VLANE (1 << 8) /* Bit 8: VLAN Enable */
/* Descriptors **********************************************************************/ /* Descriptors **********************************************************************/

4
arch/arm/src/sama5/sam_emac.c
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@ -2036,7 +2036,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
/* Write the PHY Maintenance register */ /* Write the PHY Maintenance register */
regval = EMAC_MAN_DATA(0) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) | regval = EMAC_MAN_DATA(0) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) |
EMAC_MAN_PHYA(priv->phyaddr) | EMAC_MAN_READ | EMAC_MAN_SOF; EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_READ | EMAC_MAN_SOF;
sam_putreg(priv, SAM_EMAC_MAN, regval); sam_putreg(priv, SAM_EMAC_MAN, regval);
/* Wait until the PHY is again idle */ /* Wait until the PHY is again idle */
@ -2091,7 +2091,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
/* Write the PHY Maintenance register */ /* Write the PHY Maintenance register */
regval = EMAC_MAN_DATA(phyval) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) | regval = EMAC_MAN_DATA(phyval) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) |
EMAC_MAN_PHYA(priv->phyaddr) | EMAC_MAN_WRITE| EMAC_MAN_SOF; EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_WRITE| EMAC_MAN_SOF;
sam_putreg(priv, SAM_EMAC_MAN, regval); sam_putreg(priv, SAM_EMAC_MAN, regval);
/* Wait until the PHY is again IDLE */ /* Wait until the PHY is again IDLE */

30
arch/arm/src/sama5/sam_gmac.c
View File

@ -308,6 +308,8 @@ static void sam_phydump(struct sam_gmac_s *priv);
# define sam_phydump(priv) # define sam_phydump(priv)
#endif #endif
static void sam_enablemdio(struct sam_gmac_s *priv);
static void sam_disablemdio(struct sam_gmac_s *priv);
static int sam_phywait(struct sam_gmac_s *priv); static int sam_phywait(struct sam_gmac_s *priv);
static int sam_phyreset(struct sam_gmac_s *priv); static int sam_phyreset(struct sam_gmac_s *priv);
static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr); static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr);
@ -1532,7 +1534,6 @@ static int sam_ifup(struct uip_driver_s *dev)
/* Initialize for PHY access */ /* Initialize for PHY access */
sam_phyreset(priv);
ret = sam_phyinit(priv); ret = sam_phyinit(priv);
if (ret < 0) if (ret < 0)
{ {
@ -1746,7 +1747,6 @@ static int sam_rmmac(struct uip_driver_s *dev, const uint8_t *mac)
#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE) #if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
static void sam_phydump(struct sam_gmac_s *priv) static void sam_phydump(struct sam_gmac_s *priv)
{ {
uint32_t regval;
uint16_t phyval; uint16_t phyval;
/* Enable management port */ /* Enable management port */
@ -2048,7 +2048,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
/* Write the PHY Maintenance register */ /* Write the PHY Maintenance register */
regval = GMAC_MAN_DATA(0) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) | regval = GMAC_MAN_DATA(0) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) |
GMAC_MAN_PHYA(priv->phyaddr) | GMAC_MAN_READ | GMAC_MAN_CLTTO; GMAC_MAN_PHYA(phyaddr) | GMAC_MAN_READ | GMAC_MAN_CLTTO;
sam_putreg(priv, SAM_GMAC_MAN, regval); sam_putreg(priv, SAM_GMAC_MAN, regval);
/* Wait until the PHY is again idle */ /* Wait until the PHY is again idle */
@ -2103,7 +2103,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
/* Write the PHY Maintenance register */ /* Write the PHY Maintenance register */
regval = GMAC_MAN_DATA(phyval) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) | regval = GMAC_MAN_DATA(phyval) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) |
GMAC_MAN_PHYA(priv->phyaddr) | GMAC_MAN_WRITE | GMAC_MAN_CLTTO; GMAC_MAN_PHYA(phyaddr) | GMAC_MAN_WRITE | GMAC_MAN_CLTTO;
sam_putreg(priv, SAM_GMAC_MAN, regval); sam_putreg(priv, SAM_GMAC_MAN, regval);
/* Wait until the PHY is again IDLE */ /* Wait until the PHY is again IDLE */
@ -2298,7 +2298,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
for (;;) for (;;)
{ {
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr); ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr);
if (ret == 0) if (ret < 0)
{ {
nlldbg("ERROR: Failed to read 1000BTSR register: %d\n", ret); nlldbg("ERROR: Failed to read 1000BTSR register: %d\n", ret);
goto errout; goto errout;
@ -2326,7 +2326,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
/* Get the Autonegotiation Link partner base page */ /* Get the Autonegotiation Link partner base page */
ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa); ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
if (ret == 0) if (ret < 0)
{ {
nlldbg("ERROR: Failed to read LPA register: %d\n", ret); nlldbg("ERROR: Failed to read LPA register: %d\n", ret);
goto errout; goto errout;
@ -2480,17 +2480,17 @@ static void sam_mdcclock(struct sam_gmac_s *priv)
ncfgr &= ~GMAC_NCFGR_CLK_MASK; ncfgr &= ~GMAC_NCFGR_CLK_MASK;
#if BOARD_MCK_FREQUENCY <= 20000000 #if BOARD_MCK_FREQUENCY <= 20000000
ncfgr = GMAC_NCFGR_CLK_DIV8; /* MCK divided by 8 (MCK up to 20 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV8; /* MCK divided by 8 (MCK up to 20 MHz) */
#elif BOARD_MCK_FREQUENCY <= 40000000 #elif BOARD_MCK_FREQUENCY <= 40000000
ncfgr = GMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
#elif BOARD_MCK_FREQUENCY <= 80000000 #elif BOARD_MCK_FREQUENCY <= 80000000
ncfgr = GMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
#elif BOARD_MCK_FREQUENCY <= 120000000 #elif BOARD_MCK_FREQUENCY <= 120000000
ncfgr = GMAC_NCFGR_CLK_DIV48; /* MCK divided by 48 (MCK up to 120 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV48; /* MCK divided by 48 (MCK up to 120 MHz) */
#elif BOARD_MCK_FREQUENCY <= 160000000 #elif BOARD_MCK_FREQUENCY <= 160000000
ncfgr = GMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
#elif BOARD_MCK_FREQUENCY <= 240000000 #elif BOARD_MCK_FREQUENCY <= 240000000
ncfgr = GMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */ ncfgr |= GMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */
#else #else
# error Invalid BOARD_MCK_FREQUENCY # error Invalid BOARD_MCK_FREQUENCY
#endif #endif
@ -2534,11 +2534,9 @@ static int sam_phyinit(struct sam_gmac_s *priv)
return ret; return ret;
} }
if (priv->phyaddr != CONFIG_SAMA5_GMAC_PHYADDR) /* We have a PHY address. Reset the PHY */
{
sam_phyreset(priv);
}
sam_phyreset(priv);
return OK; return OK;
} }

6
include/nuttx/net/gmii.h
View File

@ -134,7 +134,7 @@
#define GMII_PHYID2_REV_MASK MII_PHYID2_REV_MASK #define GMII_PHYID2_REV_MASK MII_PHYID2_REV_MASK
#define GMII_PHYID2_REV(n) MII_PHYID2_REV(n) #define GMII_PHYID2_REV(n) MII_PHYID2_REV(n)
#define GMII_PHYID2_MODEL_SHIFT MII_PHYID2_MODEL_SHIFT #define GMII_PHYID2_MODEL_SHIFT MII_PHYID2_MODEL_SHIFT
#define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL #define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL_MASK
# define GMII_PHYID2_MODEL(n) MII_PHYID2_MODEL(n) # define GMII_PHYID2_MODEL(n) MII_PHYID2_MODEL(n)
#define GMII_PHYID2_OUI_SHIFT MII_PHYID2_OUI_SHIFT #define GMII_PHYID2_OUI_SHIFT MII_PHYID2_OUI_SHIFT
#define GMII_PHYID2_OUI_MASK MII_PHYID2_OUI_MASK #define GMII_PHYID2_OUI_MASK MII_PHYID2_OUI_MASK
@ -242,7 +242,7 @@
#define GMII_1000BTCR_TESTMODE_SHIFT (13) /* Bits 13-15: Test Mode */ #define GMII_1000BTCR_TESTMODE_SHIFT (13) /* Bits 13-15: Test Mode */
#define GMII_1000BTCR_TESTMODE_MASK (7 << GMII_1000BTCR_TESTMODE_SHIFT) #define GMII_1000BTCR_TESTMODE_MASK (7 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_MODE_NORMAL (0 << GMII_1000BTCR_TESTMODE_SHIFT) # define GMII_1000BTCR_MODE_NORMAL (0 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_TESTMODE(n) ((n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */ # define GMII_1000BTCR_TESTMODE(n) ((uint16_t)(n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */
/* 1000BASE-T Status Register */ /* 1000BASE-T Status Register */
@ -260,7 +260,7 @@
#define GMII_ERCR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */ #define GMII_ERCR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
#define GMII_ERCR_ADDR_MASK (0xff << GMII_ERCR_ADDR_SHIFT) #define GMII_ERCR_ADDR_MASK (0xff << GMII_ERCR_ADDR_SHIFT)
# define GMII_ERCR_ADDR(n) ((n) << GMII_ERCR_ADDR_SHIFT) # define GMII_ERCR_ADDR(n) ((uint16_t)(n) << GMII_ERCR_ADDR_SHIFT)
#define GMII_ERCR_PAGE (1 << 8) /* Bit 8: Select page for extended register */ #define GMII_ERCR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
/* Bits 9-14: Reserved */ /* Bits 9-14: Reserved */
#define GMII_ERCR_READ (0) /* Bit 15: 0=Read extended register */ #define GMII_ERCR_READ (0) /* Bit 15: 0=Read extended register */

12
include/nuttx/net/mii.h
View File

@ -204,13 +204,13 @@
#define MII_PHYID2_REV_SHIFT (0) /* Bits 0-3: Revision number mask */ #define MII_PHYID2_REV_SHIFT (0) /* Bits 0-3: Revision number mask */
#define MII_PHYID2_REV_MASK (15 << MII_PHYID2_REV_SHIFT) #define MII_PHYID2_REV_MASK (15 << MII_PHYID2_REV_SHIFT)
# define MII_PHYID2_REV(n) ((n) << MII_PHYID2_REV_SHIFT) # define MII_PHYID2_REV(n) ((uint16_t)(n) << MII_PHYID2_REV_SHIFT)
#define MII_PHYID2_MODEL_SHIFT (4) /* Bits 4-9: Model number mask */ #define MII_PHYID2_MODEL_SHIFT (4) /* Bits 4-9: Model number mask */
#define MII_PHYID2_MODEL_MASK (0x3f << MII_PHYID2_MODEL_SHIFT) #define MII_PHYID2_MODEL_MASK (0x3f << MII_PHYID2_MODEL_SHIFT)
# define MII_PHYID2_MODEL(n) ((n) << MII_PHYID2_MODEL_SHIFT) # define MII_PHYID2_MODEL(n) ((uint16_t)(n) << MII_PHYID2_MODEL_SHIFT)
#define MII_PHYID2_OUI_SHIFT (10) /* Bits 10-15: OUI mask [24:19] */ #define MII_PHYID2_OUI_SHIFT (10) /* Bits 10-15: OUI mask [24:19] */
#define MII_PHYID2_OUI_MASK (0x3f << MII_PHYID2_OUI_SHIFT) #define MII_PHYID2_OUI_MASK (0x3f << MII_PHYID2_OUI_SHIFT)
# define MII_PHYID2_OUI(n) ((n) << MII_PHYID2_OUI_SHIFT) # define MII_PHYID2_OUI(n) ((uint16_t)(n) << MII_PHYID2_OUI_SHIFT)
/* Advertisement control register bit definitions */ /* Advertisement control register bit definitions */
@ -285,9 +285,9 @@
/* MMD access control register */ /* MMD access control register */
#define MII_MMDCONTROL_DEVAD_SHIFT (0) /* Bits 0-4: Device address */ #define MII_MMDCONTROL_DEVAD_SHIFT (0) /* Bits 0-4: Device address */
#define MII_MMDCONTROL_DEVAD_MASK (31 << MII_MMDCONTROL_DEVAD_SHIFT) #define MII_MMDCONTROL_DEVAD_MASK (31 << MII_MMDCONTROL_DEVAD_SHIFT)
# define MII_MMDCONTROL_DEVAD(n) ((n) << MII_MMDCONTROL_DEVAD_SHIFT) # define MII_MMDCONTROL_DEVAD(n) ((uint16_t)(n) << MII_MMDCONTROL_DEVAD_SHIFT)
/* Bits 5-13: Reserved */ /* Bits 5-13: Reserved */
#define MII_MMDCONTROL_FUNC_SHIFT (14) /* Bits 14-15: Function */ #define MII_MMDCONTROL_FUNC_SHIFT (14) /* Bits 14-15: Function */
#define MII_MMDCONTROL_FUNC_MASK (3 << MII_MMDCONTROL_FUNC_SHIFT) #define MII_MMDCONTROL_FUNC_MASK (3 << MII_MMDCONTROL_FUNC_SHIFT)