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Add basic data transfer logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2264 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-11-17 16:24:44 +00:00
parent 2142afe747
commit 7ef8423ad0
4 changed files with 934 additions and 198 deletions
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85
arch/arm/src/stm32/stm32_sdio.c
View File

@ -141,7 +141,6 @@ struct stm32_dev_s
uint32 *buffer; /* Address of current R/W buffer */
size_t remaining; /* Number of bytes remaining in the transfer */
int result; /* Result of the transfer */
boolean stopxfr; /* TRUE: Send STOP_TRANSMISSION */
/* DMA data transfer support */
@ -181,7 +180,6 @@ static void stm32_dataconfig(uint32 timeout, uint32 dlen, uint32 dctrl);
static void stm32_datadisable(void);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
static int stm32_stoptransmission(struct stm32_dev_s *priv);
static void stm32_endtransfer(struct stm32_dev_s *priv, int result);
/* Interrupt Handling *******************************************************/
@ -237,7 +235,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
FAR ubyte *buffer, size_t buflen);
static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
FAR const ubyte *buffer, size_t buflen);
static int stm32_sdiodmastart(FAR struct sdio_dev_s *dev);
#endif
/* Initialization/uninitialization/reset ************************************/
@ -278,7 +275,6 @@ struct stm32_dev_s g_sdiodev =
.dmasupported = stm32_dmasupported,
.dmarecvsetup = stm32_dmarecvsetup,
.dmasendsetup = stm32_dmasendsetup,
.dmastart = stm32_sdiodmastart,
#endif
},
};
@ -469,7 +465,7 @@ static inline void stm32_clkdisable(void)
#ifdef CONFIG_SDIO_DMA
static void stm32_dmacallback(DMA_HANDLE handle, ubyte isr, void *arg)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
/* FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg; */
/* We don't really do anything at the completion of DMA. The termination
* of the transfer is driven by the SDIO interrupts.
@ -685,26 +681,6 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
}
}
/****************************************************************************
* Name: stm32_stoptransmission
*
* Description:
* Send STOP_TRANSMISSION
*
* Input Parameters:
* dev - An instance of the SDIO device interface
*
* Returned Value:
* OK on success; A negated errno on failure.
*
****************************************************************************/
static int stm32_stoptransmission(struct stm32_dev_s *priv)
{
# warning "Not implemented"
return -ENOSYS;
}
/****************************************************************************
* Name: stm32_endtransfer
*
@ -811,8 +787,6 @@ static int stm32_interrupt(int irq, void *context)
if ((sta & SDIO_STA_DATAEND) != 0)
{
int result;
/* Handle any data remaining the RX FIFO. If the RX FIFO is
* less than half full at the end of the transfer, then no
* half-full interrupt will be received.
@ -827,18 +801,10 @@ static int stm32_interrupt(int irq, void *context)
stm32_recvfifo(priv);
}
/* Check if we are supposed to send STOP_TRANSMISSION now */
result = OK;
if (priv->stopxfr)
{
result = stm32_stoptransmission(priv);
}
/* Then terminate the transfer */
putreg32(SDIO_ICR_DATAENDC, STM32_SDIO_ICR);
stm32_endtransfer(priv, result);
stm32_endtransfer(priv, OK);
}
/* Handler data block send/receive CRC failure */
@ -1116,6 +1082,10 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer,
DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
DEBUGASSERT(((uint32)buffer & 3) == 0);
/* Reset the DPSM configuration */
stm32_datadisable();
/* Save the destination buffer information for use by the interrupt handler */
priv->buffer = (uint32*)buffer;
@ -1166,6 +1136,10 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const ubyte *buffer,
DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
DEBUGASSERT(((uint32)buffer & 3) == 0);
/* Reset the DPSM configuration */
stm32_datadisable();
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32*)buffer;
@ -1706,6 +1680,10 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer,
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
DEBUGASSERT(((uint32)buffer & 3) == 0);
/* Reset the DPSM configuration */
stm32_datadisable();
/* Wide bus operation is required for DMA */
if (priv->widebus)
@ -1731,6 +1709,10 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR ubyte *buffer,
putreg32(1, SDIO_DCTRL_DMAEN_BB);
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer,
(buflen + 3) >> 2, SDIO_RXDMA16_CONFIG);
/* Start the DMA */
stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE);
ret = OK;
}
return ret;
@ -1767,6 +1749,10 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
DEBUGASSERT(((uint32)buffer & 3) == 0);
/* Reset the DPSM configuration */
stm32_datadisable();
/* Wide bus operation is required for DMA */
if (priv->widebus)
@ -1794,35 +1780,16 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32)buffer,
(buflen + 3) >> 2, SDIO_TXDMA16_CONFIG);
putreg32(1, SDIO_DCTRL_DMAEN_BB);
/* Start the DMA */
stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE);
ret = OK;
}
return ret;
}
#endif
/****************************************************************************
* Name: stm32_sdiodmastart
*
* Description:
* Start the DMA
*
* Input Parameters:
* dev - An instance of the SDIO device interface
*
* Returned Value:
* OK on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SDIO_DMA
static int stm32_sdiodmastart(FAR struct sdio_dev_s *dev)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
stm32_dmastart(priv->dma, stm32_dmacallback, priv, FALSE);
return OK;
}
#endif
/****************************************************************************
* Initialization/uninitialization/reset
****************************************************************************/

998
drivers/mmcsd/mmcsd_sdio.c
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File diff suppressed because it is too large Load Diff

24
drivers/mmcsd/mmcsd_sdio.h
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@ -115,7 +115,7 @@
#define MMCSD_R1_AKESEQERROR (1 << 3) /* Authentication error */
#define MMCSD_R1_ERRORMASK 0xfdffe008 /* Error mask */
#define IS_STATE(v,s) (((v)&MMCSD_R1_CURRENTSTATE_MASK)==(s))
#define IS_STATE(v,s) (((v)&MMCSD_R1_STATE_MASK)==(s))
/* R3 (OCR) */
@ -148,6 +148,28 @@
#define MMCSD_R3_HIGHCAPACITY (1 << 30) /* TRUE: Card supports block addressing */
#define MMCSD_CARD_BUSY (1 << 31) /* Card power-up busy bit */
/* R6 Card Status bit definitions */
#define MMCSD_R6_RCA_SHIFT (16) /* New published RCA */
#define MMCSD_R6_RCA_MASK (0xffff << MMCSD_R6_RCA_SHIFT)
#define MMCSD_R6_COMCRCERROR (1 << 15) /* CRC error */
#define MMCSD_R6_ILLEGALCOMMAND (1 << 14) /* Bad command */
#define MMCSD_R6_ERROR (1 << 13) /* General error */
#define MMCSD_R6_STATE_SHIFT (9) /* Current card state */
#define MMCSD_R6_STATE_MASK (15 << MMCSD_R6_STATE_SHIFT)
/* Card identification mode states */
# define MMCSD_R6_STATE_IDLE (0 << MMCSD_R6_STATE_SHIFT) /* 0=Idle state */
# define MMCSD_R6_STATE_READY (1 << MMCSD_R6_STATE_SHIFT) /* 1=Ready state */
# define MMCSD_R6_STATE_IDENT (2 << MMCSD_R6_STATE_SHIFT) /* 2=Identification state */
/* Data transfer states */
# define MMCSD_R6_STATE_STBY (3 << MMCSD_R6_STATE_SHIFT) /* 3=Standby state */
# define MMCSD_R6_STATE_TRAN (4 << MMCSD_R6_STATE_SHIFT) /* 4=Transfer state */
# define MMCSD_R6_STATE_DATA (5 << MMCSD_R6_STATE_SHIFT) /* 5=Sending data state */
# define MMCSD_R6_STATE_RCV (6 << MMCSD_R6_STATE_SHIFT) /* 6=Receiving data state */
# define MMCSD_R6_STATE_PRG (7 << MMCSD_R6_STATE_SHIFT) /* 7=Programming state */
# define MMCSD_R6_STATE_DIS (8 << MMCSD_R6_STATE_SHIFT) /* 8=Disconnect state */
#define MMCSD_R6_ERRORMASK 0x0000e000 /* Error mask */
/* SD Configuration Register (SCR) encoding */
#define MMCSD_SCR_BUSWIDTH_1BIT (1)

25
include/nuttx/sdio.h
View File

@ -629,7 +629,7 @@
* Setup to perform a read DMA. If the processor supports a data cache,
* then this method will also make sure that the contents of the DMA memory
* and the data cache are coherent. For read transfers this may mean
* invalidating the data cache.
* invalidating the data cache. Upon return, DMA is enable and waiting.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
@ -654,7 +654,7 @@
* Setup to perform a write DMA. If the processor supports a data cache,
* then this method will also make sure that the contents of the DMA memory
* and the data cache are coherent. For write transfers, this may mean
* flushing the data cache.
* flushing the data cache. Upon return, DMA is enable and waiting.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
@ -672,26 +672,6 @@
# define SDIO_DMASENDSETUP(dev,buffer,len) (-ENOSYS)
#endif
/****************************************************************************
* Name: SDIO_DMASTART
*
* Description:
* Start the DMA
*
* Input Parameters:
* dev - An instance of the SDIO device interface
*
* Returned Value:
* OK on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_SDIO_DMA
# define SDIO_DMASTART(dev) ((dev)->dmastart(dev))
#else
# define SDIO_DMASTART(dev) (-ENOSYS)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
@ -772,7 +752,6 @@ struct sdio_dev_s
size_t buflen);
int (*dmasendsetup)(FAR struct sdio_dev_s *dev, FAR const ubyte *buffer,
size_t buflen);
int (*dmastart)(FAR struct sdio_dev_s *dev);
#endif
};