SAMV71: Add Supply Controller register definition header file
This commit is contained in:
Gregory Nutt
parent
7113de4d18
commit
7f92f22167
@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/chip/sam_clockconfig.c
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* arch/arm/src/sam34/sam_clockconfig.c
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*
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* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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185
arch/arm/src/samv7/chip/sam_supc.h
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185
arch/arm/src/samv7/chip/sam_supc.h
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_supc.h
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* Supply Controller (SUPC) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* SUPC register offsets ****************************************************************/
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#define SAM_SUPC_CR_OFFSET 000x00 /* Supply Controller Control Register */
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#define SAM_SUPC_SMMR_OFFSET 0x0004 /* Supply Controller Supply Monitor Mode Register */
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#define SAM_SUPC_MR_OFFSET 0x0008 /* Supply Controller Mode Register */
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#define SAM_SUPC_WUMR_OFFSET 0x000c /* Supply Controller Wake Up Mode Register */
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#define SAM_SUPC_WUIR_OFFSET 0x0010 /* Supply Controller Wake Up Inputs Register */
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#define SAM_SUPC_SR_OFFSET 0x0014 /* Supply Controller Status Register */
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/* SUPC register addresses **************************************************************/
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#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
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#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
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#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET)
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#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET)
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#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
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#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
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/* SUPC register bit definitions ********************************************************/
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/* Supply Controller Control Register */
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#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
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#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */
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#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT)
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# define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT)
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/* Supply Controller Supply Monitor Mode Register */
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#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */
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#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
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# define SUPC_SMMR_SMTH(n) ((uint32_t)(n) << SUPC_SMMR_SMTH_SHIFT)
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# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.58 < 1.60 < 1.62 */
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# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.70 < 1.72 < 1.74 */
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# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.82 < 1.84 < 1.86 */
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# define SUPC_SMMR_SMTH_2p0V (3 << SUPC_SMMR_SMTH_SHIFT) /* 1.94 < 1.96 < 1.98 */
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# define SUPC_SMMR_SMTH_2p2V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.05 < 2.08 < 2.11 */
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# define SUPC_SMMR_SMTH_2p6V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.17 < 2.20 < 2.23 */
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# define SUPC_SMMR_SMTH_2p3V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.29 < 2.32 < 2.35 */
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# define SUPC_SMMR_SMTH_2p4V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.41 < 2.44 < 2.47 */
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# define SUPC_SMMR_SMTH_2p6V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.53 < 2.56 < 2.59 */
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# define SUPC_SMMR_SMTH_2p7V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.65 < 2.68 < 2.71 */
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# define SUPC_SMMR_SMTH_2p8V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.77 < 2.80 < 2.83 */
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# define SUPC_SMMR_SMTH_2p9V (11 << SUPC_SMMR_SMTH_SHIFT) /* 2.90 < 2.92 < 2.95 */
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# define SUPC_SMMR_SMTH_3p0V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.00 < 3.04 < 3.07 */
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# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.12 < 3.16 < 3.20 */
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# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.24 < 3.28 < 3.32 */
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# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.36 < 3.40 < 3.44 */
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#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */
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#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT)
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# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */
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# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */
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# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
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# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
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# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
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#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
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#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
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/* Supply Controller Mode Register */
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#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
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#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
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#define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */
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#define SUPC_MR_BKUPRETON (1 << 17) /* Bit 17: SRAM On In Backup Mode */
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#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */
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#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */
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#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT)
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# define SUPC_MR_KEY (0xa5 << SUPC_MR_KEY_SHIFT)
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/* Supply Controller Wake Up Mode Register */
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#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */
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#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */
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#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */
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#define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */
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#define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */
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#define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */
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#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
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#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
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# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
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# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */
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# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */
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# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */
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# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
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# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
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#define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */
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#define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT)
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# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */
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# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */
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/* System Controller Wake Up Inputs Register */
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#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-13: Wake Up Input Enable 0 to 13 */
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#define SUPC_WUIR_WKUPEN_MASK (0x3fff << SUPC_WUIR_WKUPEN_SHIFT)
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# define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT)
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#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 13 */
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#define SUPC_WUIR_WKUPT_MASK (0x3fff << SUPC_WUIR_WKUPT_SHIFT)
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# define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT)
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/* Supply Controller Status Register */
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#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */
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#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */
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#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */
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#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */
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#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */
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#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
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#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
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#define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */
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#define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */
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#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-29: WKUP Input Status 0 to 13 */
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#define SUPC_SR_WKUPIS_MASK (0x3fff << SUPC_SR_WKUPIS_SHIFT)
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# define SUPC_SR_WKUPIS(n) (1 << (SUPC_SR_WKUPIS_SHIFT+(n)))
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H */
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81
arch/arm/src/samv7/chip/sam_sysc.h
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81
arch/arm/src/samv7/chip/sam_sysc.h
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@ -0,0 +1,81 @@
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_sysc.h
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* Supply Controller (SYSC) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* SYSC register offsets ****************************************************************/
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#define SAM_SYSC_WPMR_OFFSET 0x0004 /* Write Protection Mode Register */
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/* SYSC register addresses **************************************************************/
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#define SAM_SYSC_WPMR (SAM_SYSC_BASE+SAM_SYSC_WPMR_OFFSET)
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/* SYSC register bit definitions ********************************************************/
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/* System Controller Write Protect Mode Register */
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#define SYSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
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#define SYSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
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#define SYSC_WPMR_WPKEY_MASK (0x00ffffff << SYSC_WPMR_WPKEY_SHIFT)
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# define SYSC_WPMR_WPKEY (0x00525443 << SYSC_WPMR_WPKEY_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H */
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@ -143,6 +143,7 @@
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# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */
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# define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */
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# define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */
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# define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */
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# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1850-0x400e19ff: Watchdog Timer 1 (WDT1) */
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#define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */
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#define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */
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