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STL32 F15x: stm32_stdclockconfig() was calling stm32_pw_setvos() which accessed PWR_CR via an inactive APB. From Juha Niskanen.

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This commit is contained in:
Gregory Nutt 2015-06-11 08:09:36 -06:00
parent 98b2034cdf
commit 7fab748667
1 changed files with 8 additions and 1 deletions
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9
arch/arm/src/stm32/stm32l15xxx_rcc.c
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@ -110,6 +110,7 @@ static inline void rcc_reset(void)
* the SYSCLK and we want the PLL to be stable through the transition.
*/
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCOSEL_MASK | RCC_CFGR_MCOPRE_MASK);
putreg32(regval, STM32_RCC_CFGR);
@ -524,6 +525,12 @@ static void stm32_stdclockconfig(void)
uint16_t pwrcr;
#endif
/* Enable PWR clock from APB1 to give access to PWR_CR register */
regval = getreg32(STM32_RCC_APB1ENR);
regval |= RCC_APB1ENR_PWREN;
putreg32(regval, STM32_RCC_APB1ENR);
/* Go to the high performance voltage range 1 if necessary. In this mode,
* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported.
*
@ -563,7 +570,7 @@ static void stm32_stdclockconfig(void)
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_RTCPRE_MASK;
regval |= HSE_DIVISOR);
regval |= HSE_DIVISOR;
putreg32(regval, STM32_RCC_CR);
/* Restore the previous state of the DBP bit */