Some fixes to last commit
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7887971ea5
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@ -141,8 +141,8 @@
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/* GPIO interrupt configuration register1/2 */
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#define GPIO_ICR_INDEX(n) ((n) >> 4)
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#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2));
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#define GPIO_ICR_INDEX(n) (((n) >> 4) & 1)
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#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2))
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#define GPIO_ICR_LOWLEVEL 0 /* Interrupt is low-level sensitive */
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#define GPIO_ICR_HIGHLEVEL 1 /* Interrupt is high-level sensitive */
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@ -181,7 +181,7 @@
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#define IMX_CAN1_OFFSET 0x00090000 /* 00090000 00093fff CAN1 16 KB */
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#define IMX_CAN2_OFFSET 0x00094000 /* 00094000 00097fff CAN2 16 KB */
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#define IMX_GPT_OFFSET 0x00098000 /* 00098000 0009bfff GPT 16 KB */
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#define IMX_GPIO_OFFSET(n) (0x0009c000 - ((n) << 14)) /* n=0..6 */
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#define IMX_GPIO_OFFSET(n) (0x0009c000 + ((n) << 14)) /* n=0..6 */
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#define IMX_GPIO1_OFFSET 0x0009c000 /* 0009c000 0009ffff GPIO1 16 KB */
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#define IMX_GPIO2_OFFSET 0x000a0000 /* 000a0000 000a3fff GPIO2 16 KB */
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#define IMX_GPIO3_OFFSET 0x000a4000 /* 000a4000 000a7fff GPIO3 16 KB */
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