From 8fdef878ba721e3198be2f9586dfd4d7464209fa Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 29 Mar 2016 07:13:24 -0600 Subject: [PATCH 1/3] Minor optimization to PR #60 --- arch/arm/src/stm32l4/stm32l4_lse.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index cc193e949e..9fd4b5325a 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -62,7 +62,7 @@ void stm32l4_rcc_enablelse(void) { - bool bkpenabled; + bool writable; uint32_t regval; /* The LSE is in the RTC domain and write access is denied to this domain @@ -70,7 +70,7 @@ void stm32l4_rcc_enablelse(void) * register before to configuring the LSE. */ - bkpenabled = stm32l4_pwr_enablebkp(true); + writable = stm32l4_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit * the RCC BDCR register. @@ -89,8 +89,5 @@ void stm32l4_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - if (!bkpenabled) - { - (void)stm32l4_pwr_enablebkp(false); - } + (void)stm32l4_pwr_enablebkp(writable); } From f9c2f70b3614c513cb0a890489486420b3369136 Mon Sep 17 00:00:00 2001 From: Dave Date: Tue, 29 Mar 2016 07:19:00 -0600 Subject: [PATCH 2/3] STM32L4 PWR: Fix reversed parameters in putreg32() --- arch/arm/src/stm32l4/stm32l4_pwr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index 972388e82d..7659f73147 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -105,14 +105,14 @@ bool stm32l4_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(STM32L4_RCC_APB1ENR1, regval); + putreg32(regval, STM32L4_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(STM32L4_RCC_APB1ENR1, regval); + putreg32(regval, STM32L4_RCC_APB1ENR1); } return wasenabled; From 940075f6297bc2d9b6bea694cd76b758e31bed2f Mon Sep 17 00:00:00 2001 From: Michael Spahlinger Date: Tue, 29 Mar 2016 07:25:37 -0600 Subject: [PATCH 3/3] SAMV71/SAME70: Error in UART1 Pinmapping corrected --- arch/arm/src/samv7/chip/same70_pinmap.h | 6 +++--- arch/arm/src/samv7/chip/samv71_pinmap.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/samv7/chip/same70_pinmap.h b/arch/arm/src/samv7/chip/same70_pinmap.h index fd7736c84e..160963c00e 100644 --- a/arch/arm/src/samv7/chip/same70_pinmap.h +++ b/arch/arm/src/samv7/chip/same70_pinmap.h @@ -486,9 +486,9 @@ #define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) #define GPIO_UART1_RXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_UART1_TXD (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26) -#define GPIO_UART1_TXD_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_UART1_TXD_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_UART1_TXD_1 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26) +#define GPIO_UART1_TXD_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_UART1_TXD_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) #define GPIO_UART2_RXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN25) #define GPIO_UART2_TXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26) diff --git a/arch/arm/src/samv7/chip/samv71_pinmap.h b/arch/arm/src/samv7/chip/samv71_pinmap.h index cb9942f2d2..497035e70c 100644 --- a/arch/arm/src/samv7/chip/samv71_pinmap.h +++ b/arch/arm/src/samv7/chip/samv71_pinmap.h @@ -492,9 +492,9 @@ #define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN10) #define GPIO_UART1_RXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5) -#define GPIO_UART1_TXD (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26) -#define GPIO_UART1_TXD_1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) -#define GPIO_UART1_TXD_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_UART1_TXD_1 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26) +#define GPIO_UART1_TXD_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_UART1_TXD_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6) #define GPIO_UART2_RXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN25) #define GPIO_UART2_TXD (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN26)