SAML21: Add some parameter checking for FDPLL96M
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@ -73,6 +73,23 @@
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/****************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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* Pre-processor Definitions
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****************************************************************************/
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****************************************************************************/
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/* Force enabling of the FDPLL reference clock */
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#ifdef BOARD_FDPLL96M_ENABLE
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# if BOARD_FDPLL96M_REFCLK == OSCCTRL_DPLLCTRLB_REFLCK_XOSC && \
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!defined(BOARD_XOSC_ENABLE)
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# warning Forcing BOARD_XOSC_ENABLE for FDPLL96M
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# define BOARD_XOSC_ENABLE 1
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# elif BOARD_FDPLL96M_REFCLK == OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K && \
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!defined(BOARD_XOSC32K_ENABLE)
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# warning Forcing BOARD_XOSC32K_ENABLE for FDPLL96M
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# define BOARD_XOSC32K_ENABLE 1
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# elif BOARD_FDPLL96M_REFCLK == OSCCTRL_DPLLCTRLB_REFLCK_GLCK && \
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!defined(BOARD_GCLK_ENABLE)
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# warning Forcing BOARD_GCLK_ENABLE for FDPLL96M
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# define BOARD_GCLK_ENABLE 1
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# endif
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#endif
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/****************************************************************************
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/****************************************************************************
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* Private Types
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* Private Types
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@ -226,6 +226,14 @@
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#define BOARD_DFLL48M_FREQUENCY (48000000)
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#define BOARD_DFLL48M_FREQUENCY (48000000)
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/* Fractional Digital Phase Locked Loop configuration.
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*
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* BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions
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*/
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#undef BOARD_FDPLL96M_ENABLE
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#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSC
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/* GCLK Configuration
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/* GCLK Configuration
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*
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*
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* Global enable/disable.
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* Global enable/disable.
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