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XMC4xxx: Fixes to HIB domain setup, GPIO pin configuration.

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This commit is contained in:
Gregory Nutt 2017-03-21 09:31:44 -06:00
parent 1b266096c7
commit 805a4f65e9
5 changed files with 12 additions and 12 deletions
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2
arch/arm/include/xmc4/xmc4500_irq.h
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@ -184,7 +184,7 @@
#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */
#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */

2
arch/arm/src/xmc4/chip/xmc4_memorymap.h
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@ -221,7 +221,7 @@
#define XMC4_USB0_EP4_BASE 0x50040980
#define XMC4_USB0_EP5_BASE 0x500409a0
#define XMC4_USB0_EP6_BASE 0x500409c0
#define XMC4_USB0_EP6_BASE 0x50100000 /* ECAT0 */
#define XMC4_ECAT0_BASE 0x50100000 /* ECAT0 */
#define XMC4_PMU0_BASE 0x58000000 /* PMU0 registers */
#define XMC4_FLASH0_BASE 0x58001000

4
arch/arm/src/xmc4/chip/xmc4_ports.h
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@ -71,7 +71,7 @@
#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */
#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */
#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3))
#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & ~3))
#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */
#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */
#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */
@ -79,7 +79,7 @@
#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */
#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3))
#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & ~3))
#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */
#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */

8
arch/arm/src/xmc4/xmc4_clockconfig.c
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@ -182,9 +182,9 @@ void xmc4_clock_configure(void)
regval = getreg32(XMC4_SCU_PWRSTAT);
if ((regval & SCU_PWR_HIBEN) == 0)
{
regval = getreg32(XMC4_SCU_PWRSET);
regval |= SCU_PWR_HIBEN;
putreg32(regval, XMC4_SCU_PWRSTAT);
/* Enable the HIB domain */
putreg32(SCU_PWR_HIBEN, XMC4_SCU_PWRSET);
/* Wait until HIB domain is enabled */
@ -193,7 +193,7 @@ void xmc4_clock_configure(void)
}
}
/* Remove the reset only if HIB domain were in a state of reset */
/* Remove the reset only if HIB domain was in a state of reset */
regval = getreg32(XMC4_SCU_RSTSTAT);
if ((regval & SCU_RSTSTAT_HIBRS) != 0)

8
arch/arm/src/xmc4/xmc4_gpio.h
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@ -79,8 +79,8 @@
# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT)
# define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT)
# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0)
# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0)
# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0)
# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0)
/* Pin type modifier:
*
@ -160,7 +160,7 @@
*/
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
@ -180,7 +180,7 @@
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)