sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/armv7-ar: flush dcache when addr is not aligned with cache line

Browse Source 
When invalidate address is not aligned with cache line,
must align address and flush the cache line.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-01-16 11:36:29 +08:00 committed by Xiang Xiao
parent 4bb155db64
commit 806a2a8b8d
2 changed files with 36 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/src/armv7-a/cp15_cacheops.c
View File

@ -94,16 +94,32 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
uint32_t line;
line = cp15_cache_get_info(NULL, NULL);
start &= ~(line - 1);
ARM_DSB();
if ((start & (line - 1)) != 0)
{
start &= ~(line - 1);
if (op == CP15_CACHE_INVALIDATE)
{
cp15_cleaninvalidate_dcacheline_bymva(start);
start += line;
}
}
while (start < end)
{
switch (op)
{
case CP15_CACHE_INVALIDATE:
cp15_invalidate_dcacheline_bymva(start);
if (start + line <= end)
{
cp15_invalidate_dcacheline_bymva(start);
}
else
{
cp15_cleaninvalidate_dcacheline_bymva(start);
}
break;
case CP15_CACHE_CLEAN:
cp15_clean_dcache_bymva(start);

20
arch/arm/src/armv7-r/cp15_cacheops.c
View File

@ -94,16 +94,32 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
uint32_t line;
line = cp15_cache_get_info(NULL, NULL);
start &= ~(line - 1);
ARM_DSB();
if ((start & (line - 1)) != 0)
{
start &= ~(line - 1);
if (op == CP15_CACHE_INVALIDATE)
{
cp15_cleaninvalidate_dcacheline_bymva(start);
start += line;
}
}
while (start < end)
{
switch (op)
{
case CP15_CACHE_INVALIDATE:
cp15_invalidate_dcacheline_bymva(start);
if (start + line <= end)
{
cp15_invalidate_dcacheline_bymva(start);
}
else
{
cp15_cleaninvalidate_dcacheline_bymva(start);
}
break;
case CP15_CACHE_CLEAN:
cp15_clean_dcache_bymva(start);