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STM32L4 ADC: implement peripheral

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This commit is contained in:
Juha Niskanen 2017-08-28 07:05:04 -06:00 committed by Gregory Nutt
parent a2dc88e075
commit 809569cda9
5 changed files with 1736 additions and 24 deletions
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2
arch/arm/src/stm32f7/stm32_adc.c
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@ -1020,7 +1020,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
* reset values. It could set all the ADCs configured.
*
* Input Parameters:
* regaddr - The register to read
* priv - A reference to the ADC block status
* reset - Condition, set or reset
*
* Returned Value:

2
arch/arm/src/stm32l4/README.txt
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@ -43,7 +43,7 @@ CRC : TODO (configurable polynomial)
WWDG : TODO
IWDG : works
MMCSD : TODO
ADC : TODO
ADC : Code written, to be tested
DAC : Code written, to be tested
DMA2D : TODO (Chrom-Art Accelerator for image manipulation)

22
arch/arm/src/stm32l4/chip/stm32l4_adc.h
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@ -373,6 +373,10 @@
#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */
#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT)
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (6)
/* ADC regular sequence register 1 */
#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */
@ -385,6 +389,10 @@
#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT)
#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */
#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT)
#define ADC_SQR1_RESERVED (0xe0820830)
#define ADC_SQR1_FIRST (1)
#define ADC_SQR1_LAST (4)
#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET)
/* ADC regular sequence register 2 */
@ -398,6 +406,10 @@
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT )
#define ADC_SQR2_RESERVED (0xe0820820)
#define ADC_SQR2_FIRST (5)
#define ADC_SQR2_LAST (9)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
@ -410,7 +422,11 @@
#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */
#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT )
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT)
#define ADC_SQR3_RESERVED (0xe0820820)
#define ADC_SQR3_FIRST (10)
#define ADC_SQR3_LAST (14)
#define ADC_SQR3_SQ_OFFSET (0)
/* ADC regular sequence register 4 */
@ -418,6 +434,10 @@
#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT)
#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 15th conversion in regular sequence */
#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT)
#define ADC_SQR4_RESERVED (0xfffff820)
#define ADC_SQR4_FIRST (15)
#define ADC_SQR4_LAST (16)
#define ADC_SQR4_SQ_OFFSET (0)
/* ADC regular data register */

15
arch/arm/src/stm32l4/chip/stm32l4_tim.h
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@ -1,4 +1,4 @@
/****************************************************************************************************
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4_tim.h
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
@ -32,16 +32,16 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_TIM_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_TIM_H
/****************************************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
************************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *****************************************************************/
/* Basic Timers - TIM6 and TIM7 */
@ -127,7 +127,7 @@
#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter (16-bit) */
#define STM32L4_LPTIM_OR_OFFSET 0x001c /* Options Register */
/* Register Addresses *******************************************************************************/
/* Register Addresses ***************************************************************/
/* Advanced Timers - TIM1 and TIM8 */
@ -341,7 +341,7 @@
#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET)
#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* Register Bitfield Definitions ****************************************************/
/* Control register 1 */
@ -671,6 +671,7 @@
#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */

1719
arch/arm/src/stm32l4/stm32l4_adc.c
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