SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC
This commit is contained in:
Gregory Nutt
parent
519c8f3e97
commit
80c0b5628d
@ -179,16 +179,6 @@
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#define HSCMI_NOTXDMA 1
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/* There are two ways to DMA:
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*
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* (1) Use the FIFO address, incrementing the address on the HSMCI side
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* (2) Use the TDR/RDR address with no address increment
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*
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* Both work.
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*/
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#undef HSCMI_FIFODMA
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/* Timing */
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#define HSMCI_CMDTIMEOUT (100000)
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@ -198,35 +188,17 @@
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#define HSMCI_DTIMER_DATATIMEOUT (0x000fffff)
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/* DMA configuration flags. There are two ways to to this:
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*
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* (1) Use the FIFO address, incrementing the address on the HSMCI side
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* (2) Use the TDR/RDR address with no address increment
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*
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* REVISIT: Is memory always on IF0?
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*/
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/* DMA configuration flags */
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#define HSMCI_DMA_CHKSIZE HSMCI_DMA_CHKSIZE_1
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#ifdef HSCMI_FIFODMA
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# define DMA_FLAGS(pid) \
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(DMACH_FLAG_PERIPHPID(pid) | HSMCI_SYSBUS_IF | \
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DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
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DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHINCREMENT | \
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DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
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DMACH_FLAG_MEMPID_MAX | MEMORY_SYSBUS_IF | \
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DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
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DMACH_FLAG_MEMCHUNKSIZE_4 | DMACH_FLAG_MEMBURST_1)
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#else
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# define DMA_FLAGS(pid) \
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(DMACH_FLAG_PERIPHPID(pid) | HSMCI_SYSBUS_IF | \
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DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
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DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
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DMACH_FLAG_MEMPID_MAX | MEMORY_SYSBUS_IF | \
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DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
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DMACH_FLAG_MEMCHUNKSIZE_4 | DMACH_FLAG_MEMBURST_1)
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#endif
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#define DMA_FLAGS(pid) \
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(DMACH_FLAG_PERIPHPID(pid) | HSMCI_SYSBUS_IF | \
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DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
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DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
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DMACH_FLAG_MEMPID_MAX | MEMORY_SYSBUS_IF | \
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DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
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DMACH_FLAG_MEMCHUNKSIZE_4 | DMACH_FLAG_MEMBURST_1)
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/* Status errors:
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*
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@ -1026,13 +998,18 @@ static void sam_hsmcidump(struct sam_dev_s *priv,
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#ifdef CONFIG_SAMA5_HSMCI_XFRDEBUG
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static void sam_xfrsample(struct sam_dev_s *priv, int index)
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{
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struct sam_xfrregs_s *regs = &priv->xfrsamples[index];
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/* On a multiple block transfer, only sample on the first block */
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if ((priv->smplset & (1 << index)) == 0)
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{
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struct sam_xfrregs_s *regs = &priv->xfrsamples[index];
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#ifdef CONFIG_DEBUG_DMA
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sam_dmasample(priv->dma, ®s->dma);
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sam_dmasample(priv->dma, ®s->dma);
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#endif
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sam_hsmcisample(priv, ®s->hsmci);
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priv->smplset |= (1 << index);
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sam_hsmcisample(priv, ®s->hsmci);
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priv->smplset |= (1 << index);
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}
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}
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#endif
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@ -1204,49 +1181,56 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
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struct sam_dev_s *priv = (struct sam_dev_s *)arg;
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sdio_eventset_t wkupevent;
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/* Mark the DMA not busy and sample DMA registers */
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priv->dmabusy = false;
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sam_xfrsample((struct sam_dev_s *)arg, SAMPLENDX_DMA_CALLBACK);
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/* Disable the DMA handshaking */
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sam_putreg(priv, 0, SAM_HSMCI_DMA_OFFSET);
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/* Terminate the transfer with an I/O error in the event of a DMA failure */
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if (result < 0)
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{
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wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
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flldbg("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
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/* sam_endtransfer will terminate the transfer and wait up the waiting
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* client in this case.
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*/
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sam_endtransfer(priv, wkupevent);
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}
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/* The DMA completed without error. Wake-up the waiting client if (1) both the
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* HSMCI and DMA completion events, and (2) There is a client waiting for
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* this event.
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*
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* If the HSMCI transfer event has already completed, it must have completed
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* successfully (because the DMA was not cancelled). sam_endtransfer() should
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* have already received the SDIOWAIT_TRANSFERDONE event, but this event would
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* not yet have been recorded. We need to post the SDIOWAIT_TRANSFERDONE
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* again in this case here.
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*
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* The timeout will remain active until sam_endwait() is eventually called
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* so we should not have any concern about hangs if the HSMCI transfer never
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* completed.
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/* Is DMA still active? We can get this callback when sam_dmastop() is
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* called too.
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*/
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else if (!priv->xfrbusy && (priv->waitevents & SDIOWAIT_TRANSFERDONE) != 0)
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if (priv->dmabusy)
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{
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/* Okay.. wake up any waiting threads */
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/* Mark the DMA not busy and sample DMA registers */
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sam_endwait(priv, SDIOWAIT_TRANSFERDONE);
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priv->dmabusy = false;
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sam_xfrsample((struct sam_dev_s *)arg, SAMPLENDX_DMA_CALLBACK);
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/* Disable the DMA handshaking */
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sam_putreg(priv, 0, SAM_HSMCI_DMA_OFFSET);
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/* Terminate the transfer with an I/O error in the event of a DMA failure */
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if (result < 0)
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{
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wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
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flldbg("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
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/* sam_endtransfer will terminate the transfer and wait up the waiting
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* client in this case.
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*/
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sam_endtransfer(priv, wkupevent);
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}
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/* The DMA completed without error. Wake-up the waiting client if (1) both the
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* HSMCI and DMA completion events, and (2) There is a client waiting for
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* this event.
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*
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* If the HSMCI transfer event has already completed, it must have completed
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* successfully (because the DMA was not cancelled). sam_endtransfer() should
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* have already received the SDIOWAIT_TRANSFERDONE event, but this event would
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* not yet have been recorded. We need to post the SDIOWAIT_TRANSFERDONE
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* again in this case here.
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*
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* The timeout will remain active until sam_endwait() is eventually called
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* so we should not have any concern about hangs if the HSMCI transfer never
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* completed.
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*/
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else if (!priv->xfrbusy && (priv->waitevents & SDIOWAIT_TRANSFERDONE) != 0)
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{
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/* Okay.. wake up any waiting threads */
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sam_endwait(priv, SDIOWAIT_TRANSFERDONE);
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}
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}
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}
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@ -1294,7 +1278,23 @@ static void sam_eventtimeout(int argc, uint32_t arg)
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DEBUGASSERT(argc == 1 && priv != NULL);
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sam_xfrsample((struct sam_dev_s *)arg, SAMPLENDX_TIMEOUT);
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/* Is a data transfer complete event expected? */
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/* Make sure that any hung DMA is stopped. dmabusy == false is the cue
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* so the DMA callback is ignored.
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*/
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priv->dmabusy = false;
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sam_dmastop(priv->dma);
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/* Disable the DMA handshaking */
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sam_putreg(priv, 0, SAM_HSMCI_DMA_OFFSET);
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/* Make sure that any hung HSMCI transfer is stopped */
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sam_disablexfrints(priv);
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sam_notransfer(priv);
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/* Is a data timeout complete event expected? (should always be the case) */
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if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
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{
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@ -1380,8 +1380,16 @@ static void sam_endtransfer(struct sam_dev_s *priv,
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if ((wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR)) != 0)
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{
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sam_dmastop(priv->dma);
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/* dmabusy == false gives the DMA callback handler a clue about what
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* is going on.
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*/
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priv->dmabusy = false;
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sam_dmastop(priv->dma);
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/* Disable the DMA handshaking */
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sam_putreg(priv, 0, SAM_HSMCI_DMA_OFFSET);
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}
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/* The transfer is complete. Wake-up the waiting client if (1) both the
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@ -1418,11 +1426,13 @@ static void sam_endtransfer(struct sam_dev_s *priv,
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static void sam_notransfer(struct sam_dev_s *priv)
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{
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uint32_t regval;
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/* Make read/write proof (or not). This is a legacy behavior: This really
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* just needs be be done once at initialization time.
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*/
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uint32_t regval = sam_getreg(priv, SAM_HSMCI_MR_OFFSET);
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regval = sam_getreg(priv, SAM_HSMCI_MR_OFFSET);
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regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF);
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sam_putreg(priv, regval, SAM_HSMCI_MR_OFFSET);
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@ -1437,7 +1447,7 @@ static void sam_notransfer(struct sam_dev_s *priv)
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}
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/****************************************************************************
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* Interrrupt Handling
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* Interrupt Handling
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****************************************************************************/
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/****************************************************************************
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@ -1968,7 +1978,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
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break;
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}
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/* 'OR' in data transer related bits */
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/* 'OR' in data transfer related bits */
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switch (cmd & MMCSD_DATAXFR_MASK)
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{
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@ -2098,10 +2108,12 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
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/* Make sure that the DMA is stopped (it will be stopped automatically
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* on normal transfers, but not necessarily when the transfer terminates
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* on an error condition.
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*
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* dmabusy == false let's the DMA callback know what is happening.
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*/
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sam_dmastop(priv->dma);
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priv->dmabusy = false;
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sam_dmastop(priv->dma);
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/* Disable the DMA handshaking */
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@ -2683,34 +2695,57 @@ static bool sam_dmasupported(FAR struct sdio_dev_s *dev)
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****************************************************************************/
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static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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size_t buflen)
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size_t buflen)
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{
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struct sam_dev_s *priv = (struct sam_dev_s *)dev;
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uint32_t paddr;
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uint32_t maddr;
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uint32_t regval;
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unsigned int blocksize;
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unsigned int nblocks;
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unsigned int offset;
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unsigned int i;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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DEBUGASSERT(((uint32_t)buffer & 3) == 0);
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/* Physical address of the HSCMI RDR register and of the buffer location
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* in RAM.
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/* How many blocks? That should have been saved by the sam_blocksetup()
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* method earlier.
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*/
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#ifdef HSCMI_FIFODMA
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paddr = hsmci_physregaddr(priv, SAM_HSMCI_FIFO_OFFSET);
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#else
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paddr = hsmci_physregaddr(priv, SAM_HSMCI_RDR_OFFSET);
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#endif
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maddr = sam_physramaddr((uintptr_t)buffer);
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regval = sam_getreg(priv, SAM_HSMCI_BLKR_OFFSET);
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nblocks = ((regval & HSMCI_BLKR_BCNT_MASK) >> HSMCI_BLKR_BCNT_SHIFT);
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blocksize = ((regval & HSMCI_BLKR_BLKLEN_MASK) >> HSMCI_BLKR_BLKLEN_SHIFT);
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/* Setup register sampling */
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DEBUGASSERT(nblocks > 0 && blocksize > 0 && (blocksize & 3) == 0);
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/* Physical address of the HSCMI source register, either the TDR (for
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* single transfers) or the first FIFO register, and the physcal address
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* of the buffer in RAM.
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*/
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offset = (nblocks == 1 ? SAM_HSMCI_RDR_OFFSET : SAM_HSMCI_FIFO_OFFSET);
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paddr = hsmci_physregaddr(priv, offset);
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maddr = sam_physramaddr((uintptr_t)buffer);
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/* Setup register sampling (only works for the case of nblocks == 1) */
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sam_xfrsampleinit(priv);
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sam_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
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/* Configure the RX DMA */
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/* Set DMA for each block */
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sam_dmarxsetup(priv->dma, paddr, maddr, buflen);
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for (i = 0; i < nblocks; i++)
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{
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/* Configure the RX DMA */
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sam_dmarxsetup(priv->dma, paddr, maddr, buflen);
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/* Update addresses for the next block */
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paddr += sizeof(uint32_t);
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maddr += blocksize;
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}
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/* Enable DMA handshaking */
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@ -2725,7 +2760,7 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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sam_dmastart(priv->dma, sam_dmacallback, priv);
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/* Configure transfer-related interrupts. Transfer interrupts are not
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* enabled until after the transfer is stard with an SD command (i.e.,
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* enabled until after the transfer is started with an SD command (i.e.,
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* at the beginning of sam_eventwait().
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*/
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@ -2754,33 +2789,57 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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****************************************************************************/
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static int sam_dmasendsetup(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
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FAR const uint8_t *buffer, size_t buflen)
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{
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#ifndef HSCMI_NOTXDMA
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struct sam_dev_s *priv = (struct sam_dev_s *)dev;
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uint32_t paddr;
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uint32_t maddr;
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uint32_t regval;
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unsigned int blocksize;
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unsigned int nblocks;
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unsigned int offset;
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unsigned int i;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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DEBUGASSERT(((uint32_t)buffer & 3) == 0);
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/* Physical address of the HSCMI TDR registr */
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/* How many blocks? That should have been saved by the sam_blocksetup()
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* method earlier.
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*/
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#ifdef HSCMI_FIFODMA
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paddr = hsmci_physregaddr(priv, SAM_HSMCI_FIFO_OFFSET);
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#else
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paddr = hsmci_physregaddr(priv, SAM_HSMCI_TDR_OFFSET);
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#endif
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maddr = sam_physramaddr((uintptr_t)buffer);
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regval = sam_getreg(priv, SAM_HSMCI_BLKR_OFFSET);
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nblocks = ((regval & HSMCI_BLKR_BCNT_SHIFT) >> HSMCI_BLKR_BCNT_SHIFT);
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blocksize = ((regval & HSMCI_BLKR_BLKLEN_MASK) >> HSMCI_BLKR_BLKLEN_SHIFT);
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DEBUGASSERT(nblocks > 0 && blocksize > 0 && (blocksize & 3) == 0);
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/* Setup register sampling */
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/* Physical address of the HSCMI source register, either the TDR (for
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* single transfers) or the first FIFO register, and the physcal address
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* of the buffer in RAM.
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*/
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offset = (nblocks == 1 ? SAM_HSMCI_TDR_OFFSET : SAM_HSMCI_FIFO_OFFSET);
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paddr = hsmci_physregaddr(priv, offset);
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maddr = sam_physramaddr((uintptr_t)buffer);
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/* Setup register sampling (only works for the case of nblocks == 1) */
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sam_xfrsampleinit(priv);
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sam_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
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/* Configure the TX DMA */
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/* Set DMA for each block */
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sam_dmatxsetup(priv->dma, paddr, maddr, buflen);
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for (i = 0; i < nblocks; i++)
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{
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/* Configure the TX DMA */
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sam_dmatxsetup(priv->dma, paddr, maddr, buflen);
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/* Update addresses for the next block */
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paddr += sizeof(uint32_t);
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maddr += blocksize;
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}
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/* Enable DMA handshaking */
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