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arch: armv7-a: Fix style warnings in mmu.h

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Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2020-11-14 18:14:14 +09:00 committed by Xiang Xiao
parent 4cc38caba9
commit 812257d058
1 changed files with 240 additions and 226 deletions
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466
arch/arm/src/armv7-a/mmu.h
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@ -1,4 +1,4 @@
/************************************************************************************
/************************************************************************************************************
* arch/arm/src/armv7-a/mmu.h
* CP15 MMU register definitions
*
@ -40,14 +40,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_MMU_H
#define __ARCH_ARM_SRC_ARMV7_A_MMU_H
/************************************************************************************
/************************************************************************************************************
* Included Files
************************************************************************************/
************************************************************************************************************/
#include <nuttx/config.h>
@ -57,10 +57,11 @@
# include "chip.h"
#endif /* __ASSEMBLY__ */
/************************************************************************************
/************************************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
************************************************************************************************************/
/* Configuration ********************************************************************************************/
#if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV)
@ -73,7 +74,8 @@
#endif
#endif /* CONFIG_PAGING */
/* MMU CP15 Register Bit Definitions ************************************************/
/* MMU CP15 Register Bit Definitions ************************************************************************/
/* Reference: Cortex-A5™ MPCore Paragraph 6.7, "MMU software accessible registers." */
/* TLB Type Register TLB Type Register
@ -84,9 +86,10 @@
*/
/* System Control Register (SCTLR). see cstlr.h */
/* Non-secure Access Control Register (NSACR). See cstlr.h */
/* Translation Table Base Register 0 (TTBR0)*/
/* Translation Table Base Register 0 (TTBR0) */
#define TTBR0_IRGN1 (1 << 0) /* Bit 0: Inner cacheability IRGN[1] (MP extensions) */
#define TTBR0_C (1 << 0) /* Bit 0: Inner cacheability for table walk */
@ -94,15 +97,17 @@
/* Bit 2: Reserved */
#define TTBR0_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */
#define TTBR0_RGN_MASK (3 << TTBR0_RGN_SHIFT)
# define TTBR0_RGN_NONE (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */
# define TTBR0_RGN_WBWA (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
# define TTBR0_RGN_WT (2 << TTBR0_RGN_SHIFT) /* Write-Through */
# define TTBR0_RGN_WB (3 << TTBR0_RGN_SHIFT) /* Write-Back */
#define TTBR0_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-n: Reserved, n=7-13 */
#define TTBR0_RGN_NONE (0 << TTBR0_RGN_SHIFT) /* Non-cacheable */
#define TTBR0_RGN_WBWA (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
#define TTBR0_RGN_WT (2 << TTBR0_RGN_SHIFT) /* Write-Through */
#define TTBR0_RGN_WB (3 << TTBR0_RGN_SHIFT) /* Write-Back */
#define TTBR0_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-n: Reserved, n=7-13 */
#define _TTBR0_LOWER(n) (0xffffffff << (n))
/* Bits (n+1)-31: Translation table base 0 */
/* Bits (n+1)-31: Translation table base 0 */
#define TTBR0_BASE_MASK(n) (~_TTBR0_LOWER(n))
/* Translation Table Base Register 1 (TTBR1) */
@ -113,13 +118,14 @@
/* Bit 2: Reserved */
#define TTBR1_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */
#define TTBR1_RGN_MASK (3 << TTBR1_RGN_SHIFT)
# define TTBR1_RGN_NONE (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */
# define TTBR1_RGN_WBWA (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
# define TTBR1_RGN_WT (2 << TTBR1_RGN_SHIFT) /* Write-Through */
# define TTBR1_RGN_WB (3 << TTBR1_RGN_SHIFT) /* Write-Back */
#define TTBR1_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-13: Reserved */
#define TTBR1_RGN_NONE (0 << TTBR1_RGN_SHIFT) /* Non-cacheable */
#define TTBR1_RGN_WBWA (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
#define TTBR1_RGN_WT (2 << TTBR1_RGN_SHIFT) /* Write-Through */
#define TTBR1_RGN_WB (3 << TTBR1_RGN_SHIFT) /* Write-Back */
#define TTBR1_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-13: Reserved */
#define TTBR1_BASE_SHIFT (14) /* Bits 14-31: Translation table base 1 */
#define TTBR1_BASE_MASK (0xffffc000)
@ -127,14 +133,14 @@
#define TTBCR_N_SHIFT (0) /* Bits 0-2: Boundary size of TTBR0 */
#define TTBCR_N_MASK (7 << TTBCR_N_SHIFT)
# define TTBCR_N_16KB (0 << TTBCR_N_SHIFT) /* Reset value */
# define TTBCR_N_8KB (1 << TTBCR_N_SHIFT)
# define TTBCR_N_4KB (2 << TTBCR_N_SHIFT)
# define TTBCR_N_2KB (3 << TTBCR_N_SHIFT)
# define TTBCR_N_1KB (4 << TTBCR_N_SHIFT)
# define TTBCR_N_512B (5 << TTBCR_N_SHIFT)
# define TTBCR_N_256B (6 << TTBCR_N_SHIFT)
# define TTBCR_N_128B (7 << TTBCR_N_SHIFT)
#define TTBCR_N_16KB (0 << TTBCR_N_SHIFT) /* Reset value */
#define TTBCR_N_8KB (1 << TTBCR_N_SHIFT)
#define TTBCR_N_4KB (2 << TTBCR_N_SHIFT)
#define TTBCR_N_2KB (3 << TTBCR_N_SHIFT)
#define TTBCR_N_1KB (4 << TTBCR_N_SHIFT)
#define TTBCR_N_512B (5 << TTBCR_N_SHIFT)
#define TTBCR_N_256B (6 << TTBCR_N_SHIFT)
#define TTBCR_N_128B (7 << TTBCR_N_SHIFT)
/* Bit 3: Reserved */
#define TTBCR_PD0 (1 << 4) /* Bit 4: Translation table walk on a TLB miss w/TTBR0 */
#define TTBCR_PD1 (1 << 5) /* Bit 5: Translation table walk on a TLB miss w/TTBR1 */
@ -144,9 +150,9 @@
#define DACR_SHIFT(n) ((n) << 1) /* Domain n, n=0-15 */
#define DACR_MASK(n) (3 << DACR_SHIFT(n))
# define DACR_NONE(n) (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */
# define DACR_CLIENT(n) (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */
# define DACR_MANAGER(n) (3 << DACR_SHIFT(n)) /* Accesses are not checked */
#define DACR_NONE(n) (0 << DACR_SHIFT(n)) /* Any access generates a domain fault */
#define DACR_CLIENT(n) (1 << DACR_SHIFT(n)) /* Accesses checked against permissions TLB */
#define DACR_MANAGER(n) (3 << DACR_SHIFT(n)) /* Accesses are not checked */
/* Data Fault Status Register (DFSR) */
@ -222,6 +228,7 @@
#define TLB_VA_MASK (0xfffff000) /* Bits 12-31: Virtual address */
/* Primary Region Remap Register (PRRR) */
/* Normal Memory Remap Register (NMRR) */
/* TLB Hitmap Register (TLBHR) */
@ -234,7 +241,8 @@
/* Context ID Register (CONTEXTIDR). See cstlr.h */
/* Translation Table Definitions ****************************************************/
/* Translation Table Definitions ****************************************************************************/
/* Hardware translation table definitions. Only the "short descriptor format" is
* supported.
*
@ -245,11 +253,11 @@
#define PMD_TYPE_SHIFT (0) /* Bits: 1:0: Type of mapping */
#define PMD_TYPE_MASK (3 << PMD_TYPE_SHIFT)
# define PMD_TYPE_FAULT (0 << PMD_TYPE_SHIFT) /* None */
# define PMD_TYPE_PTE (1 << PMD_TYPE_SHIFT) /* Page table */
# define PMD_TYPE_SECT (2 << PMD_TYPE_SHIFT) /* Section or supersection */
# define PMD_TYPE_PXN (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */
/* Bits 2-31: Depend on the mapping type */
#define PMD_TYPE_FAULT (0 << PMD_TYPE_SHIFT) /* None */
#define PMD_TYPE_PTE (1 << PMD_TYPE_SHIFT) /* Page table */
#define PMD_TYPE_SECT (2 << PMD_TYPE_SHIFT) /* Section or supersection */
#define PMD_TYPE_PXN (3 << PMD_TYPE_SHIFT) /* PXN Section or supersection */
/* Bits 2-31: Depend on the mapping type */
/* Level 1 Fault Translation Table Format.
*
@ -271,7 +279,7 @@
/* Bit 4: Should be zero (SBZ) */
#define PMD_PTE_DOM_SHIFT (5) /* Bits 5-8: Domain */
#define PMD_PTE_DOM_MASK (15 << PMD_PTE_DOM_SHIFT)
# define PMD_PTE_DOM(n) ((n) << PMD_PTE_DOM_SHIFT)
#define PMD_PTE_DOM(n) ((n) << PMD_PTE_DOM_SHIFT)
/* Bit 9: Not implemented */
#define PMD_PTE_PADDR_MASK (0xfffffc00) /* Bits 10-31: Page table base address */
@ -300,13 +308,13 @@
#define PMD_SECT_XN (1 << 4) /* Bit 4: Execute-never bit */
#define PMD_SECT_DOM_SHIFT (5) /* Bits 5-8: Domain */
#define PMD_SECT_DOM_MASK (15 << PMD_SECT_DOM_SHIFT)
# define PMD_SECT_DOM(n) ((n) << PMD_SECT_DOM_SHIFT)
#define PMD_SECT_DOM(n) ((n) << PMD_SECT_DOM_SHIFT)
/* Bit 9: Implementation defined */
#define PMD_SECT_AP_SHIFT (10) /* Bits 10-11: Access Permissions bits AP[0:1] */
#define PMD_SECT_AP_MASK (3 << PMD_SECT_AP_SHIFT)
# define PMD_SECT_AP0 (1 << PMD_SECT_AP_SHIFT) /* AP[0]: Access permission bit 0 */
# define PMD_SECT_AP1 (2 << PMD_SECT_AP_SHIFT) /* AP[1]: Access permission bit 1 */
#define PMD_SECT_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */
#define PMD_SECT_AP0 (1 << PMD_SECT_AP_SHIFT) /* AP[0]: Access permission bit 0 */
#define PMD_SECT_AP1 (2 << PMD_SECT_AP_SHIFT) /* AP[1]: Access permission bit 1 */
#define PMD_SECT_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */
#define PMD_SECT_TEX_MASK (7 << PMD_SECT_TEX_SHIFT)
#define PMD_SECT_AP2 (1 << 15) /* Bit 15: AP[2]: Access permission bit 2 */
#define PMD_SECT_S (1 << 16) /* Bit 16: Shareable bit */
@ -402,26 +410,29 @@
#define PTE_TYPE_SHIFT (0) /* Bits: 1:0: Type of mapping */
#define PTE_TYPE_MASK (3 << PTE_TYPE_SHIFT)
# define PTE_TYPE_FAULT (0 << PTE_TYPE_SHIFT) /* None */
# define PTE_TYPE_LARGE (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */
# define PTE_TYPE_SMALL (2 << PTE_TYPE_SHIFT) /* 4Kb of memory */
#define PTE_B (1 << 2) /* Bit 2: Bufferable bit */
#define PTE_C (1 << 3) /* Bit 3: Cacheable bit */
#define PTE_AP_SHIFT (4) /* Bits 4-5: Access Permissions bits AP[0:1] */
#define PTE_TYPE_FAULT (0 << PTE_TYPE_SHIFT) /* None */
#define PTE_TYPE_LARGE (1 << PTE_TYPE_SHIFT) /* 64Kb of memory */
#define PTE_TYPE_SMALL (2 << PTE_TYPE_SHIFT) /* 4Kb of memory */
#define PTE_B (1 << 2) /* Bit 2: Bufferable bit */
#define PTE_C (1 << 3) /* Bit 3: Cacheable bit */
#define PTE_AP_SHIFT (4) /* Bits 4-5: Access Permissions bits AP[0:1] */
#define PTE_AP_MASK (3 << PTE_AP_SHIFT)
# define PTE_AP0 (1 << PTE_AP_SHIFT) /* AP[0]: Access permission bit 0 */
# define PTE_AP1 (2 << PTE_AP_SHIFT) /* AP[1]: Access permission bit 1 */
/* Bits 6-8: Depend on entry type */
#define PTE_AP2 (1 << 9) /* Bit 9: AP[2]: Access permission bit 2 */
#define PTE_S (1 << 10) /* Bit 10: Shareable bit */
#define PTE_NG (1 << 11) /* Bit 11: Not global bit. */
/* Bits 12-31:Depend on entry type */
#define PTE_AP0 (1 << PTE_AP_SHIFT) /* AP[0]: Access permission bit 0 */
#define PTE_AP1 (2 << PTE_AP_SHIFT) /* AP[1]: Access permission bit 1 */
/* Bits 6-8: Depend on entry type */
#define PTE_AP2 (1 << 9) /* Bit 9: AP[2]: Access permission bit 2 */
#define PTE_S (1 << 10) /* Bit 10: Shareable bit */
#define PTE_NG (1 << 11) /* Bit 11: Not global bit. */
/* Bits 12-31:Depend on entry type */
/* Large page -- 64Kb */
/* Bits: 1:0: Type of mapping */
/* Bit 2: Bufferable bit */
/* Bit 3: Cacheable bit */
/* Bits 4-5: Access Permissions bits AP[0:1] */
/* Bits: 1:0: Type of mapping
* Bit 2: Bufferable bit
* Bit 3: Cacheable bit
* Bits 4-5: Access Permissions bits AP[0:1]
*/
#define PTE_LARGE_TEX_SHIFT (12) /* Bits 12-14: Memory region attribute bits */
#define PTE_LARGE_TEX_MASK (7 << PTE_LARGE_TEX_SHIFT)
#define PTE_LARGE_XN (1 << 15) /* Bit 15: Execute-never bit */
@ -430,10 +441,12 @@
/* Small page -- 4Kb */
/* Bits: 1:0: Type of mapping */
/* Bit 2: Bufferable bit */
/* Bit 3: Cacheable bit */
/* Bits 4-5: Access Permissions bits AP[0:1] */
/* Bits: 1:0: Type of mapping
* Bit 2: Bufferable bit
* Bit 3: Cacheable bit
* Bits 4-5: Access Permissions bits AP[0:1]
*/
#define PTE_SMALL_FLAG_MASK (0x0000003f) /* Bits 0-11: MMU flags (mostly) */
#define PTE_SMALL_PADDR_MASK (0xfffff000) /* Bits 12-31: Small page base address, PA[31:12] */
@ -626,7 +639,7 @@
#define PGTABLE_SIZE 0x00004000
/* Virtual Page Table Location ******************************************************/
/* Virtual Page Table Location ******************************************************************************/
#ifdef CONFIG_PAGING
/* Check if the virtual address of the page table has been defined. It
@ -648,7 +661,7 @@
#endif /* PGTABLE_BASE_VADDR */
/* MMU flags ************************************************************************/
/* MMU flags ************************************************************************************************/
/* Create some friendly definitions to handle page table entries */
@ -670,7 +683,7 @@
#define PG_L1_PADDRMASK PMD_SECT_PADDR_MASK
/* Addresses of Memory Regions ******************************************************/
/* Addresses of Memory Regions ******************************************************************************/
/* We position the locked region PTEs at an offset into the first
* L2 page table. The L1 entry points to an 1Mb aligned virtual
@ -720,7 +733,7 @@
#define PG_L2_DATA_VADDR (PG_L2_LOCKED_VADDR + PG_L2_TEXT_SIZE)
#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
/* Page Table Info ******************************************************************/
/* Page Table Info ******************************************************************************************/
/* The number of pages in the in the page table (PG_PGTABLE_NPAGES). We
* position the page table PTEs just after the data section PTEs.
@ -734,7 +747,7 @@
#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
/* Vector Mapping *******************************************************************/
/* Vector Mapping *******************************************************************************************/
/* One page is required to map the vector table. The vector table could lie
* at virtual address zero (or at the start of RAM which is aliased to address
@ -788,7 +801,7 @@
# error "Logic missing for high vectors in this case"
#endif
/* Page Usage ***********************************************************************/
/* Page Usage ***********************************************************************************************/
/* This is the total number of pages used in the text/data mapping: */
@ -803,7 +816,7 @@
# error "Total pages required exceeds RAM size"
#endif
/* Page Management ******************************************************************/
/* Page Management ******************************************************************************************/
/* For page management purposes, the following summarize the "heap" of
* free pages, operations on free pages and the L2 page table.
@ -868,9 +881,9 @@
#endif /* CONFIG_PAGING */
/************************************************************************************
/************************************************************************************************************
* Public Types
************************************************************************************/
************************************************************************************************************/
#ifndef __ASSEMBLY__
/* struct section_mapping_s describes the L1 mapping of a large region of memory
@ -888,13 +901,13 @@ struct section_mapping_s
};
#endif
/************************************************************************************
/************************************************************************************************************
* Assembly Macros
************************************************************************************/
************************************************************************************************************/
#ifdef __ASSEMBLY__
/************************************************************************************
/************************************************************************************************************
* Name: cp15_disable_mmu
*
* Description:
@ -903,15 +916,15 @@ struct section_mapping_s
* Input Parameters:
* None
*
************************************************************************************/
************************************************************************************************************/
.macro cp15_disable_mmu, scratch
mrc p15, 0, \scratch, c1, c0, 0
bic \scratch, \scratch, #1
mcr p15, 0, \scratch, c1, c0, 0
.endm
.macro cp15_disable_mmu, scratch
mrc p15, 0, \scratch, c1, c0, 0
bic \scratch, \scratch, #1
mcr p15, 0, \scratch, c1, c0, 0
.endm
/************************************************************************************
/************************************************************************************************************
* Name: cp15_invalidate_tlbs
*
* Description:
@ -925,13 +938,13 @@ struct section_mapping_s
* Input Parameters:
* None
*
************************************************************************************/
************************************************************************************************************/
.macro cp15_invalidate_tlbs, scratch
mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */
.endm
.macro cp15_invalidate_tlbs, scratch
mcr p15, 0, \scratch, c8, c7, 0 /* TLBIALL */
.endm
/************************************************************************************
/************************************************************************************************************
* Name: cp15_invalidate_tlb_bymva
*
* Description:
@ -940,20 +953,20 @@ struct section_mapping_s
* Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************/
************************************************************************************************************/
.macro cp15_invalidate_tlb_bymva, vaddr
dsb
.macro cp15_invalidate_tlb_bymva, vaddr
dsb
#if defined(CONFIG_ARCH_CORTEXA8)
mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */
mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */
#else
mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */
mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */
#endif
dsb
isb
.endm
dsb
isb
.endm
/************************************************************************************
/************************************************************************************************************
* Name: cp15_wrdacr
*
* Description:
@ -962,21 +975,21 @@ struct section_mapping_s
* Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************/
************************************************************************************************************/
.macro cp15_wrdacr, dacr
mcr p15, 0, \dacr, c3, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
.endm
.macro cp15_wrdacr, dacr
mcr p15, 0, \dacr, c3, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
.endm
/************************************************************************************
/************************************************************************************************************
* Name: cp15_wrttb
*
* Description:
@ -989,23 +1002,23 @@ struct section_mapping_s
* Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************/
************************************************************************************************************/
.macro cp15_wrttb, ttb, scratch
mcr p15, 0, \ttb, c2, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
mov \scratch, #0x0
mcr p15, 0, \scratch, c2, c0, 2
.endm
.macro cp15_wrttb, ttb, scratch
mcr p15, 0, \ttb, c2, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
mov \scratch, #0x0
mcr p15, 0, \scratch, c2, c0, 2
.endm
/************************************************************************************
/************************************************************************************************************
* Name: pg_l2map
*
* Description:
@ -1013,11 +1026,11 @@ struct section_mapping_s
* written. This macro is used when CONFIG_PAGING is enable. This case,
* it is used as follows:
*
* ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table
* ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address
* ldr r2, =CONFIG_PAGING_NLOCKED <-- number of pages
* ldr r3, =MMUFLAGS <-- L2 MMU flags
* pg_l2map r0, r1, r2, r3, r4
* ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table
* ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address
* ldr r2, =CONFIG_PAGING_NLOCKED <-- number of pages
* ldr r3, =MMUFLAGS <-- L2 MMU flags
* pg_l2map r0, r1, r2, r3, r4
*
* Input Parameters:
* l2 - Physical or virtual start address in the L2 page table, depending
@ -1038,44 +1051,44 @@ struct section_mapping_s
* - The L2 page tables have been zeroed prior to calling this function
* - pg_l1span has been called to initialize the L1 table.
*
************************************************************************************/
************************************************************************************************************/
#ifdef CONFIG_PAGING
.macro pg_l2map, l2, ppage, npages, mmuflags, tmp
b 2f
.macro pg_l2map, l2, ppage, npages, mmuflags, tmp
b 2f
1:
/* Write the one L2 entries. First, get tmp = (ppage | mmuflags),
* the value to write into the L2 PTE
*/
/* Write the one L2 entries. First, get tmp = (ppage | mmuflags),
* the value to write into the L2 PTE
*/
orr \tmp, \ppage, \mmuflags
orr \tmp, \ppage, \mmuflags
/* Write value into table at the current table address
* (and increment the L2 page table address by 4)
*/
/* Write value into table at the current table address
* (and increment the L2 page table address by 4)
*/
str \tmp, [\l2], #4
str \tmp, [\l2], #4
/* Update the physical address that will correspond to the next
* table entry.
*/
/* Update the physical address that will correspond to the next
* table entry.
*/
add \ppage, \ppage, #CONFIG_PAGING_PAGESIZE
add \ppage, \ppage, #CONFIG_PAGING_PAGESIZE
/* Decrement the number of pages written */
/* Decrement the number of pages written */
sub \npages, \npages, #1
sub \npages, \npages, #1
2:
/* Check if all of the pages have been written. If not, then
* loop and write the next PTE.
*/
/* Check if all of the pages have been written. If not, then
* loop and write the next PTE.
*/
cmp \npages, #0
bgt 1b
.endm
cmp \npages, #0
bgt 1b
.endm
#endif /* CONFIG_PAGING */
/************************************************************************************
/************************************************************************************************************
* Name: pg_l1span
*
* Description:
@ -1083,12 +1096,12 @@ struct section_mapping_s
* entries will be written as many as needed to span npages. This macro is
* used when CONFIG_PAGING is enable. In this case, it is used as follows:
*
* ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table
* ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table
* ldr r2, =PG_PGTABLE_NPAGES <-- Total number of pages
* ldr r3, =PG_PGTABLE_NPAGE1 <-- Number of pages in the first PTE
* ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags
* pg_l1span r0, r1, r2, r3, r4, r4
* ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table
* ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table
* ldr r2, =PG_PGTABLE_NPAGES <-- Total number of pages
* ldr r3, =PG_PGTABLE_NPAGE1 <-- Number of pages in the first PTE
* ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags
* pg_l1span r0, r1, r2, r3, r4, r4
*
* Input Parameters (unmodified unless noted):
* l1 - Physical or virtual address in the L1 table to begin writing (modified)
@ -1111,56 +1124,56 @@ struct section_mapping_s
* - The MMU is not yet enabled
* - The L2 page tables have been zeroed prior to calling this function
*
************************************************************************************/
************************************************************************************************************/
#ifdef CONFIG_PAGING
.macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp
b 2f
.macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp
b 2f
1:
/* Write the L1 table entry that refers to this (unmapped) small page
* table.
*
* tmp = (l2table | mmuflags), the value to write into the page table
*/
/* Write the L1 table entry that refers to this (unmapped) small page
* table.
*
* tmp = (l2table | mmuflags), the value to write into the page table
*/
orr \tmp, \l2, \mmuflags
orr \tmp, \l2, \mmuflags
/* Write the value into the L1 table at the correct offset.
* (and increment the L1 table address by 4)
*/
/* Write the value into the L1 table at the correct offset.
* (and increment the L1 table address by 4)
*/
str \tmp, [\l1], #4
str \tmp, [\l1], #4
/* Update the L2 page table address for the next L1 table entry. */
/* Update the L2 page table address for the next L1 table entry. */
add \l2, \l2, #PT_SIZE /* Next L2 page table start address */
add \l2, \l2, #PT_SIZE /* Next L2 page table start address */
/* Update the number of pages that we have account for (with
* non-mappings). NOTE that the first page may have fewer than
* the maximum entries per page table.
*/
/* Update the number of pages that we have account for (with
* non-mappings). NOTE that the first page may have fewer than
* the maximum entries per page table.
*/
sub \npages, \npages, \ppage
mov \ppage, #PTE_NPAGES
sub \npages, \npages, \ppage
mov \ppage, #PTE_NPAGES
2:
/* Check if all of the pages have been written. If not, then
* loop and write the next L1 entry.
*/
/* Check if all of the pages have been written. If not, then
* loop and write the next L1 entry.
*/
cmp \npages, #0
bgt 1b
.endm
cmp \npages, #0
bgt 1b
.endm
#endif /* CONFIG_PAGING */
#endif /* __ASSEMBLY__ */
/************************************************************************************
/************************************************************************************************************
* Inline Functions
************************************************************************************/
************************************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/************************************************************************************************************
* Name: cp15_disable_mmu
*
* Description:
@ -1169,7 +1182,7 @@ struct section_mapping_s
* Input Parameters:
* None
*
************************************************************************************/
************************************************************************************************************/
static inline void cp15_disable_mmu(void)
{
@ -1184,7 +1197,7 @@ static inline void cp15_disable_mmu(void)
);
}
/************************************************************************************
/************************************************************************************************************
* Name: cp15_invalidate_tlbs
*
* Description:
@ -1198,7 +1211,7 @@ static inline void cp15_disable_mmu(void)
* Input Parameters:
* None
*
************************************************************************************/
************************************************************************************************************/
static inline void cp15_invalidate_tlbs(void)
{
@ -1211,7 +1224,7 @@ static inline void cp15_invalidate_tlbs(void)
);
}
/************************************************************************************
/************************************************************************************************************
* Name: cp15_invalidate_tlb_bymva
*
* Description:
@ -1220,7 +1233,7 @@ static inline void cp15_invalidate_tlbs(void)
* Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************/
************************************************************************************************************/
static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
{
@ -1240,7 +1253,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
);
}
/************************************************************************************
/************************************************************************************************************
* Name: cp15_wrdacr
*
* Description:
@ -1249,7 +1262,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
* Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************/
************************************************************************************************************/
static inline void cp15_wrdacr(unsigned int dacr)
{
@ -1270,7 +1283,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
);
}
/************************************************************************************
/************************************************************************************************************
* Name: cp15_wrttb
*
* Description:
@ -1283,7 +1296,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
* Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************/
************************************************************************************************************/
static inline void cp15_wrttb(unsigned int ttb)
{
@ -1306,7 +1319,7 @@ static inline void cp15_wrttb(unsigned int ttb)
);
}
/*************************************************************************************
/************************************************************************************************************
* Name: mmu_l1_getentry
*
* Description:
@ -1315,12 +1328,12 @@ static inline void cp15_wrttb(unsigned int ttb)
* Input Parameters:
* vaddr - The virtual address to be mapped.
*
************************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
{
uint32_t *l1table = (uint32_t*)PGTABLE_BASE_VADDR;
uint32_t *l1table = (uint32_t *)PGTABLE_BASE_VADDR;
uint32_t index = vaddr >> 20;
/* Return the address of the page table entry */
@ -1329,7 +1342,7 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
}
#endif
/*************************************************************************************
/************************************************************************************************************
* Name: mmu_l2_getentry
*
* Description:
@ -1340,12 +1353,12 @@ static inline uint32_t mmu_l1_getentry(uint32_t vaddr)
* l2vaddr - The virtual address of the beginning of the L2 page table
* vaddr - The virtual address to be mapped.
*
************************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
{
uint32_t *l2table = (uint32_t*)l2vaddr;
uint32_t *l2table = (uint32_t *)l2vaddr;
uint32_t index;
/* The table divides a 1Mb address space up into 256 entries, each
@ -1363,13 +1376,13 @@ static inline uint32_t mmu_l2_getentry(uint32_t l2vaddr, uint32_t vaddr)
#endif /* __ASSEMBLY__ */
/************************************************************************************
/************************************************************************************************************
* Public Data
************************************************************************************/
************************************************************************************************************/
/************************************************************************************
/************************************************************************************************************
* Public Function Prototypes
************************************************************************************/
************************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -1380,7 +1393,7 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/************************************************************************************************************
* Name: mmu_l1_setentry
*
* Description:
@ -1394,13 +1407,13 @@ extern "C"
* boundary
* mmuflags - The MMU flags to use in the mapping.
*
************************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
#endif
/****************************************************************************
/************************************************************************************************************
* Name: mmu_l1_restore
*
* Description:
@ -1411,13 +1424,13 @@ void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags);
* vaddr - A virtual address to be mapped
* l1entry - The value to write into the page table entry
*
****************************************************************************/
************************************************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
#endif
/************************************************************************************
/************************************************************************************************************
* Name: mmu_l1_clrentry
*
* Description:
@ -1427,13 +1440,13 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
* Input Parameters:
* vaddr - A virtual address within the L1 address region to be unmapped.
*
************************************************************************************/
************************************************************************************************************/
#if !defined (CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
# define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
#endif
/****************************************************************************
/************************************************************************************************************
* Name: mmu_l2_setentry
*
* Description:
@ -1448,14 +1461,14 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
* address boundary
* mmuflags - The MMU flags to use in the mapping.
*
****************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
uint32_t mmuflags);
#endif
/****************************************************************************
/************************************************************************************************************
* Name: mmu_l1_map_region
*
* Description:
@ -1465,13 +1478,13 @@ void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
* Input Parameters:
* mapping - Describes the mapping to be performed.
*
****************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_map_region(const struct section_mapping_s *mapping);
#endif
/****************************************************************************
/************************************************************************************************************
* Name: mmu_l1_map_regions
*
* Description:
@ -1482,13 +1495,14 @@ void mmu_l1_map_region(const struct section_mapping_s *mapping);
* mappings - Describes the array of mappings to be performed.
* count - The number of mappings to be performed.
*
****************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_l1_map_regions(const struct section_mapping_s *mappings,
size_t count);
#endif
/****************************************************************************
/************************************************************************************************************
* Name: mmu_invalidate_region
*
* Description:
@ -1498,7 +1512,7 @@ void mmu_l1_map_regions(const struct section_mapping_s *mappings,
* vaddr - The beginning of the region to invalidate.
* size - The size of the region in bytes to be invalidated.
*
****************************************************************************/
************************************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
void mmu_invalidate_region(uint32_t vstart, size_t size);