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style: fix multiple style issues and remove unused

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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko 2023-09-10 15:20:43 +03:00 committed by Xiang Xiao
parent f06c509f9e
commit 816cb3cfaf
6 changed files with 57 additions and 60 deletions
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33
arch/arm/src/armv7-m/mpu.h
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@ -94,7 +94,7 @@
#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */
#define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT)
# define MPU_RASR_SIZE_LOG2(n) ((n-1) << MPU_RASR_SIZE_SHIFT)
# define MPU_RASR_SIZE_LOG2(n) ((n - 1) << MPU_RASR_SIZE_SHIFT)
#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */
#define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT)
@ -115,7 +115,7 @@
# define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */
# define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */
# define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */
# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT)
# define MPU_RASR_TEX_BB(bb) ((4 | (bb)) << MPU_RASR_TEX_SHIFT)
# define MPU_RASR_CP_NC (0) /* Non-cacheable */
# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */
# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */
@ -142,7 +142,7 @@
#if defined(CONFIG_MPU_RESET)
void mpu_reset(void);
#else
# define mpu_reset() do { } while (0)
# define mpu_reset()
#endif
/****************************************************************************
@ -157,7 +157,7 @@ void mpu_reset(void);
#if defined(CONFIG_ARM_MPU_EARLY_RESET)
void mpu_early_reset(void);
#else
# define mpu_early_reset() do { } while (0)
# define mpu_early_reset()
#endif
#ifdef CONFIG_ARM_MPU
@ -246,8 +246,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena);
*
****************************************************************************/
void mpu_configure_region(uintptr_t base, size_t size,
uint32_t flags);
void mpu_configure_region(uintptr_t base, size_t size, uint32_t flags);
/****************************************************************************
* Inline Functions
@ -270,9 +269,10 @@ void mpu_configure_region(uintptr_t base, size_t size,
(regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", \
(regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, \
(regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); \
} while (0)
} \
while (0)
#else
# define mpu_showtype() do { } while (0)
# define mpu_showtype()
#endif
/****************************************************************************
@ -294,7 +294,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \
} while (0)
} \
while (0)
/****************************************************************************
* Name: mpu_user_flash
@ -315,7 +316,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
/* Not Shareable */ \
MPU_RASR_AP_RORO /* P:RO U:RO */ \
/* Instruction access */); \
} while (0)
} \
while (0)
/****************************************************************************
* Name: mpu_priv_flash
@ -336,7 +338,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
/* Not Shareable */ \
MPU_RASR_AP_RONO /* P:RO U:None */ \
/* Instruction access */); \
} while (0)
} \
while (0)
/****************************************************************************
* Name: mpu_user_intsram
@ -357,7 +360,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWRW /* P:RW U:RW */ \
/* Instruction access */); \
} while (0)
} \
while (0)
/****************************************************************************
* Name: mpu_priv_intsram
@ -371,14 +375,15 @@ void mpu_configure_region(uintptr_t base, size_t size,
do \
{ \
/* The configure the region */ \
mpu_configure_region(base, size,\
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \
} while (0)
} \
while (0)
/****************************************************************************
* Name: mpu_priv_shmem

2
arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c
View File

@ -71,7 +71,7 @@
#include "esp32c3_clockconfig.h"
#ifdef CONFIG_PM
#include "esp32c3_pm.h"
# include "esp32c3_pm.h"
#endif
#include "espidf_wifi.h"

10
arch/xtensa/src/esp32/esp32_ble.c
View File

@ -41,7 +41,7 @@
#include <nuttx/wireless/bluetooth/bt_uart.h>
#if defined(CONFIG_UART_BTH4)
#include <nuttx/serial/uart_bth4.h>
# include <nuttx/serial/uart_bth4.h>
#endif
#include "esp32_ble_adapter.h"
@ -50,18 +50,10 @@
* Pre-processor Definitions
****************************************************************************/
/* BLE packet buffer max number */
#define BLE_BUF_NUM CONFIG_ESP32_BLE_PKTBUF_NUM
/* BLE packet buffer max size */
#define BLE_BUF_SIZE 1024
/* Low-priority work queue process RX/TX */
#define BLE_WORK LPWORK
/****************************************************************************
* Private Types
****************************************************************************/

12
arch/xtensa/src/esp32/esp32_irq.c
View File

@ -317,7 +317,7 @@ static int esp32_getcpuint(uint32_t intmask)
* that CPU interrupt is available.
*/
bitmask = (1ul << cpuint);
bitmask = 1ul << cpuint;
if ((intset & bitmask) != 0)
{
/* Got it! */
@ -335,7 +335,7 @@ static int esp32_getcpuint(uint32_t intmask)
if (ret >= 0)
{
xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << ret);
}
return ret;
@ -411,7 +411,7 @@ static void esp32_free_cpuint(int cpuint)
/* Mark the CPU interrupt as available */
bitmask = (1ul << cpuint);
bitmask = 1ul << cpuint;
#ifdef CONFIG_SMP
if (up_cpu_index() != 0)
@ -556,7 +556,7 @@ void up_disable_irq(int irq)
}
#endif
xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
xtensa_disable_cpuint(&g_intenable[cpu], 1ul << cpuint);
}
else
{
@ -612,7 +612,7 @@ void up_enable_irq(int irq)
/* Enable the CPU interrupt now for internal CPU. */
xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
}
else
{
@ -956,7 +956,7 @@ uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++)
{
mask = (1 << bit);
mask = 1 << bit;
if ((cpuints & mask) != 0)
{
/* Extract the IRQ number from the mapping table */

2
include/nuttx/signal.h
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@ -638,7 +638,7 @@ int nxsig_notification(pid_t pid, FAR struct sigevent *event,
#ifdef CONFIG_SIG_EVTHREAD
void nxsig_cancel_notification(FAR struct sigwork_s *work);
#else
#define nxsig_cancel_notification(work) (void)(work)
# define nxsig_cancel_notification(work) (void)(work)
#endif
#ifdef __cplusplus