ARM stack check logic; ARM no-console build fixes; Nucleus-2G updates

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3760 42af7a65-404d-4744-a932-0658087f49c3

configs/nucleus2g/include/board.h

@@ -198,6 +198,13 @@ enum lpc17_ledstate_e
 };
 #endif
 
+enum output_state
+{
+  RELAY_OPEN   = 0,
+  RELAY_CLOSED = 1,
+  RELAY_TOGGLE = 2,
+};
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/
@@ -218,7 +225,7 @@ extern "C" {
  *
  * Description:
  *   All LPC17xx architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
+ *   is called early in the initialization -- after all memory has been configured
  *   and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
@@ -238,6 +245,22 @@ EXTERN void lpc17_led1(enum lpc17_ledstate_e state);
 EXTERN void lpc17_led2(enum lpc17_ledstate_e state);
 #endif
 
+/************************************************************************************
+ * Name: nucleus_bms_relay 1-4
+ *
+ * Description:
+ * once booted these functions control the 4 isolated FET outputs from the
+ * master BMS controller
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BOARD_NUCLEUS2G_BMS
+EXTERN void nucleus_bms_relay1(enum output_state state);
+EXTERN void nucleus_bms_relay2(enum output_state state);
+EXTERN void nucleus_bms_relay3(enum output_state state);
+EXTERN void nucleus_bms_relay4(enum output_state state);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

configs/nucleus2g/src/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # configs/nucleus2g/src/Makefile
 #
-#   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 #
 # Redistribution and use in source and binary forms, with or without

configs/nucleus2g/src/nucleus2g_internal.h

@@ -120,6 +120,11 @@
 
 #define NUCLEUS2G_MMCSD_CS           (GPIO_OUTPUT | GPIO_VALUE_ONE  |  GPIO_PORT0 | GPIO_PIN16)
 
+#define NUCLEUS_BMS_RELAY1  (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN20)
+#define NUCLEUS_BMS_RELAY2  (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN21)
+#define NUCLEUS_BMS_RELAY3  (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN22)
+#define NUCLEUS_BMS_RELAY4  (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN23)
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -144,6 +149,8 @@
 
 extern void weak_function lpc17_sspinitialize(void);
 
+extern void up_relayinit(void);
+
 #endif /* __ASSEMBLY__ */
 #endif /* _CONFIGS_NUCLEUS2G_SRC_NUCLEUS2G_INTERNAL_H */
 

configs/nucleus2g/src/up_boot.c

@@ -67,7 +67,7 @@
  *
  * Description:
  *   All LPC17xx architectures must provide the following entry point.  This entry point
- *   is called early in the intitialization -- after all memory has been configured
+ *   is called early in the initialization -- after all memory has been configured
  *   and mapped but before any devices have been initialized.
  *
  ************************************************************************************/
@@ -106,4 +106,10 @@ void lpc17_boardinitialize(void)
 #ifdef CONFIG_ARCH_LEDS
   up_ledinit();
 #endif
+
+  /* Configure the relay outptus for use on the BMS master board */
+
+#ifdef CONFIG_ARCH_BOARD_NUCLEUS2G_BMS
+  up_relayinit();
+#endif
 }

configs/nucleus2g/tools/olimex.cfg

@@ -59,3 +59,4 @@ flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 80000 calc_c
 
 # 4MHz / 6 = 666kHz, so use 500
 jtag_khz 100
+

configs/nucleus2g/tools/oocd.sh

@@ -1,16 +1,23 @@
 #!/bin/sh
 
 TOPDIR=$1
+CFGFILE=$2
 USAGE="$0 <TOPDIR> [-d]"
+
 if [ -z "${TOPDIR}" ]; then
 	echo "Missing argument"
 	echo $USAGE
 	exit 1
 fi
 
+if [ -z "${CFGFILE}" ]; then
+	echo "Using olimex.cfg"
+    CFGFILE=olimex.cfg
+fi
+
 OPENOCD_PATH="/cygdrive/c/OpenOCD/openocd-0.4.0/src"
 OPENOCD_EXE=openocd.exe
-OPENOCD_CFG="${TOPDIR}/configs/nucleus2g/tools/olimex.cfg"
+OPENOCD_CFG="${TOPDIR}/configs/nucleus2g/tools/${CFGFILE}"
 OPENOCD_ARGS="-f `cygpath -w ${OPENOCD_CFG}`"
 
 if [ "X$2" = "X-d" ]; then

configs/nucleus2g/tools/scarab.cfg

@@ -0,0 +1,63 @@
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_device_desc "usbScarab A"
+ft2232_layout "olimex-jtag"
+ft2232_vid_pid 0x0403 0xbbe0
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc1768
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+
+# REVISIT is there any good reason to have this reset-init event handler??
+# Normally they should set up (board-specific) clocking then probe the flash...
+$_TARGETNAME configure -event reset-init {
+	# Force NVIC.VTOR to point to flash at 0 ...
+	# WHY?  This is it's reset value; we run right after reset!!
+	mwb 0xE000ED08 0x00
+}
+
+# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
+# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 100
+#jtag_rclk 1000
+