tiva/cc13x2_cc26x2: Fix nxstyle errors
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h, arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_smph.h, arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h, arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h, arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_smph.h: * Fix nxstyle errors.
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d523757d4a
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@ -1,10 +1,11 @@
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/********************************************************************************************************************
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/****************************************************************************
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* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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* Technical content derives from a TI header file that has a compatible
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* BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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@ -36,24 +37,24 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI4_AUX_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI4_AUX_H
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/********************************************************************************************************************
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/****************************************************************************
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* Included Files
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********************************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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#include "hardware/tiva_ddi.h"
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/********************************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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********************************************************************************************************************/
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****************************************************************************/
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/* ADI3 AUX Register Offsets ****************************************************************************************/
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/* ADI3 AUX Register Offsets ************************************************/
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#define TIVA_ADI4_AUX_MUX0_OFFSET 0x0000
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#define TIVA_ADI4_AUX_MUX1_OFFSET 0x0001
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@ -68,7 +69,7 @@
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#define TIVA_ADI4_AUX_ADCREF1_OFFSET 0x000b /* ADC Reference 1 */
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#define TIVA_ADI4_AUX_LPMBIAS_OFFSET 0x000e
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/* ADI3 AUX Register Addresses **************************************************************************************/
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/* ADI3 AUX Register Addresses **********************************************/
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#define TIVA_ADI4_AUX_MUX0 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX0_OFFSET)
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#define TIVA_ADI4_AUX_MUX1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX1_OFFSET)
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@ -83,7 +84,9 @@
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#define TIVA_ADI4_AUX_ADCREF1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF1_OFFSET)
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#define TIVA_ADI4_AUX_LPMBIAS (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_LPMBIAS_OFFSET)
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/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
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/* Offsets may also be used in conjunction with access as described in
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*cc13x2_cc26x2_ddi.h
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*/
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#define TIVA_ADI4_AUX_DIR (TIVA_AUX_ADI4_BASE + TIVA_DDI_DIR_OFFSET)
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#define TIVA_ADI4_AUX_SET (TIVA_AUX_ADI4_BASE + TIVA_DDI_SET_OFFSET)
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@ -92,7 +95,7 @@
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#define TIVA_ADI4_AUX_MASK8B (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK8B_OFFSET)
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#define TIVA_ADI4_AUX_MASK16B (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK16B_OFFSET)
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/* ADI3 AUX Register Bitfield Definitions ***************************************************************************/
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/* ADI3 AUX Register Bitfield Definitions ***********************************/
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/* TIVA_ADI4_AUX_MUX0 */
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@ -198,11 +201,11 @@
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/* TIVA_ADI4_AUX_ADC0 */
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#define ADI4_AUX_ADC0_EN (1 << 0) /* Bit 0: ADC Enable */
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#define ADI4_AUX_ADC0_RESET_N (1 << 1) /* Bit 1: Reset ADC digital subchip, active low */
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#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT (3) /* Bits 3-6: Controls the sampling duration
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* before conversion when the ADC is operated
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* in synchronous mode (SMPL_MODE = 0) */
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#define ADI4_AUX_ADC0_EN (1 << 0) /* Bit 0: ADC Enable */
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#define ADI4_AUX_ADC0_RESET_N (1 << 1) /* Bit 1: Reset ADC digital subchip, active low */
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#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT (3) /* Bits 3-6: Controls the sampling duration
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* before conversion when the ADC is operated
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* in synchronous mode (SMPL_MODE = 0) */
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#define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_MASK (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
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# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP(n) ((uint32_t)(n) << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT)
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# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p7_US (3 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16 clocks = 2.7us */
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@ -218,7 +221,7 @@
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# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p73_MS (13 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16384 clocks = 2.73ms */
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# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p46_MS (14 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32768 clocks = 5.46ms */
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# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p9_MS (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 65536 clocks = 10.9ms */
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#define ADI4_AUX_ADC0_SMPL_MODE (1 << 7) /* Bit 7: ADC Sampling mode */
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#define ADI4_AUX_ADC0_SMPL_MODE (1 << 7) /* Bit 7: ADC Sampling mode */
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# define ADI4_AUX_ADC0_SMPL_MODE_SYNCH (0)
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# define ADI4_AUX_ADC0_SMPL_MODE_ASYNCH ADI4_AUX_ADC0_SMPL_MODE
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@ -4,7 +4,8 @@
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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* Technical content derives from a TI header file that has a compatible
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* BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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@ -4,7 +4,8 @@
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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* Technical content derives from a TI header file that has a compatible
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* BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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@ -234,6 +235,7 @@
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#define TIVA_DDI_MASK16B_OFFSET 0x0400 /* Offset for 16-bit masked access */
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/* DDI Register Addresses ***************************************************/
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/* Register base addresses depend on that base address of the master, e.g.
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* TIVA_AUX_DDI0_OSC_BASE.
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*/
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@ -1,55 +1,57 @@
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/******************************************************************************
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/****************************************************************************
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* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_memorymap.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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* Technical content derives from a TI header file that has a compatible
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* BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 2) Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3) Neither the name NuttX nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_MEMORYMAP_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_MEMORYMAP_H
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/******************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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******************************************************************************/
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****************************************************************************/
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/******************************************************************************
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/****************************************************************************
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*
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* The following are defines for the base address of the memories and
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* peripherals on the CPU_MMAP interface
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*
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******************************************************************************/
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****************************************************************************/
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#define TIVA_FLASHMEM_BASE 0x00000000 /* FLASHMEM */
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#define TIVA_BROM_BASE 0x10000000 /* BROM */
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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* Technical content derives from a TI header file that has a compatible
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* BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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