diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 27d9774bb8..d0f41f5484 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -1355,6 +1355,33 @@ endif # IMXRT_GPIO_IRQ menu "Ethernet Configuration" depends on IMXRT_ENET +choice + prompt "i.MX RT Ethernet Interface" + default IMXRT_ENET1 + depends on IMXRT_ENET + +config IMXRT_ENET1 + bool "ENET 1" + +config IMXRT_ENET2 + bool "ENET 2" + +endchoice # i.MX RT Ethernet Interface + +choice + prompt "i.MX RT Ethernet TX Clock Source" + default IMXRT_PROVIDES_TXC + depends on IMXRT_ENET + +config IMXRT_MAC_PROVIDES_TXC + bool "i.MX RT Ethernet provides TX Clock" + +config IMXRT_PHY_PROVIDES_TXC + bool "External PHY provides TX Clock" + +endchoice # i.MX RT Ethernet TX Clock Source + + config IMXRT_ENET_NRXBUFFERS int "Number Rx buffers" default 6 diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h index 431df1469a..fadf63fe08 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h @@ -1515,7 +1515,10 @@ #define GPR_GPR1_ENET1_CLK_SEL (1 << 13) #define GPR_GPR1_ENET2_CLK_SEL (1 << 14) #define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) -#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) +#define GPR_GPR1_ENET1_TX_DIR_IN (0 << 17) +#define GPR_GPR1_ENET1_TX_DIR_OUT (1 << 17) +#define GPR_GPR1_ENET2_TX_DIR_IN (0 << 18) +#define GPR_GPR1_ENET2_TX_DIR_OUT (1 << 18) #define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) #define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) #define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h index 6a9820ab77..70fd019cda 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h @@ -156,26 +156,78 @@ #define GPIO_ENET_RDATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) #define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) #define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_ENET_RX_CLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) -#define GPIO_ENET_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_ENET_RX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_ENET_RX_DATA02_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) -#define GPIO_ENET_RX_DATA03_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) -#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) +#define GPIO_ENET_RX_CLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_ENET_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) +#define GPIO_ENET_RX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) +#define GPIO_ENET_RX_DATA02_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_ENET_RX_DATA03_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) #define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) #define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) #define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) -#define GPIO_ENET_TDATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_ENET_TDATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) #define GPIO_ENET_TDATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) #define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) -#define GPIO_ENET_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_ENET_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_ENET_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) -#define GPIO_ENET_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) -#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) -#define GPIO_ENET_TX_ER_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_ENET_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) +#define GPIO_ENET_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) +#define GPIO_ENET_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_ENET_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_ENET_TX_ER_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) + +/* Ethernet (ENET2) */ + +#define GPIO_ENET2_MDC_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_ENET2_MDC_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_ENET2_MDIO_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_ENET2_MDIO_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_ENET2_TDATA0_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_ENET2_TDATA0_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_ENET2_TDATA0_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_ENET2_TDATA1_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_ENET2_TDATA1_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_ENET2_TDATA1_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_ENET2_TDATA2_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_ENET2_TDATA3_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_ENET2_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_ENET2_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_ENET2_TX_CLK_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_ENET2_TX_EN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_ENET2_TX_EN_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_ENET2_TX_EN_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_ENET2_TX_ER_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_ENET2_RDATA0_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_ENET2_RDATA0_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_ENET2_RDATA0_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_ENET2_RDATA1_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_ENET2_RDATA1_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_ENET2_RDATA1_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_ENET2_RDATA2_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_ENET2_RDATA3_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_ENET2_RX_CLK_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_ENET2_RX_EN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_ENET2_RX_EN_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_ENET2_RX_EN_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_ENET2_RX_ER_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_ENET2_RX_ER_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_ENET2_RX_ER_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_ENET2_REF_CLK2_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_ENET2_REF_CLK2_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_ENET2_REF_CLK2_3 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_ENET2_1588_EVENT0_IN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_ENET2_1588_EVENT0_IN_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_ENET2_COL_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_ENET2_CRS_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_ENET2_1588_EVENT1_IN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_ENET2_1588_EVENT2_IN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_ENET2_1588_EVENT3_IN_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_ENET2_1588_EVENT0_OUT_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_ENET2_1588_EVENT0_OUT_2 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_PIO_B0_02_INDEX)) +#define GPIO_ENET2_1588_EVENT1_OUT_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_ENET2_1588_EVENT2_OUT_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_ENET2_1588_EVENT3_OUT_1 (GPIO_PERIPH | GPIO_ALT8 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) /* External Watchdog Monitor (EWM) */ diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index e10b27c5b6..7ff6eff036 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -51,6 +51,8 @@ # include #endif +#include + #include "arm_internal.h" #include "chip.h" #include "imxrt_config.h" @@ -89,12 +91,61 @@ /* CONFIG_IMXRT_ENET_NETHIFS determines the number of physical interfaces * that will be supported. + * + * The current driver only supports one interface chosen at compile time. + * It may be either ETH1 or ETH2. In the future 2 interfaces may be + * supported. */ #if CONFIG_IMXRT_ENET_NETHIFS != 1 # error "CONFIG_IMXRT_ENET_NETHIFS must be one for now" #endif +#if defined(CONFIG_IMXRT_ENET1) && defined(CONFIG_IMXRT_ENET2) +# error "The current driver only supports one interface CONFIG_IMXRT_ENET{1|2}" +#endif + +#if defined(CONFIG_IMXRT_MAC_PROVIDES_TXC) && \ + defined(CONFIG_IMXRT_PHY_PROVIDES_TXC) +# error "Only one of CONFIG_IMXRT_PHY_PROVIDES_TXC, CONFIG_IMXRT_MAC_PROVIDES_TXC can be selected" +#endif +#if !defined(CONFIG_IMXRT_MAC_PROVIDES_TXC) && \ + !defined(CONFIG_IMXRT_PHY_PROVIDES_TXC) +# error "One of CONFIG_IMXRT_PHY_PROVIDES_TXC, CONFIG_IMXRT_MAC_PROVIDES_TXC must be selected" +#endif + +#if defined(CONFIG_IMXRT_ENET1) +# define imxrt_clock_enet imxrt_clockall_enet +# define GPR_GPR1_ENET_MASK (GPR_GPR1_ENET1_CLK_SEL | \ + GPR_GPR1_ENET1_TX_DIR_OUT) +# define IMXRT_ENET_IRQ IMXRT_IRQ_ENET +# define IMXRT_ENETN_BASE IMXRT_ENET_BASE +# if defined(CONFIG_IMXRT_MAC_PROVIDES_TXC) +# define GPR_GPR1_ENET_TX_DIR GPR_GPR1_ENET1_TX_DIR_OUT +# define GPR_GPR1_ENET_CLK_SEL 0 +# endif +# if defined(CONFIG_IMXRT_PHY_PROVIDES_TXC) +# define GPR_GPR1_ENET_TX_DIR GPR_GPR1_ENET1_TX_DIR_IN +# define GPR_GPR1_ENET_CLK_SEL GPR_GPR1_ENET1_CLK_SEL +# endif +#endif + +#if defined(CONFIG_IMXRT_ENET2) +# define imxrt_clock_enet imxrt_clockall_enet2 +# define GPR_GPR1_ENET_MASK (GPR_GPR1_ENET2_CLK_SEL | \ + GPR_GPR1_ENET2_TX_DIR_OUT) +# define IMXRT_ENET_IRQ IMXRT_IRQ_ENET2 +# define IMXRT_ENETN_BASE IMXRT_ENET2_BASE +# if defined(CONFIG_IMXRT_MAC_PROVIDES_TXC) +# define GPR_GPR1_ENET_TX_DIR GPR_GPR1_ENET2_TX_DIR_OUT +# define GPR_GPR1_ENET_CLK_SEL 0 +# endif +# if defined(CONFIG_IMXRT_PHY_PROVIDES_TXC) +# define GPR_GPR1_ENET_TX_DIR GPR_GPR1_ENET2_TX_DIR_IN +# define GPR_GPR1_ENET_CLK_SEL GPR_GPR1_ENET2_CLK_SEL +# endif +#endif + #if CONFIG_IMXRT_ENET_NTXBUFFERS < 1 # error "Need at least one TX buffer" #endif @@ -125,12 +176,6 @@ # error Write back D-Cache not yet supported #endif -/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per - * second. - */ - -#define IMXRT_WDDELAY (1 * CLK_TCK) - /* Align assuming that the D-Cache is enabled (probably 32-bytes). * * REVISIT: The size of descriptors and buffers must also be in even units @@ -268,11 +313,12 @@ struct imxrt_driver_s { - bool bifup; /* true:ifup false:ifdown */ - uint8_t txtail; /* The oldest busy TX descriptor */ - uint8_t txhead; /* The next TX descriptor to use */ - uint8_t rxtail; /* The next RX descriptor to use */ - uint8_t phyaddr; /* Selected PHY address */ + uint32_t base; /* Base address of ENET controller */ + bool bifup; /* true:ifup false:ifdown */ + uint8_t txtail; /* The oldest busy TX descriptor */ + uint8_t txhead; /* The next TX descriptor to use */ + uint8_t rxtail; /* The next RX descriptor to use */ + uint8_t phyaddr; /* Selected PHY address */ struct wdog_s txtimeout; /* TX timeout timer */ struct work_s irqwork; /* For deferring interrupt work to the work queue */ struct work_s pollwork; /* For deferring poll work to the work queue */ @@ -312,6 +358,11 @@ static uint8_t g_buffer_pool[NENET_NBUFFERS * IMXRT_BUF_SIZE] /* Utility functions */ +static inline uint32_t imxrt_enet_getreg32(FAR struct imxrt_driver_s *priv, + uint32_t offset); +static inline void imxrt_enet_putreg32(FAR struct imxrt_driver_s *priv, + uint32_t value, uint32_t offset); + #ifndef IMXRT_BUFFERS_SWAP # define imxrt_swap32(value) (value) # define imxrt_swap16(value) (value) @@ -389,6 +440,49 @@ static void imxrt_reset(struct imxrt_driver_s *priv); * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: imxrt_enet_getreg32 + * + * Description: + * Get the contents of the ENET register at offset + * + * Input Parameters: + * priv - private ENET device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline uint32_t +imxrt_enet_getreg32(FAR struct imxrt_driver_s *priv, uint32_t offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: imxrt_enet_putreg32 + * + * Description: + * Write a 16-bit value to the ENET register at offset + * + * Input Parameters: + * priv - private SPI device structure + * value - the 32-bit value to be written + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline void imxrt_enet_putreg32(FAR struct imxrt_driver_s *priv, + uint32_t value, uint32_t offset) +{ + putreg32(value, priv->base + offset); +} + /**************************************************************************** * Function: imxrt_swap16/32 * @@ -563,9 +657,9 @@ static int imxrt_transmit(struct imxrt_driver_s *priv) /* Enable TX interrupts */ - regval = getreg32(IMXRT_ENET_EIMR); + regval = imxrt_enet_getreg32(priv, IMXRT_ENET_EIMR_OFFSET); regval |= TX_INTERRUPTS; - putreg32(regval, IMXRT_ENET_EIMR); + imxrt_enet_putreg32(priv, regval, IMXRT_ENET_EIMR_OFFSET); /* Setup the TX timeout watchdog (perhaps restarting the timer) */ @@ -574,7 +668,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv) /* Start the TX transfer (if it was not already waiting for buffers) */ - putreg32(ENET_TDAR, IMXRT_ENET_TDAR); + imxrt_enet_putreg32(priv, ENET_TDAR, IMXRT_ENET_TDAR_OFFSET); spin_unlock_irqrestore(NULL, flags); return OK; @@ -883,7 +977,7 @@ static void imxrt_receive(struct imxrt_driver_s *priv) /* Indicate that there have been empty receive buffers produced */ - putreg32(ENET_RDAR, IMXRT_ENET_RDAR); + imxrt_enet_putreg32(priv, ENET_RDAR, IMXRT_ENET_RDAR_OFFSET); } } while (received); @@ -961,9 +1055,9 @@ static void imxrt_txdone(struct imxrt_driver_s *priv) wd_cancel(&priv->txtimeout); - regval = getreg32(IMXRT_ENET_EIMR); + regval = imxrt_enet_getreg32(priv, IMXRT_ENET_EIMR_OFFSET); regval &= ~TX_INTERRUPTS; - putreg32(regval, IMXRT_ENET_EIMR); + imxrt_enet_putreg32(priv, regval, IMXRT_ENET_EIMR_OFFSET); } /* There should be space for a new TX in any event. Poll the network for @@ -1005,11 +1099,12 @@ static void imxrt_enet_interrupt_work(void *arg) /* Get the set of unmasked, pending interrupt. */ - pending = getreg32(IMXRT_ENET_EIR) & getreg32(IMXRT_ENET_EIMR); + pending = imxrt_enet_getreg32(priv, IMXRT_ENET_EIR_OFFSET) & + imxrt_enet_getreg32(priv, IMXRT_ENET_EIMR_OFFSET); /* Clear the pending interrupts */ - putreg32(pending, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, pending, IMXRT_ENET_EIR_OFFSET); /* Check for errors */ @@ -1036,8 +1131,8 @@ static void imxrt_enet_interrupt_work(void *arg) * multicast hash table. */ - gaurstore = getreg32(IMXRT_ENET_GAUR); - galrstore = getreg32(IMXRT_ENET_GALR); + gaurstore = imxrt_enet_getreg32(priv, IMXRT_ENET_GAUR_OFFSET); + galrstore = imxrt_enet_getreg32(priv, IMXRT_ENET_GALR_OFFSET); #endif imxrt_ifdown(&priv->dev); @@ -1046,8 +1141,8 @@ static void imxrt_enet_interrupt_work(void *arg) #ifdef CONFIG_NET_MCASTGROUP /* Now write the multicast table back */ - putreg32(gaurstore, IMXRT_ENET_GAUR); - putreg32(galrstore, IMXRT_ENET_GALR); + imxrt_enet_putreg32(priv, gaurstore, IMXRT_ENET_GAUR_OFFSET); + imxrt_enet_putreg32(priv, galrstore, IMXRT_ENET_GALR_OFFSET); #endif /* Then poll the network for new XMIT data */ @@ -1087,7 +1182,7 @@ static void imxrt_enet_interrupt_work(void *arg) #if 0 up_enable_irq(IMXRT_IRQ_EMACTMR); #endif - up_enable_irq(IMXRT_IRQ_ENET); + up_enable_irq(IMXRT_ENET_IRQ); } /**************************************************************************** @@ -1112,14 +1207,15 @@ static void imxrt_enet_interrupt_work(void *arg) static int imxrt_enet_interrupt(int irq, void *context, void *arg) { - register struct imxrt_driver_s *priv = &g_enet[0]; + register FAR struct imxrt_driver_s *priv = + (FAR struct imxrt_driver_s *) arg; /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. */ - up_disable_irq(IMXRT_IRQ_ENET); + up_disable_irq(IMXRT_ENET_IRQ); /* Schedule to perform the interrupt processing on the worker thread. */ @@ -1194,7 +1290,7 @@ static void imxrt_txtimeout_expiry(wdparm_t arg) * condition with interrupt work that is already queued and in progress. */ - up_disable_irq(IMXRT_IRQ_ENET); + up_disable_irq(IMXRT_ENET_IRQ); /* Schedule to perform the TX timeout processing on the worker thread, * canceling any pending interrupt work. @@ -1248,9 +1344,10 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) /* Set the MAC address */ - putreg32((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3], - IMXRT_ENET_PALR); - putreg32((mac[4] << 24) | (mac[5] << 16), IMXRT_ENET_PAUR); + imxrt_enet_putreg32(priv, (mac[0] << 24) | (mac[1] << 16) | + (mac[2] << 8) | mac[3], IMXRT_ENET_PALR_OFFSET); + imxrt_enet_putreg32(priv, (mac[4] << 24) | (mac[5] << 16), + IMXRT_ENET_PAUR_OFFSET); /* Configure the PHY */ @@ -1264,55 +1361,56 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) /* Handle promiscuous mode */ #ifdef CONFIG_NET_PROMISCUOUS - regval = getreg32(IMXRT_ENET_RCR); + regval = imxrt_enet_getreg32(priv, IMXRT_ENET_RCR_OFFSET); regval |= ENET_RCR_PROM; - putreg32(regval, IMXRT_ENET_RCR); + imxrt_enet_putreg32(priv, regval, IMXRT_ENET_RCR_OFFSET); #endif /* Select legacy of enhanced buffer descriptor format */ #ifdef CONFIG_IMXRT_ENETENHANCEDBD - putreg32(ENET_ECR_EN1588, IMXRT_ENET_ECR); + imxrt_enet_putreg32(priv, ENET_ECR_EN1588, IMXRT_ENET_ECR_OFFSET); #else - putreg32(0, IMXRT_ENET_ECR); + imxrt_enet_putreg32(priv, 0, IMXRT_ENET_ECR_OFFSET); #endif /* Set the RX buffer size */ - putreg32(IMXRT_BUF_SIZE, IMXRT_ENET_MRBR); + imxrt_enet_putreg32(priv, IMXRT_BUF_SIZE, IMXRT_ENET_MRBR_OFFSET); /* Point to the start of the circular RX buffer descriptor queue */ - putreg32((uint32_t)priv->rxdesc, IMXRT_ENET_RDSR); + imxrt_enet_putreg32(priv, (uint32_t)priv->rxdesc, IMXRT_ENET_RDSR_OFFSET); /* Point to the start of the circular TX buffer descriptor queue */ - putreg32((uint32_t)priv->txdesc, IMXRT_ENET_TDSR); + imxrt_enet_putreg32(priv, (uint32_t)priv->txdesc, IMXRT_ENET_TDSR_OFFSET); /* And enable the MAC itself */ - regval = getreg32(IMXRT_ENET_ECR); + regval = imxrt_enet_getreg32(priv, IMXRT_ENET_ECR_OFFSET); regval |= ENET_ECR_ETHEREN #ifdef IMXRT_USE_DBSWAP | ENET_ECR_DBSWP #endif ; - putreg32(regval, IMXRT_ENET_ECR); + imxrt_enet_putreg32(priv, regval, IMXRT_ENET_ECR_OFFSET); /* Indicate that there have been empty receive buffers produced */ - putreg32(ENET_RDAR, IMXRT_ENET_RDAR); + imxrt_enet_putreg32(priv, ENET_RDAR, IMXRT_ENET_RDAR_OFFSET); /* Clear all pending ENET interrupt */ - putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, + IMXRT_ENET_EIR_OFFSET); /* Enable RX and error interrupts at the controller (TX interrupts are * still disabled). */ - putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS, - IMXRT_ENET_EIMR); + imxrt_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS, + IMXRT_ENET_EIMR_OFFSET); /* Mark the interrupt "up" and enable interrupts at the NVIC */ @@ -1321,7 +1419,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) #if 0 up_enable_irq(IMXRT_IRQ_EMACTMR); #endif - up_enable_irq(IMXRT_IRQ_ENET); + up_enable_irq(IMXRT_ENET_IRQ); return OK; } @@ -1382,8 +1480,8 @@ static int imxrt_ifdown(struct net_driver_s *dev) flags = enter_critical_section(); - up_disable_irq(IMXRT_IRQ_ENET); - putreg32(0, IMXRT_ENET_EIMR); + up_disable_irq(IMXRT_ENET_IRQ); + imxrt_enet_putreg32(priv, 0, IMXRT_ENET_EIMR_OFFSET); /* Cancel the TX timeout timers */ @@ -1591,6 +1689,7 @@ static int imxrt_addmac(struct net_driver_s *dev, const uint8_t *mac) uint32_t hashindex; uint32_t temp; uint32_t registeraddress; + struct imxrt_driver_s *priv = (struct imxrt_driver_s *)dev->d_private; hashindex = imxrt_enet_hash_index(mac); @@ -1598,17 +1697,17 @@ static int imxrt_addmac(struct net_driver_s *dev, const uint8_t *mac) if (hashindex > 31) { - registeraddress = IMXRT_ENET_GAUR; + registeraddress = IMXRT_ENET_GAUR_OFFSET; hashindex -= 32; } else { - registeraddress = IMXRT_ENET_GALR; + registeraddress = IMXRT_ENET_GALR_OFFSET; } - temp = getreg32(registeraddress); + temp = imxrt_enet_getreg32(priv, registeraddress); temp |= 1 << hashindex; - putreg32(temp, registeraddress); + imxrt_enet_putreg32(priv, temp, registeraddress); return OK; } @@ -1638,6 +1737,7 @@ static int imxrt_rmmac(struct net_driver_s *dev, const uint8_t *mac) uint32_t hashindex; uint32_t temp; uint32_t registeraddress; + struct imxrt_driver_s *priv = (struct imxrt_driver_s *)dev->d_private; /* Remove the MAC address from the hardware multicast routing table */ @@ -1645,17 +1745,17 @@ static int imxrt_rmmac(struct net_driver_s *dev, const uint8_t *mac) if (hashindex > 31) { - registeraddress = IMXRT_ENET_GAUR; + registeraddress = IMXRT_ENET_GAUR_OFFSET; hashindex -= 32; } else { - registeraddress = IMXRT_ENET_GALR; + registeraddress = IMXRT_ENET_GALR_OFFSET; } - temp = getreg32(registeraddress); + temp = imxrt_enet_getreg32(priv, registeraddress); temp &= ~(1 << hashindex); - putreg32(temp, registeraddress); + imxrt_enet_putreg32(priv, temp, registeraddress); return OK; } @@ -1814,9 +1914,9 @@ static void imxrt_initmii(struct imxrt_driver_s *priv) * clock. This hold time value may need to be increased on some platforms */ - putreg32(ENET_MSCR_HOLDTIME_2CYCLES | - IMXRT_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT, - IMXRT_ENET_MSCR); + imxrt_enet_putreg32(priv, ENET_MSCR_HOLDTIME_2CYCLES | + IMXRT_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT, + IMXRT_ENET_MSCR_OFFSET); } /**************************************************************************** @@ -1843,23 +1943,24 @@ static int imxrt_writemii(struct imxrt_driver_s *priv, uint8_t phyaddr, /* Clear the MII interrupt bit */ - putreg32(ENET_INT_MII, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, ENET_INT_MII, IMXRT_ENET_EIR_OFFSET); /* Initiate the MII Management write */ - putreg32(data | - 2 << ENET_MMFR_TA_SHIFT | - (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | - (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT | - ENET_MMFR_OP_WRMII | - 1 << ENET_MMFR_ST_SHIFT, - IMXRT_ENET_MMFR); + imxrt_enet_putreg32(priv, data | + 2 << ENET_MMFR_TA_SHIFT | + (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | + (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT | + ENET_MMFR_OP_WRMII | + 1 << ENET_MMFR_ST_SHIFT, + IMXRT_ENET_MMFR_OFFSET); /* Wait for the transfer to complete */ for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) { - if ((getreg32(IMXRT_ENET_EIR) & ENET_INT_MII) != 0) + if ((imxrt_enet_getreg32(priv, IMXRT_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) { break; } @@ -1874,7 +1975,7 @@ static int imxrt_writemii(struct imxrt_driver_s *priv, uint8_t phyaddr, /* Clear the MII interrupt bit */ - putreg32(ENET_INT_MII, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, ENET_INT_MII, IMXRT_ENET_EIR_OFFSET); return OK; } @@ -1902,22 +2003,23 @@ static int imxrt_readmii(struct imxrt_driver_s *priv, uint8_t phyaddr, /* Clear the MII interrupt bit */ - putreg32(ENET_INT_MII, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, ENET_INT_MII, IMXRT_ENET_EIR_OFFSET); /* Initiate the MII Management read */ - putreg32(2 << ENET_MMFR_TA_SHIFT | - (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | - (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT | - ENET_MMFR_OP_RDMII | - 1 << ENET_MMFR_ST_SHIFT, - IMXRT_ENET_MMFR); + imxrt_enet_putreg32(priv, 2 << ENET_MMFR_TA_SHIFT | + (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | + (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT | + ENET_MMFR_OP_RDMII | + 1 << ENET_MMFR_ST_SHIFT, + IMXRT_ENET_MMFR_OFFSET); /* Wait for the transfer to complete */ for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) { - if ((getreg32(IMXRT_ENET_EIR) & ENET_INT_MII) != 0) + if ((imxrt_enet_getreg32(priv, IMXRT_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) { break; } @@ -1933,11 +2035,12 @@ static int imxrt_readmii(struct imxrt_driver_s *priv, uint8_t phyaddr, /* Clear the MII interrupt bit */ - putreg32(ENET_INT_MII, IMXRT_ENET_EIR); + imxrt_enet_putreg32(priv, ENET_INT_MII, IMXRT_ENET_EIR_OFFSET); /* And return the MII data */ - *data = (uint16_t)(getreg32(IMXRT_ENET_MMFR) & ENET_MMFR_DATA_MASK); + *data = (uint16_t)(imxrt_enet_getreg32(priv, IMXRT_ENET_MMFR_OFFSET) & + ENET_MMFR_DATA_MASK); return OK; } @@ -2221,8 +2324,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) #endif tcr = 0; - putreg32(rcr, IMXRT_ENET_RCR); - putreg32(tcr, IMXRT_ENET_TCR); + imxrt_enet_putreg32(priv, rcr, IMXRT_ENET_RCR_OFFSET); + imxrt_enet_putreg32(priv, tcr, IMXRT_ENET_TCR_OFFSET); /* Enable Discard Of Frames With MAC Layer Errors. * Enable Discard Of Frames With Wrong Protocol Checksum. @@ -2230,7 +2333,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) */ racc = ENET_RACC_PRODIS | ENET_RACC_LINEDIS | ENET_RACC_IPDIS; - putreg32(racc, IMXRT_ENET_RACC); + imxrt_enet_putreg32(priv, racc, IMXRT_ENET_RACC_OFFSET); /* Setup half or full duplex */ @@ -2271,8 +2374,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) return -EIO; } - putreg32(rcr, IMXRT_ENET_RCR); - putreg32(tcr, IMXRT_ENET_TCR); + imxrt_enet_putreg32(priv, rcr, IMXRT_ENET_RCR_OFFSET); + imxrt_enet_putreg32(priv, tcr, IMXRT_ENET_TCR_OFFSET); return OK; } @@ -2377,7 +2480,7 @@ static void imxrt_reset(struct imxrt_driver_s *priv) /* Set the reset bit and clear the enable bit */ - putreg32(ENET_ECR_RESET, IMXRT_ENET_ECR); + imxrt_enet_putreg32(priv, ENET_ECR_RESET, IMXRT_ENET_ECR_OFFSET); /* Wait at least 8 clock cycles */ @@ -2424,58 +2527,12 @@ int imxrt_netinitialize(int intf) DEBUGASSERT(intf < CONFIG_IMXRT_ENET_NETHIFS); priv = &g_enet[intf]; - /* Enable ENET1_TX_CLK_DIR (Provides 50MHz clk OUT to PHY) */ - - regval = getreg32(IMXRT_IOMUXC_GPR_GPR1); - regval |= GPR_GPR1_ENET1_TX_CLK_OUT_EN; - putreg32(regval, IMXRT_IOMUXC_GPR_GPR1); - - /* Enable the ENET clock. Clock is on during all modes, - * except STOP mode. - */ - - imxrt_clockall_enet(); - - /* Configure all ENET/MII pins */ - - imxrt_config_gpio(GPIO_ENET_MDIO); - imxrt_config_gpio(GPIO_ENET_MDC); - imxrt_config_gpio(GPIO_ENET_RX_EN); - imxrt_config_gpio(GPIO_ENET_RX_DATA00); - imxrt_config_gpio(GPIO_ENET_RX_DATA01); - imxrt_config_gpio(GPIO_ENET_TX_DATA00); - imxrt_config_gpio(GPIO_ENET_TX_DATA01); - imxrt_config_gpio(GPIO_ENET_TX_CLK); - imxrt_config_gpio(GPIO_ENET_TX_EN); -#ifdef GPIO_ENET_RX_ER - imxrt_config_gpio(GPIO_ENET_RX_ER); -#endif - - /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ - -#if 0 - if (irq_attach(IMXRT_IRQ_EMACTMR, imxrt_tmrinterrupt, NULL)) - { - /* We could not attach the ISR to the interrupt */ - - nerr("ERROR: Failed to attach EMACTMR IRQ\n"); - return -EAGAIN; - } -#endif - - /* Attach the Ethernet interrupt handler */ - - if (irq_attach(IMXRT_IRQ_ENET, imxrt_enet_interrupt, NULL)) - { - /* We could not attach the ISR to the interrupt */ - - nerr("ERROR: Failed to attach EMACTX IRQ\n"); - return -EAGAIN; - } - /* Initialize the driver structure */ memset(priv, 0, sizeof(struct imxrt_driver_s)); + + priv->base = IMXRT_ENETN_BASE; /* Assigne base address */ + priv->dev.d_ifup = imxrt_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = imxrt_ifdown; /* I/F down callback */ priv->dev.d_txavail = imxrt_txavail; /* New TX data callback */ @@ -2488,6 +2545,73 @@ int imxrt_netinitialize(int intf) #endif priv->dev.d_private = g_enet; /* Used to recover private state from dev */ + /* Configure ENET1_TX_CLK */ + + regval = getreg32(IMXRT_IOMUXC_GPR_GPR1); + regval &= ~GPR_GPR1_ENET_MASK; + regval |= (GPR_GPR1_ENET_TX_DIR | GPR_GPR1_ENET_CLK_SEL); + putreg32(regval, IMXRT_IOMUXC_GPR_GPR1); + + /* Enable the ENET clock. Clock is on during all modes, + * except STOP mode. + */ + + imxrt_clock_enet(); + + /* Configure all ENET/MII pins */ + +#if defined(CONFIG_IMXRT_ENET1) + imxrt_config_gpio(GPIO_ENET_MDIO); + imxrt_config_gpio(GPIO_ENET_MDC); + imxrt_config_gpio(GPIO_ENET_RX_EN); + imxrt_config_gpio(GPIO_ENET_RX_DATA00); + imxrt_config_gpio(GPIO_ENET_RX_DATA01); + imxrt_config_gpio(GPIO_ENET_TX_DATA00); + imxrt_config_gpio(GPIO_ENET_TX_DATA01); + imxrt_config_gpio(GPIO_ENET_TX_CLK); + imxrt_config_gpio(GPIO_ENET_TX_EN); +# ifdef GPIO_ENET_RX_ER + imxrt_config_gpio(GPIO_ENET_RX_ER); +# endif +#endif + +#if defined(CONFIG_IMXRT_ENET2) + imxrt_config_gpio(GPIO_ENET2_MDIO); + imxrt_config_gpio(GPIO_ENET2_MDC); + imxrt_config_gpio(GPIO_ENET2_RX_EN); + imxrt_config_gpio(GPIO_ENET2_RX_DATA00); + imxrt_config_gpio(GPIO_ENET2_RX_DATA01); + imxrt_config_gpio(GPIO_ENET2_TX_DATA00); + imxrt_config_gpio(GPIO_ENET2_TX_DATA01); + imxrt_config_gpio(GPIO_ENET2_TX_CLK); + imxrt_config_gpio(GPIO_ENET2_TX_EN); +# ifdef GPIO_ENET2_RX_ER + imxrt_config_gpio(GPIO_ENET2_RX_ER); +# endif +#endif + + /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ + +#if 0 + if (irq_attach(IMXRT_IRQ_EMACTMR, imxrt_tmrinterrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach EMACTMR IRQ\n"); + return -EAGAIN; + } +#endif + + /* Attach the Ethernet interrupt handler */ + + if (irq_attach(IMXRT_ENET_IRQ, imxrt_enet_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach EMACTX IRQ\n"); + return -EAGAIN; + } + #ifdef CONFIG_NET_ETHERNET #ifdef CONFIG_NET_USE_OTP_ETHERNET_MAC diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h index e71aea4937..55ee2fd067 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.h +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -67,6 +67,7 @@ #define imxrt_clockoff_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_OFF) #define imxrt_clockoff_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_OFF) #define imxrt_clockoff_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_OFF) +#define imxrt_clockoff_enet2() imxrt_periphclk_configure(CCM_CCGR_ENET2, CCM_CG_OFF) #define imxrt_clockoff_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_OFF) #define imxrt_clockoff_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_OFF) #define imxrt_clockoff_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_OFF) @@ -180,6 +181,7 @@ #define imxrt_clockrun_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_RUN) #define imxrt_clockrun_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_RUN) #define imxrt_clockrun_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_RUN) +#define imxrt_clockrun_enet2() imxrt_periphclk_configure(CCM_CCGR_ENET2, CCM_CG_RUN) #define imxrt_clockrun_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_RUN) #define imxrt_clockrun_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_RUN) #define imxrt_clockrun_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_RUN) @@ -293,6 +295,7 @@ #define imxrt_clockall_enc3() imxrt_periphclk_configure(CCM_CCGR_ENC3, CCM_CG_ALL) #define imxrt_clockall_enc4() imxrt_periphclk_configure(CCM_CCGR_ENC4, CCM_CG_ALL) #define imxrt_clockall_enet() imxrt_periphclk_configure(CCM_CCGR_ENET, CCM_CG_ALL) +#define imxrt_clockall_enet2() imxrt_periphclk_configure(CCM_CCGR_ENET2, CCM_CG_ALL) #define imxrt_clockall_ewm() imxrt_periphclk_configure(CCM_CCGR_EWM, CCM_CG_ALL) #define imxrt_clockall_flexio1() imxrt_periphclk_configure(CCM_CCGR_FLEXIO1, CCM_CG_ALL) #define imxrt_clockall_flexio2() imxrt_periphclk_configure(CCM_CCGR_FLEXIO2, CCM_CG_ALL)