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Merged in raiden00/nuttx_h7 (pull request #672)

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stm32h7: add lowputc, more cosmetic in stm32h7x3xx_rcc.h

Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni 2018-07-09 16:32:22 +00:00 committed by GregoryN
parent 0aa30eb15b
commit 8271f72b72
7 changed files with 1169 additions and 578 deletions
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2
arch/arm/src/stm32h7/Make.defs
View File

@ -108,7 +108,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_start.c stm32_rcc.c
CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c

884
arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h
View File

@ -236,7 +236,7 @@
/* Clock Configuration Register (CFGR) */
#define RCC_CFGR_SW_SHIFT (1) /* Bits 0-2: System clock Switch */
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */
#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT)
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */
# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */
@ -520,648 +520,398 @@
/* AHB1 peripheral reset register */
#define RCC_AHB1RSTR_DMA1RST_SHIFT (0ul) /* RCC AHB1RSTR: DMA1RST (Bit 0) */
#define RCC_AHB1RSTR_DMA1RST (0x1ul) /* RCC AHB1RSTR: DMA1RST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_DMA2RST_SHIFT (1ul) /* RCC AHB1RSTR: DMA2RST (Bit 1) */
#define RCC_AHB1RSTR_DMA2RST (0x2ul) /* RCC AHB1RSTR: DMA2RST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_ADC12RST_SHIFT (5ul) /* RCC AHB1RSTR: ADC12RST (Bit 5) */
#define RCC_AHB1RSTR_ADC12RST (0x20ul) /* RCC AHB1RSTR: ADC12RST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_ETH1MACRST_SHIFT (15ul) /* RCC AHB1RSTR: ETH1MACRST (Bit 15) */
#define RCC_AHB1RSTR_ETH1MACRST (0x8000ul) /* RCC AHB1RSTR: ETH1MACRST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_USB1OTGRST_SHIFT (25ul) /* RCC AHB1RSTR: USB1OTGRST (Bit 25) */
#define RCC_AHB1RSTR_USB1OTGRST (0x2000000ul) /* RCC AHB1RSTR: USB1OTGRST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_USB2OTGRST_SHIFT (27ul) /* RCC AHB1RSTR: USB2OTGRST (Bit 27) */
#define RCC_AHB1RSTR_USB2OTGRST (0x8000000ul) /* RCC AHB1RSTR: USB2OTGRST (Bitfield-Mask: 0x01) */
#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */
#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */
#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */
/* Bits 6-14: Reserved */
#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */
/* Bits 16-24: Reserved */
#define RCC_AHB1RSTR_USB1OTGRST (1 << 25) /* RCC AHB1RSTR: USB1OTGRST */
/* Bit 26: Reserved */
#define RCC_AHB1RSTR_USB2OTGRST (1 << 27) /* RCC AHB1RSTR: USB2OTGRST */
/* Bits 28-31: Reserved */
/* AHB2 peripheral reset register */
#define RCC_AHB2RSTR_CAMITFRST_SHIFT (0ul) /* RCC AHB2RSTR: CAMITFRST (Bit 0) */
#define RCC_AHB2RSTR_CAMITFRST (0x1ul) /* RCC AHB2RSTR: CAMITFRST (Bitfield-Mask: 0x01) */
#define RCC_AHB2RSTR_CRYPTRST_SHIFT (4ul) /* RCC AHB2RSTR: CRYPTRST (Bit 4) */
#define RCC_AHB2RSTR_CRYPTRST (0x10ul) /* RCC AHB2RSTR: CRYPTRST (Bitfield-Mask: 0x01) */
#define RCC_AHB2RSTR_HASHRST_SHIFT (5ul) /* RCC AHB2RSTR: HASHRST (Bit 5) */
#define RCC_AHB2RSTR_HASHRST (0x20ul) /* RCC AHB2RSTR: HASHRST (Bitfield-Mask: 0x01) */
#define RCC_AHB2RSTR_RNGRST_SHIFT (6ul) /* RCC AHB2RSTR: RNGRST (Bit 6) */
#define RCC_AHB2RSTR_RNGRST (0x40ul) /* RCC AHB2RSTR: RNGRST (Bitfield-Mask: 0x01) */
#define RCC_AHB2RSTR_SDMMC2RST_SHIFT (9ul) /* RCC AHB2RSTR: SDMMC2RST (Bit 9) */
#define RCC_AHB2RSTR_SDMMC2RST (0x200ul) /* RCC AHB2RSTR: SDMMC2RST (Bitfield-Mask: 0x01) */
#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */
/* Bits 1-3: Reserved */
#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */
#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */
#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */
/* Bits 7-8: Reserved */
#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */
/* Bits 10-31: Reserved */
/* AHB4 peripheral reset register */
#define RCC_AHB4RSTR_GPIOARST_SHIFT (0ul) /* RCC AHB4RSTR: GPIOARST (Bit 0) */
#define RCC_AHB4RSTR_GPIOARST (0x1ul) /* RCC AHB4RSTR: GPIOARST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOBRST_SHIFT (1ul) /* RCC AHB4RSTR: GPIOBRST (Bit 1) */
#define RCC_AHB4RSTR_GPIOBRST (0x2ul) /* RCC AHB4RSTR: GPIOBRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOCRST_SHIFT (2ul) /* RCC AHB4RSTR: GPIOCRST (Bit 2) */
#define RCC_AHB4RSTR_GPIOCRST (0x4ul) /* RCC AHB4RSTR: GPIOCRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIODRST_SHIFT (3ul) /* RCC AHB4RSTR: GPIODRST (Bit 3) */
#define RCC_AHB4RSTR_GPIODRST (0x8ul) /* RCC AHB4RSTR: GPIODRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOERST_SHIFT (4ul) /* RCC AHB4RSTR: GPIOERST (Bit 4) */
#define RCC_AHB4RSTR_GPIOERST (0x10ul) /* RCC AHB4RSTR: GPIOERST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOFRST_SHIFT (5ul) /* RCC AHB4RSTR: GPIOFRST (Bit 5) */
#define RCC_AHB4RSTR_GPIOFRST (0x20ul) /* RCC AHB4RSTR: GPIOFRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOGRST_SHIFT (6ul) /* RCC AHB4RSTR: GPIOGRST (Bit 6) */
#define RCC_AHB4RSTR_GPIOGRST (0x40ul) /* RCC AHB4RSTR: GPIOGRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOHRST_SHIFT (7ul) /* RCC AHB4RSTR: GPIOHRST (Bit 7) */
#define RCC_AHB4RSTR_GPIOHRST (0x80ul) /* RCC AHB4RSTR: GPIOHRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOIRST_SHIFT (8ul) /* RCC AHB4RSTR: GPIOIRST (Bit 8) */
#define RCC_AHB4RSTR_GPIOIRST (0x100ul) /* RCC AHB4RSTR: GPIOIRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOJRST_SHIFT (9ul) /* RCC AHB4RSTR: GPIOJRST (Bit 9) */
#define RCC_AHB4RSTR_GPIOJRST (0x200ul) /* RCC AHB4RSTR: GPIOJRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOKRST_SHIFT (10ul) /* RCC AHB4RSTR: GPIOKRST (Bit 10) */
#define RCC_AHB4RSTR_GPIOKRST (0x400ul) /* RCC AHB4RSTR: GPIOKRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_CRCRST_SHIFT (19ul) /* RCC AHB4RSTR: CRCRST (Bit 19) */
#define RCC_AHB4RSTR_CRCRST (0x80000ul) /* RCC AHB4RSTR: CRCRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_BDMARST_SHIFT (21ul) /* RCC AHB4RSTR: BDMARST (Bit 21) */
#define RCC_AHB4RSTR_BDMARST (0x200000ul) /* RCC AHB4RSTR: BDMARST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_ADC3RST_SHIFT (24ul) /* RCC AHB4RSTR: ADC3RST (Bit 24) */
#define RCC_AHB4RSTR_ADC3RST (0x1000000ul) /* RCC AHB4RSTR: ADC3RST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_HSEMRST_SHIFT (25ul) /* RCC AHB4RSTR: HSEMRST (Bit 25) */
#define RCC_AHB4RSTR_HSEMRST (0x2000000ul) /* RCC AHB4RSTR: HSEMRST (Bitfield-Mask: 0x01) */
#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */
#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */
#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */
#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */
#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */
#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */
#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */
#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */
#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */
#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */
#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */
/* Bits 11-18: Reserved */
#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */
/* Bit 20: Reserved */
#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */
/* Bits 22-23: Reserved */
#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */
#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */
/* Bits 26-31: Reserved */
/* APB3 peripheral reset register */
#define RCC_APB3RSTR_LTDCRST_SHIFT (3ul) /* RCC APB3RSTR: LTDCRST (Bit 3) */
#define RCC_APB3RSTR_LTDCRST (0x8ul) /* RCC APB3RSTR: LTDCRST (Bitfield-Mask: 0x01) */
/* Bits 0-2: Reserved */
#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */
/* Bits 4-31: Reserved */
/* APB3 L peripheral reset register */
#define RCC_APB1LRSTR_TIM2RST_SHIFT (0ul) /* RCC APB1LRSTR: TIM2RST (Bit 0) */
#define RCC_APB1LRSTR_TIM2RST (0x1ul) /* RCC APB1LRSTR: TIM2RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM3RST_SHIFT (1ul) /* RCC APB1LRSTR: TIM3RST (Bit 1) */
#define RCC_APB1LRSTR_TIM3RST (0x2ul) /* RCC APB1LRSTR: TIM3RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM4RST_SHIFT (2ul) /* RCC APB1LRSTR: TIM4RST (Bit 2) */
#define RCC_APB1LRSTR_TIM4RST (0x4ul) /* RCC APB1LRSTR: TIM4RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM5RST_SHIFT (3ul) /* RCC APB1LRSTR: TIM5RST (Bit 3) */
#define RCC_APB1LRSTR_TIM5RST (0x8ul) /* RCC APB1LRSTR: TIM5RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM6RST_SHIFT (4ul) /* RCC APB1LRSTR: TIM6RST (Bit 4) */
#define RCC_APB1LRSTR_TIM6RST (0x10ul) /* RCC APB1LRSTR: TIM6RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM7RST_SHIFT (5ul) /* RCC APB1LRSTR: TIM7RST (Bit 5) */
#define RCC_APB1LRSTR_TIM7RST (0x20ul) /* RCC APB1LRSTR: TIM7RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM12RST_SHIFT (6ul) /* RCC APB1LRSTR: TIM12RST (Bit 6) */
#define RCC_APB1LRSTR_TIM12RST (0x40ul) /* RCC APB1LRSTR: TIM12RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM13RST_SHIFT (7ul) /* RCC APB1LRSTR: TIM13RST (Bit 7) */
#define RCC_APB1LRSTR_TIM13RST (0x80ul) /* RCC APB1LRSTR: TIM13RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM14RST_SHIFT (8ul) /* RCC APB1LRSTR: TIM14RST (Bit 8) */
#define RCC_APB1LRSTR_TIM14RST (0x100ul) /* RCC APB1LRSTR: TIM14RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_LPTIM1RST_SHIFT (9ul) /* RCC APB1LRSTR: LPTIM1RST (Bit 9) */
#define RCC_APB1LRSTR_LPTIM1RST (0x200ul) /* RCC APB1LRSTR: LPTIM1RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_SPI2RST_SHIFT (14ul) /* RCC APB1LRSTR: SPI2RST (Bit 14) */
#define RCC_APB1LRSTR_SPI2RST (0x4000ul) /* RCC APB1LRSTR: SPI2RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_SPI3RST_SHIFT (15ul) /* RCC APB1LRSTR: SPI3RST (Bit 15) */
#define RCC_APB1LRSTR_SPI3RST (0x8000ul) /* RCC APB1LRSTR: SPI3RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_SPDIFRXRST_SHIFT (16ul) /* RCC APB1LRSTR: SPDIFRXRST (Bit 16) */
#define RCC_APB1LRSTR_SPDIFRXRST (0x10000ul) /* RCC APB1LRSTR: SPDIFRXRST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_USART2RST_SHIFT (17ul) /* RCC APB1LRSTR: USART2RST (Bit 17) */
#define RCC_APB1LRSTR_USART2RST (0x20000ul) /* RCC APB1LRSTR: USART2RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_USART3RST_SHIFT (18ul) /* RCC APB1LRSTR: USART3RST (Bit 18) */
#define RCC_APB1LRSTR_USART3RST (0x40000ul) /* RCC APB1LRSTR: USART3RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_UART4RST_SHIFT (19ul) /* RCC APB1LRSTR: UART4RST (Bit 19) */
#define RCC_APB1LRSTR_UART4RST (0x80000ul) /* RCC APB1LRSTR: UART4RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_UART5RST_SHIFT (20ul) /* RCC APB1LRSTR: UART5RST (Bit 20) */
#define RCC_APB1LRSTR_UART5RST (0x100000ul) /* RCC APB1LRSTR: UART5RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_I2C1RST_SHIFT (21ul) /* RCC APB1LRSTR: I2C1RST (Bit 21) */
#define RCC_APB1LRSTR_I2C1RST (0x200000ul) /* RCC APB1LRSTR: I2C1RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_I2C2RST_SHIFT (22ul) /* RCC APB1LRSTR: I2C2RST (Bit 22) */
#define RCC_APB1LRSTR_I2C2RST (0x400000ul) /* RCC APB1LRSTR: I2C2RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_I2C3RST_SHIFT (23ul) /* RCC APB1LRSTR: I2C3RST (Bit 23) */
#define RCC_APB1LRSTR_I2C3RST (0x800000ul) /* RCC APB1LRSTR: I2C3RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_HDMICECRST_SHIFT (27ul) /* RCC APB1LRSTR: HDMICECRST (Bit 27) */
#define RCC_APB1LRSTR_HDMICECRST (0x8000000ul) /* RCC APB1LRSTR: HDMICECRST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_DAC12RST_SHIFT (29ul) /* RCC APB1LRSTR: DAC12RST (Bit 29) */
#define RCC_APB1LRSTR_DAC12RST (0x20000000ul) /* RCC APB1LRSTR: DAC12RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_USART7RST_SHIFT (30ul) /* RCC APB1LRSTR: USART7RST (Bit 30) */
#define RCC_APB1LRSTR_USART7RST (0x40000000ul) /* RCC APB1LRSTR: USART7RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_USART8RST_SHIFT (31ul) /* RCC APB1LRSTR: USART8RST (Bit 31) */
#define RCC_APB1LRSTR_USART8RST (0x80000000ul) /* RCC APB1LRSTR: USART8RST (Bitfield-Mask: 0x01) */
#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */
#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */
#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */
#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */
#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */
#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */
#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */
#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */
#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */
#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */
/* Bits 10-13: Reserved */
#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */
#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */
#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */
#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */
#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */
#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */
#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */
#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */
#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */
#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */
/* Bits 24-26: Reserved */
#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */
/* Bit 28: Reserved */
#define RCC_APB1LRSTR_DAC12RST (1 << 29) /* RCC APB1LRSTR: DAC12RST */
#define RCC_APB1LRSTR_USART7RST (1 << 30) /* RCC APB1LRSTR: USART7RST */
#define RCC_APB1LRSTR_USART8RST (1 << 31) /* RCC APB1LRSTR: USART8RST */
/* APB1 H peripheral reset register */
#define RCC_APB1HRSTR_CRSRST_SHIFT (1ul) /* RCC APB1HRSTR: CRSRST (Bit 1) */
#define RCC_APB1HRSTR_CRSRST (0x2ul) /* RCC APB1HRSTR: CRSRST (Bitfield-Mask: 0x01) */
#define RCC_APB1HRSTR_SWPRST_SHIFT (2ul) /* RCC APB1HRSTR: SWPRST (Bit 2) */
#define RCC_APB1HRSTR_SWPRST (0x4ul) /* RCC APB1HRSTR: SWPRST (Bitfield-Mask: 0x01) */
#define RCC_APB1HRSTR_OPAMPRST_SHIFT (4ul) /* RCC APB1HRSTR: OPAMPRST (Bit 4) */
#define RCC_APB1HRSTR_OPAMPRST (0x10ul) /* RCC APB1HRSTR: OPAMPRST (Bitfield-Mask: 0x01) */
#define RCC_APB1HRSTR_MDIOSRST_SHIFT (5ul) /* RCC APB1HRSTR: MDIOSRST (Bit 5) */
#define RCC_APB1HRSTR_MDIOSRST (0x20ul) /* RCC APB1HRSTR: MDIOSRST (Bitfield-Mask: 0x01) */
#define RCC_APB1HRSTR_FDCANRST_SHIFT (8ul) /* RCC APB1HRSTR: FDCANRST (Bit 8) */
#define RCC_APB1HRSTR_FDCANRST (0x100ul) /* RCC APB1HRSTR: FDCANRST (Bitfield-Mask: 0x01) */
/* Bit 0: Reserved */
#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */
#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */
/* Bit 3: Reserved */
#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/
#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */
/* Bits 6-7: Reserved */
#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/
/* Bits 9-31: Reserved */
/* APB2 peripheral reset register */
#define RCC_APB2RSTR_TIM1RST_SHIFT (0ul) /* RCC APB2RSTR: TIM1RST (Bit 0) */
#define RCC_APB2RSTR_TIM1RST (0x1ul) /* RCC APB2RSTR: TIM1RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_TIM8RST_SHIFT (1ul) /* RCC APB2RSTR: TIM8RST (Bit 1) */
#define RCC_APB2RSTR_TIM8RST (0x2ul) /* RCC APB2RSTR: TIM8RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_USART1RST_SHIFT (4ul) /* RCC APB2RSTR: USART1RST (Bit 4) */
#define RCC_APB2RSTR_USART1RST (0x10ul) /* RCC APB2RSTR: USART1RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_USART6RST_SHIFT (5ul) /* RCC APB2RSTR: USART6RST (Bit 5) */
#define RCC_APB2RSTR_USART6RST (0x20ul) /* RCC APB2RSTR: USART6RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SPI1RST_SHIFT (12ul) /* RCC APB2RSTR: SPI1RST (Bit 12) */
#define RCC_APB2RSTR_SPI1RST (0x1000ul) /* RCC APB2RSTR: SPI1RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SPI4RST_SHIFT (13ul) /* RCC APB2RSTR: SPI4RST (Bit 13) */
#define RCC_APB2RSTR_SPI4RST (0x2000ul) /* RCC APB2RSTR: SPI4RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_TIM15RST_SHIFT (16ul) /* RCC APB2RSTR: TIM15RST (Bit 16) */
#define RCC_APB2RSTR_TIM15RST (0x10000ul) /* RCC APB2RSTR: TIM15RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_TIM16RST_SHIFT (17ul) /* RCC APB2RSTR: TIM16RST (Bit 17) */
#define RCC_APB2RSTR_TIM16RST (0x20000ul) /* RCC APB2RSTR: TIM16RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_TIM17RST_SHIFT (18ul) /* RCC APB2RSTR: TIM17RST (Bit 18) */
#define RCC_APB2RSTR_TIM17RST (0x40000ul) /* RCC APB2RSTR: TIM17RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SPI5RST_SHIFT (20ul) /* RCC APB2RSTR: SPI5RST (Bit 20) */
#define RCC_APB2RSTR_SPI5RST (0x100000ul) /* RCC APB2RSTR: SPI5RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SAI1RST_SHIFT (22ul) /* RCC APB2RSTR: SAI1RST (Bit 22) */
#define RCC_APB2RSTR_SAI1RST (0x400000ul) /* RCC APB2RSTR: SAI1RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SAI2RST_SHIFT (23ul) /* RCC APB2RSTR: SAI2RST (Bit 23) */
#define RCC_APB2RSTR_SAI2RST (0x800000ul) /* RCC APB2RSTR: SAI2RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_SAI3RST_SHIFT (24ul) /* RCC APB2RSTR: SAI3RST (Bit 24) */
#define RCC_APB2RSTR_SAI3RST (0x1000000ul) /* RCC APB2RSTR: SAI3RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_DFSDM1RST_SHIFT (28ul) /* RCC APB2RSTR: DFSDM1RST (Bit 28) */
#define RCC_APB2RSTR_DFSDM1RST (0x10000000ul) /* RCC APB2RSTR: DFSDM1RST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_HRTIMRST_SHIFT (29ul) /* RCC APB2RSTR: HRTIMRST (Bit 29) */
#define RCC_APB2RSTR_HRTIMRST (0x20000000ul) /* RCC APB2RSTR: HRTIMRST (Bitfield-Mask: 0x01) */
#define RCC_APB2RSTR_TIM1RST (0x1ul) /* RCC APB2RSTR: TIM1RST */
#define RCC_APB2RSTR_TIM8RST (0x2ul) /* RCC APB2RSTR: TIM8RST */
#define RCC_APB2RSTR_USART1RST (0x10ul) /* RCC APB2RSTR: USART1RST */
#define RCC_APB2RSTR_USART6RST (0x20ul) /* RCC APB2RSTR: USART6RST */
#define RCC_APB2RSTR_SPI1RST (0x1000ul) /* RCC APB2RSTR: SPI1RST */
#define RCC_APB2RSTR_SPI4RST (0x2000ul) /* RCC APB2RSTR: SPI4RST */
#define RCC_APB2RSTR_TIM15RST (0x10000ul) /* RCC APB2RSTR: TIM15RST */
#define RCC_APB2RSTR_TIM16RST (0x20000ul) /* RCC APB2RSTR: TIM16RST */
#define RCC_APB2RSTR_TIM17RST (0x40000ul) /* RCC APB2RSTR: TIM17RST */
#define RCC_APB2RSTR_SPI5RST (0x100000ul) /* RCC APB2RSTR: SPI5RST */
#define RCC_APB2RSTR_SAI1RST (0x400000ul) /* RCC APB2RSTR: SAI1RST */
#define RCC_APB2RSTR_SAI2RST (0x800000ul) /* RCC APB2RSTR: SAI2RST */
#define RCC_APB2RSTR_SAI3RST (0x1000000ul) /* RCC APB2RSTR: SAI3RST */
#define RCC_APB2RSTR_DFSDM1RST (0x10000000ul) /* RCC APB2RSTR: DFSDM1RST */
#define RCC_APB2RSTR_HRTIMRST (0x20000000ul) /* RCC APB2RSTR: HRTIMRST */
/* APB4 peripheral reset register */
#define RCC_APB4RSTR_SYSCFGRST_SHIFT (1ul) /* RCC APB4RSTR: SYSCFGRST (Bit 1) */
#define RCC_APB4RSTR_SYSCFGRST (0x2ul) /* RCC APB4RSTR: SYSCFGRST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_LPUART1RST_SHIFT (3ul) /* RCC APB4RSTR: LPUART1RST (Bit 3) */
#define RCC_APB4RSTR_LPUART1RST (0x8ul) /* RCC APB4RSTR: LPUART1RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_SPI6RST_SHIFT (5ul) /* RCC APB4RSTR: SPI6RST (Bit 5) */
#define RCC_APB4RSTR_SPI6RST (0x20ul) /* RCC APB4RSTR: SPI6RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_I2C4RST_SHIFT (7ul) /* RCC APB4RSTR: I2C4RST (Bit 7) */
#define RCC_APB4RSTR_I2C4RST (0x80ul) /* RCC APB4RSTR: I2C4RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_LPTIM2RST_SHIFT (9ul) /* RCC APB4RSTR: LPTIM2RST (Bit 9) */
#define RCC_APB4RSTR_LPTIM2RST (0x200ul) /* RCC APB4RSTR: LPTIM2RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_LPTIM3RST_SHIFT (10ul) /* RCC APB4RSTR: LPTIM3RST (Bit 10) */
#define RCC_APB4RSTR_LPTIM3RST (0x400ul) /* RCC APB4RSTR: LPTIM3RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_LPTIM4RST_SHIFT (11ul) /* RCC APB4RSTR: LPTIM4RST (Bit 11) */
#define RCC_APB4RSTR_LPTIM4RST (0x800ul) /* RCC APB4RSTR: LPTIM4RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_LPTIM5RST_SHIFT (12ul) /* RCC APB4RSTR: LPTIM5RST (Bit 12) */
#define RCC_APB4RSTR_LPTIM5RST (0x1000ul) /* RCC APB4RSTR: LPTIM5RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_COMP12RST_SHIFT (14ul) /* RCC APB4RSTR: COMP12RST (Bit 14) */
#define RCC_APB4RSTR_COMP12RST (0x4000ul) /* RCC APB4RSTR: COMP12RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_VREFRST_SHIFT (15ul) /* RCC APB4RSTR: VREFRST (Bit 15) */
#define RCC_APB4RSTR_VREFRST (0x8000ul) /* RCC APB4RSTR: VREFRST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_SAI4RST_SHIFT (21ul) /* RCC APB4RSTR: SAI4RST (Bit 21) */
#define RCC_APB4RSTR_SAI4RST (0x200000ul) /* RCC APB4RSTR: SAI4RST (Bitfield-Mask: 0x01) */
#define RCC_APB4RSTR_SYSCFGRST (0x2ul) /* RCC APB4RSTR: SYSCFGRST */
#define RCC_APB4RSTR_LPUART1RST (0x8ul) /* RCC APB4RSTR: LPUART1RST */
#define RCC_APB4RSTR_SPI6RST (0x20ul) /* RCC APB4RSTR: SPI6RST */
#define RCC_APB4RSTR_I2C4RST (0x80ul) /* RCC APB4RSTR: I2C4RST */
#define RCC_APB4RSTR_LPTIM2RST (0x200ul) /* RCC APB4RSTR: LPTIM2RST */
#define RCC_APB4RSTR_LPTIM3RST (0x400ul) /* RCC APB4RSTR: LPTIM3RST */
#define RCC_APB4RSTR_LPTIM4RST (0x800ul) /* RCC APB4RSTR: LPTIM4RST */
#define RCC_APB4RSTR_LPTIM5RST (0x1000ul) /* RCC APB4RSTR: LPTIM5RST */
#define RCC_APB4RSTR_COMP12RST (0x4000ul) /* RCC APB4RSTR: COMP12RST */
#define RCC_APB4RSTR_VREFRST (0x8000ul) /* RCC APB4RSTR: VREFRST */
#define RCC_APB4RSTR_SAI4RST (0x200000ul) /* RCC APB4RSTR: SAI4RST */
/* AHB3 Peripheral Clock enable register */
#define RCC_AHB3ENR_MDMAEN_SHIFT (0ul) /* RCC AHB3ENR: MDMAEN (Bit 0) */
#define RCC_AHB3ENR_MDMAEN (0x1ul) /* RCC AHB3ENR: MDMAEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_DMA2DEN_SHIFT (4ul) /* RCC AHB3ENR: DMA2DEN (Bit 4) */
#define RCC_AHB3ENR_DMA2DEN (0x10ul) /* RCC AHB3ENR: DMA2DEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_JPGDECEN_SHIFT (5ul) /* RCC AHB3ENR: JPGDECEN (Bit 5) */
#define RCC_AHB3ENR_JPGDECEN (0x20ul) /* RCC AHB3ENR: JPGDECEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_FMCEN_SHIFT (12ul) /* RCC AHB3ENR: FMCEN (Bit 12) */
#define RCC_AHB3ENR_FMCEN (0x1000ul) /* RCC AHB3ENR: FMCEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_QSPIEN_SHIFT (14ul) /* RCC AHB3ENR: QSPIEN (Bit 14) */
#define RCC_AHB3ENR_QSPIEN (0x4000ul) /* RCC AHB3ENR: QSPIEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_SDMMC1EN_SHIFT (16ul) /* RCC AHB3ENR: SDMMC1EN (Bit 16) */
#define RCC_AHB3ENR_SDMMC1EN (0x10000ul) /* RCC AHB3ENR: SDMMC1EN (Bitfield-Mask: 0x01) */
#define RCC_AHB3ENR_MDMAEN (0x1ul) /* RCC AHB3ENR: MDMAEN */
#define RCC_AHB3ENR_DMA2DEN (0x10ul) /* RCC AHB3ENR: DMA2DEN */
#define RCC_AHB3ENR_JPGDECEN (0x20ul) /* RCC AHB3ENR: JPGDECEN */
#define RCC_AHB3ENR_FMCEN (0x1000ul) /* RCC AHB3ENR: FMCEN */
#define RCC_AHB3ENR_QSPIEN (0x4000ul) /* RCC AHB3ENR: QSPIEN */
#define RCC_AHB3ENR_SDMMC1EN (0x10000ul) /* RCC AHB3ENR: SDMMC1EN */
/* AHB1 Peripheral Clock enable register */
#define RCC_AHB1ENR_DMA1EN_SHIFT (0ul) /* RCC AHB1ENR: DMA1EN (Bit 0) */
#define RCC_AHB1ENR_DMA1EN (0x1ul) /* RCC AHB1ENR: DMA1EN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_DMA2EN_SHIFT (1ul) /* RCC AHB1ENR: DMA2EN (Bit 1) */
#define RCC_AHB1ENR_DMA2EN (0x2ul) /* RCC AHB1ENR: DMA2EN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_ADC12EN_SHIFT (5ul) /* RCC AHB1ENR: ADC12EN (Bit 5) */
#define RCC_AHB1ENR_ADC12EN (0x20ul) /* RCC AHB1ENR: ADC12EN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_ETH1MACEN_SHIFT (15ul) /* RCC AHB1ENR: ETH1MACEN (Bit 15) */
#define RCC_AHB1ENR_ETH1MACEN (0x8000ul) /* RCC AHB1ENR: ETH1MACEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_ETH1TXEN_SHIFT (16ul) /* RCC AHB1ENR: ETH1TXEN (Bit 16) */
#define RCC_AHB1ENR_ETH1TXEN (0x10000ul) /* RCC AHB1ENR: ETH1TXEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_ETH1RXEN_SHIFT (17ul) /* RCC AHB1ENR: ETH1RXEN (Bit 17) */
#define RCC_AHB1ENR_ETH1RXEN (0x20000ul) /* RCC AHB1ENR: ETH1RXEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_USB1OTGEN_SHIFT (25ul) /* RCC AHB1ENR: USB1OTGEN (Bit 25) */
#define RCC_AHB1ENR_USB1OTGEN (0x2000000ul) /* RCC AHB1ENR: USB1OTGEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_USB1ULPIEN_SHIFT (26ul) /* RCC AHB1ENR: USB1ULPIEN (Bit 26) */
#define RCC_AHB1ENR_USB1ULPIEN (0x4000000ul) /* RCC AHB1ENR: USB1ULPIEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_USB2OTGEN_SHIFT (27ul) /* RCC AHB1ENR: USB2OTGEN (Bit 27) */
#define RCC_AHB1ENR_USB2OTGEN (0x8000000ul) /* RCC AHB1ENR: USB2OTGEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_USB2ULPIEN_SHIFT (28ul) /* RCC AHB1ENR: USB2ULPIEN (Bit 28) */
#define RCC_AHB1ENR_USB2ULPIEN (0x10000000ul) /* RCC AHB1ENR: USB2ULPIEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1ENR_DMA1EN (0x1ul) /* RCC AHB1ENR: DMA1EN */
#define RCC_AHB1ENR_DMA2EN (0x2ul) /* RCC AHB1ENR: DMA2EN */
#define RCC_AHB1ENR_ADC12EN (0x20ul) /* RCC AHB1ENR: ADC12EN */
#define RCC_AHB1ENR_ETH1MACEN (0x8000ul) /* RCC AHB1ENR: ETH1MACEN */
#define RCC_AHB1ENR_ETH1TXEN (0x10000ul) /* RCC AHB1ENR: ETH1TXEN */
#define RCC_AHB1ENR_ETH1RXEN (0x20000ul) /* RCC AHB1ENR: ETH1RXEN */
#define RCC_AHB1ENR_USB1OTGEN (0x2000000ul) /* RCC AHB1ENR: USB1OTGEN */
#define RCC_AHB1ENR_USB1ULPIEN (0x4000000ul) /* RCC AHB1ENR: USB1ULPIEN */
#define RCC_AHB1ENR_USB2OTGEN (0x8000000ul) /* RCC AHB1ENR: USB2OTGEN */
#define RCC_AHB1ENR_USB2ULPIEN (0x10000000ul) /* RCC AHB1ENR: USB2ULPIEN */
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_CAMITFEN_SHIFT (0ul) /* RCC AHB2ENR: CAMITFEN (Bit 0) */
#define RCC_AHB2ENR_CAMITFEN (0x1ul) /* RCC AHB2ENR: CAMITFEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_CRYPTEN_SHIFT (4ul) /* RCC AHB2ENR: CRYPTEN (Bit 4) */
#define RCC_AHB2ENR_CRYPTEN (0x10ul) /* RCC AHB2ENR: CRYPTEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_HASHEN_SHIFT (5ul) /* RCC AHB2ENR: HASHEN (Bit 5) */
#define RCC_AHB2ENR_HASHEN (0x20ul) /* RCC AHB2ENR: HASHEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_RNGEN_SHIFT (6ul) /* RCC AHB2ENR: RNGEN (Bit 6) */
#define RCC_AHB2ENR_RNGEN (0x40ul) /* RCC AHB2ENR: RNGEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_SDMMC2EN_SHIFT (9ul) /* RCC AHB2ENR: SDMMC2EN (Bit 9) */
#define RCC_AHB2ENR_SDMMC2EN (0x200ul) /* RCC AHB2ENR: SDMMC2EN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_SRAM1EN_SHIFT (29ul) /* RCC AHB2ENR: SRAM1EN (Bit 29) */
#define RCC_AHB2ENR_SRAM1EN (0x20000000ul) /* RCC AHB2ENR: SRAM1EN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_SRAM2EN_SHIFT (30ul) /* RCC AHB2ENR: SRAM2EN (Bit 30) */
#define RCC_AHB2ENR_SRAM2EN (0x40000000ul) /* RCC AHB2ENR: SRAM2EN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_SRAM3EN_SHIFT (31ul) /* RCC AHB2ENR: SRAM3EN (Bit 31) */
#define RCC_AHB2ENR_SRAM3EN (0x80000000ul) /* RCC AHB2ENR: SRAM3EN (Bitfield-Mask: 0x01) */
#define RCC_AHB2ENR_CAMITFEN (0x1ul) /* RCC AHB2ENR: CAMITFEN */
#define RCC_AHB2ENR_CRYPTEN (0x10ul) /* RCC AHB2ENR: CRYPTEN */
#define RCC_AHB2ENR_HASHEN (0x20ul) /* RCC AHB2ENR: HASHEN */
#define RCC_AHB2ENR_RNGEN (0x40ul) /* RCC AHB2ENR: RNGEN */
#define RCC_AHB2ENR_SDMMC2EN (0x200ul) /* RCC AHB2ENR: SDMMC2EN */
#define RCC_AHB2ENR_SRAM1EN (0x20000000ul) /* RCC AHB2ENR: SRAM1EN */
#define RCC_AHB2ENR_SRAM2EN (0x40000000ul) /* RCC AHB2ENR: SRAM2EN */
#define RCC_AHB2ENR_SRAM3EN (0x80000000ul) /* RCC AHB2ENR: SRAM3EN */
/* AHB4 Peripheral Clock enable register */
#define RCC_AHB4ENR_GPIOAEN_SHIFT (0ul) /* RCC AHB4ENR: GPIOAEN (Bit 0) */
#define RCC_AHB4ENR_GPIOAEN (0x1ul) /* RCC AHB4ENR: GPIOAEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOBEN_SHIFT (1ul) /* RCC AHB4ENR: GPIOBEN (Bit 1) */
#define RCC_AHB4ENR_GPIOBEN (0x2ul) /* RCC AHB4ENR: GPIOBEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOCEN_SHIFT (2ul) /* RCC AHB4ENR: GPIOCEN (Bit 2) */
#define RCC_AHB4ENR_GPIOCEN (0x4ul) /* RCC AHB4ENR: GPIOCEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIODEN_SHIFT (3ul) /* RCC AHB4ENR: GPIODEN (Bit 3) */
#define RCC_AHB4ENR_GPIODEN (0x8ul) /* RCC AHB4ENR: GPIODEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOEEN_SHIFT (4ul) /* RCC AHB4ENR: GPIOEEN (Bit 4) */
#define RCC_AHB4ENR_GPIOEEN (0x10ul) /* RCC AHB4ENR: GPIOEEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOFEN_SHIFT (5ul) /* RCC AHB4ENR: GPIOFEN (Bit 5) */
#define RCC_AHB4ENR_GPIOFEN (0x20ul) /* RCC AHB4ENR: GPIOFEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOGEN_SHIFT (6ul) /* RCC AHB4ENR: GPIOGEN (Bit 6) */
#define RCC_AHB4ENR_GPIOGEN (0x40ul) /* RCC AHB4ENR: GPIOGEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOHEN_SHIFT (7ul) /* RCC AHB4ENR: GPIOHEN (Bit 7) */
#define RCC_AHB4ENR_GPIOHEN (0x80ul) /* RCC AHB4ENR: GPIOHEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOIEN_SHIFT (8ul) /* RCC AHB4ENR: GPIOIEN (Bit 8) */
#define RCC_AHB4ENR_GPIOIEN (0x100ul) /* RCC AHB4ENR: GPIOIEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOJEN_SHIFT (9ul) /* RCC AHB4ENR: GPIOJEN (Bit 9) */
#define RCC_AHB4ENR_GPIOJEN (0x200ul) /* RCC AHB4ENR: GPIOJEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOKEN_SHIFT (10ul) /* RCC AHB4ENR: GPIOKEN (Bit 10) */
#define RCC_AHB4ENR_GPIOKEN (0x400ul) /* RCC AHB4ENR: GPIOKEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_CRCEN_SHIFT (19ul) /* RCC AHB4ENR: CRCEN (Bit 19) */
#define RCC_AHB4ENR_CRCEN (0x80000ul) /* RCC AHB4ENR: CRCEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_BDMAEN_SHIFT (21ul) /* RCC AHB4ENR: BDMAEN (Bit 21) */
#define RCC_AHB4ENR_BDMAEN (0x200000ul) /* RCC AHB4ENR: BDMAEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_ADC3EN_SHIFT (24ul) /* RCC AHB4ENR: ADC3EN (Bit 24) */
#define RCC_AHB4ENR_ADC3EN (0x1000000ul) /* RCC AHB4ENR: ADC3EN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_HSEMEN_SHIFT (25ul) /* RCC AHB4ENR: HSEMEN (Bit 25) */
#define RCC_AHB4ENR_HSEMEN (0x2000000ul) /* RCC AHB4ENR: HSEMEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_BKPRAMEN_SHIFT (28ul) /* RCC AHB4ENR: BKPRAMEN (Bit 28) */
#define RCC_AHB4ENR_BKPRAMEN (0x10000000ul) /* RCC AHB4ENR: BKPRAMEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4ENR_GPIOAEN (0x1ul) /* RCC AHB4ENR: GPIOAEN */
#define RCC_AHB4ENR_GPIOBEN (0x2ul) /* RCC AHB4ENR: GPIOBEN */
#define RCC_AHB4ENR_GPIOCEN (0x4ul) /* RCC AHB4ENR: GPIOCEN */
#define RCC_AHB4ENR_GPIODEN (0x8ul) /* RCC AHB4ENR: GPIODEN */
#define RCC_AHB4ENR_GPIOEEN (0x10ul) /* RCC AHB4ENR: GPIOEEN */
#define RCC_AHB4ENR_GPIOFEN (0x20ul) /* RCC AHB4ENR: GPIOFEN */
#define RCC_AHB4ENR_GPIOGEN (0x40ul) /* RCC AHB4ENR: GPIOGEN */
#define RCC_AHB4ENR_GPIOHEN (0x80ul) /* RCC AHB4ENR: GPIOHEN */
#define RCC_AHB4ENR_GPIOIEN (0x100ul) /* RCC AHB4ENR: GPIOIEN */
#define RCC_AHB4ENR_GPIOJEN (0x200ul) /* RCC AHB4ENR: GPIOJEN */
#define RCC_AHB4ENR_GPIOKEN (0x400ul) /* RCC AHB4ENR: GPIOKEN */
#define RCC_AHB4ENR_CRCEN (0x80000ul) /* RCC AHB4ENR: CRCEN */
#define RCC_AHB4ENR_BDMAEN (0x200000ul) /* RCC AHB4ENR: BDMAEN */
#define RCC_AHB4ENR_ADC3EN (0x1000000ul) /* RCC AHB4ENR: ADC3EN */
#define RCC_AHB4ENR_HSEMEN (0x2000000ul) /* RCC AHB4ENR: HSEMEN */
#define RCC_AHB4ENR_BKPRAMEN (0x10000000ul) /* RCC AHB4ENR: BKPRAMEN */
/* APB3 Peripheral Clock enable register */
#define RCC_APB3ENR_LTDCEN_SHIFT (3ul) /* RCC APB3ENR: LTDCEN (Bit 3) */
#define RCC_APB3ENR_LTDCEN (0x8ul) /* RCC APB3ENR: LTDCEN (Bitfield-Mask: 0x01) */
#define RCC_APB3ENR_WWDG1EN_SHIFT (6ul) /* RCC APB3ENR: WWDG1EN (Bit 6) */
#define RCC_APB3ENR_WWDG1EN (0x40ul) /* RCC APB3ENR: WWDG1EN (Bitfield-Mask: 0x01) */
#define RCC_APB3ENR_LTDCEN (0x8ul) /* RCC APB3ENR: LTDCEN */
#define RCC_APB3ENR_WWDG1EN (0x40ul) /* RCC APB3ENR: WWDG1EN */
/* APB1 L Peripheral Clock enable register */
#define RCC_APB1LENR_TIM2EN_SHIFT (0ul) /* RCC APB1LENR: TIM2EN (Bit 0) */
#define RCC_APB1LENR_TIM2EN (0x1ul) /* RCC APB1LENR: TIM2EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM3EN_SHIFT (1ul) /* RCC APB1LENR: TIM3EN (Bit 1) */
#define RCC_APB1LENR_TIM3EN (0x2ul) /* RCC APB1LENR: TIM3EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM4EN_SHIFT (2ul) /* RCC APB1LENR: TIM4EN (Bit 2) */
#define RCC_APB1LENR_TIM4EN (0x4ul) /* RCC APB1LENR: TIM4EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM5EN_SHIFT (3ul) /* RCC APB1LENR: TIM5EN (Bit 3) */
#define RCC_APB1LENR_TIM5EN (0x8ul) /* RCC APB1LENR: TIM5EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM6EN_SHIFT (4ul) /* RCC APB1LENR: TIM6EN (Bit 4) */
#define RCC_APB1LENR_TIM6EN (0x10ul) /* RCC APB1LENR: TIM6EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM7EN_SHIFT (5ul) /* RCC APB1LENR: TIM7EN (Bit 5) */
#define RCC_APB1LENR_TIM7EN (0x20ul) /* RCC APB1LENR: TIM7EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM12EN_SHIFT (6ul) /* RCC APB1LENR: TIM12EN (Bit 6) */
#define RCC_APB1LENR_TIM12EN (0x40ul) /* RCC APB1LENR: TIM12EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM13EN_SHIFT (7ul) /* RCC APB1LENR: TIM13EN (Bit 7) */
#define RCC_APB1LENR_TIM13EN (0x80ul) /* RCC APB1LENR: TIM13EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM14EN_SHIFT (8ul) /* RCC APB1LENR: TIM14EN (Bit 8) */
#define RCC_APB1LENR_TIM14EN (0x100ul) /* RCC APB1LENR: TIM14EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_LPTIM1EN_SHIFT (9ul) /* RCC APB1LENR: LPTIM1EN (Bit 9) */
#define RCC_APB1LENR_LPTIM1EN (0x200ul) /* RCC APB1LENR: LPTIM1EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_SPI2EN_SHIFT (14ul) /* RCC APB1LENR: SPI2EN (Bit 14) */
#define RCC_APB1LENR_SPI2EN (0x4000ul) /* RCC APB1LENR: SPI2EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_SPI3EN_SHIFT (15ul) /* RCC APB1LENR: SPI3EN (Bit 15) */
#define RCC_APB1LENR_SPI3EN (0x8000ul) /* RCC APB1LENR: SPI3EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_SPDIFRXEN_SHIFT (16ul) /* RCC APB1LENR: SPDIFRXEN (Bit 16) */
#define RCC_APB1LENR_SPDIFRXEN (0x10000ul) /* RCC APB1LENR: SPDIFRXEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_USART2EN_SHIFT (17ul) /* RCC APB1LENR: USART2EN (Bit 17) */
#define RCC_APB1LENR_USART2EN (0x20000ul) /* RCC APB1LENR: USART2EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_USART3EN_SHIFT (18ul) /* RCC APB1LENR: USART3EN (Bit 18) */
#define RCC_APB1LENR_USART3EN (0x40000ul) /* RCC APB1LENR: USART3EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_UART4EN_SHIFT (19ul) /* RCC APB1LENR: UART4EN (Bit 19) */
#define RCC_APB1LENR_UART4EN (0x80000ul) /* RCC APB1LENR: UART4EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_UART5EN_SHIFT (20ul) /* RCC APB1LENR: UART5EN (Bit 20) */
#define RCC_APB1LENR_UART5EN (0x100000ul) /* RCC APB1LENR: UART5EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_I2C1EN_SHIFT (21ul) /* RCC APB1LENR: I2C1EN (Bit 21) */
#define RCC_APB1LENR_I2C1EN (0x200000ul) /* RCC APB1LENR: I2C1EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_I2C2EN_SHIFT (22ul) /* RCC APB1LENR: I2C2EN (Bit 22) */
#define RCC_APB1LENR_I2C2EN (0x400000ul) /* RCC APB1LENR: I2C2EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_I2C3EN_SHIFT (23ul) /* RCC APB1LENR: I2C3EN (Bit 23) */
#define RCC_APB1LENR_I2C3EN (0x800000ul) /* RCC APB1LENR: I2C3EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_HDMICECEN_SHIFT (27ul) /* RCC APB1LENR: HDMICECEN (Bit 27) */
#define RCC_APB1LENR_HDMICECEN (0x8000000ul) /* RCC APB1LENR: HDMICECEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_DAC12EN_SHIFT (29ul) /* RCC APB1LENR: DAC12EN (Bit 29) */
#define RCC_APB1LENR_DAC12EN (0x20000000ul) /* RCC APB1LENR: DAC12EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_USART7EN_SHIFT (30ul) /* RCC APB1LENR: USART7EN (Bit 30) */
#define RCC_APB1LENR_USART7EN (0x40000000ul) /* RCC APB1LENR: USART7EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_USART8EN_SHIFT (31ul) /* RCC APB1LENR: USART8EN (Bit 31) */
#define RCC_APB1LENR_USART8EN (0x80000000ul) /* RCC APB1LENR: USART8EN (Bitfield-Mask: 0x01) */
#define RCC_APB1LENR_TIM2EN (1 << 0) /* RCC APB1LENR: TIM2EN */
#define RCC_APB1LENR_TIM3EN (1 << 1) /* RCC APB1LENR: TIM3EN */
#define RCC_APB1LENR_TIM4EN (1 << 2) /* RCC APB1LENR: TIM4EN */
#define RCC_APB1LENR_TIM5EN (1 << 3) /* RCC APB1LENR: TIM5EN */
#define RCC_APB1LENR_TIM6EN (1 << 4) /* RCC APB1LENR: TIM6EN */
#define RCC_APB1LENR_TIM7EN (1 << 5) /* RCC APB1LENR: TIM7EN */
#define RCC_APB1LENR_TIM12EN (1 << 6) /* RCC APB1LENR: TIM12EN */
#define RCC_APB1LENR_TIM13EN (1 << 7) /* RCC APB1LENR: TIM13EN */
#define RCC_APB1LENR_TIM14EN (1 << 8) /* RCC APB1LENR: TIM14EN */
#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* RCC APB1LENR: LPTIM1EN */
/* Bits 10-13: Reserved */
#define RCC_APB1LENR_SPI2EN (1 << 14) /* RCC APB1LENR: SPI2EN */
#define RCC_APB1LENR_SPI3EN (1 << 15) /* RCC APB1LENR: SPI3EN */
#define RCC_APB1LENR_SPDIFRXEN (1 << 16) /* RCC APB1LENR: SPDIFRXEN */
#define RCC_APB1LENR_USART2EN (1 << 17) /* RCC APB1LENR: USART2EN */
#define RCC_APB1LENR_USART3EN (1 << 18) /* RCC APB1LENR: USART3EN */
#define RCC_APB1LENR_UART4EN (1 << 19) /* RCC APB1LENR: UART4EN */
#define RCC_APB1LENR_UART5EN (1 << 20) /* RCC APB1LENR: UART5EN */
#define RCC_APB1LENR_I2C1EN (1 << 21) /* RCC APB1LENR: I2C1EN */
#define RCC_APB1LENR_I2C2EN (1 << 22) /* RCC APB1LENR: I2C2EN */
#define RCC_APB1LENR_I2C3EN (1 << 23) /* RCC APB1LENR: I2C3EN */
/* Bits 24-25: Reserved */
#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */
/* Bit 28: Reserved */
#define RCC_APB1LENR_DAC12EN (1 << 29) /* RCC APB1LENR: DAC12EN */
#define RCC_APB1LENR_USART7EN (1 << 30) /* RCC APB1LENR: USART7EN */
#define RCC_APB1LENR_USART8EN (1 << 31) /* RCC APB1LENR: USART8EN */
/* APB1 H Peripheral Clock enable register */
#define RCC_APB1HENR_CRSEN_SHIFT (1ul) /* RCC APB1HENR: CRSEN (Bit 1) */
#define RCC_APB1HENR_CRSEN (0x2ul) /* RCC APB1HENR: CRSEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HENR_SWPEN_SHIFT (2ul) /* RCC APB1HENR: SWPEN (Bit 2) */
#define RCC_APB1HENR_SWPEN (0x4ul) /* RCC APB1HENR: SWPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HENR_OPAMPEN_SHIFT (4ul) /* RCC APB1HENR: OPAMPEN (Bit 4) */
#define RCC_APB1HENR_OPAMPEN (0x10ul) /* RCC APB1HENR: OPAMPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HENR_MDIOSEN_SHIFT (5ul) /* RCC APB1HENR: MDIOSEN (Bit 5) */
#define RCC_APB1HENR_MDIOSEN (0x20ul) /* RCC APB1HENR: MDIOSEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HENR_FDCANEN_SHIFT (8ul) /* RCC APB1HENR: FDCANEN (Bit 8) */
#define RCC_APB1HENR_FDCANEN (0x100ul) /* RCC APB1HENR: FDCANEN (Bitfield-Mask: 0x01) */
/* Bit 0: Reserved */
#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */
#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */
/* Bit 3: Reserved */
#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */
#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */
/* Bits 6-7: Reserved */
#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */
/* Bits 9-31: Reserved */
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_TIM1EN_SHIFT (0ul) /* RCC APB2ENR: TIM1EN (Bit 0) */
#define RCC_APB2ENR_TIM1EN (0x1ul) /* RCC APB2ENR: TIM1EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_TIM8EN_SHIFT (1ul) /* RCC APB2ENR: TIM8EN (Bit 1) */
#define RCC_APB2ENR_TIM8EN (0x2ul) /* RCC APB2ENR: TIM8EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_USART1EN_SHIFT (4ul) /* RCC APB2ENR: USART1EN (Bit 4) */
#define RCC_APB2ENR_USART1EN (0x10ul) /* RCC APB2ENR: USART1EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_USART6EN_SHIFT (5ul) /* RCC APB2ENR: USART6EN (Bit 5) */
#define RCC_APB2ENR_USART6EN (0x20ul) /* RCC APB2ENR: USART6EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SPI1EN_SHIFT (12ul) /* RCC APB2ENR: SPI1EN (Bit 12) */
#define RCC_APB2ENR_SPI1EN (0x1000ul) /* RCC APB2ENR: SPI1EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SPI4EN_SHIFT (13ul) /* RCC APB2ENR: SPI4EN (Bit 13) */
#define RCC_APB2ENR_SPI4EN (0x2000ul) /* RCC APB2ENR: SPI4EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_TIM16EN_SHIFT (17ul) /* RCC APB2ENR: TIM16EN (Bit 17) */
#define RCC_APB2ENR_TIM16EN (0x20000ul) /* RCC APB2ENR: TIM16EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_TIM15EN_SHIFT (16ul) /* RCC APB2ENR: TIM15EN (Bit 16) */
#define RCC_APB2ENR_TIM15EN (0x10000ul) /* RCC APB2ENR: TIM15EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_TIM17EN_SHIFT (18ul) /* RCC APB2ENR: TIM17EN (Bit 18) */
#define RCC_APB2ENR_TIM17EN (0x40000ul) /* RCC APB2ENR: TIM17EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SPI5EN_SHIFT (20ul) /* RCC APB2ENR: SPI5EN (Bit 20) */
#define RCC_APB2ENR_SPI5EN (0x100000ul) /* RCC APB2ENR: SPI5EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SAI1EN_SHIFT (22ul) /* RCC APB2ENR: SAI1EN (Bit 22) */
#define RCC_APB2ENR_SAI1EN (0x400000ul) /* RCC APB2ENR: SAI1EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SAI2EN_SHIFT (23ul) /* RCC APB2ENR: SAI2EN (Bit 23) */
#define RCC_APB2ENR_SAI2EN (0x800000ul) /* RCC APB2ENR: SAI2EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_SAI3EN_SHIFT (24ul) /* RCC APB2ENR: SAI3EN (Bit 24) */
#define RCC_APB2ENR_SAI3EN (0x1000000ul) /* RCC APB2ENR: SAI3EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_DFSDM1EN_SHIFT (28ul) /* RCC APB2ENR: DFSDM1EN (Bit 28) */
#define RCC_APB2ENR_DFSDM1EN (0x10000000ul) /* RCC APB2ENR: DFSDM1EN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_HRTIMEN_SHIFT (29ul) /* RCC APB2ENR: HRTIMEN (Bit 29) */
#define RCC_APB2ENR_HRTIMEN (0x20000000ul) /* RCC APB2ENR: HRTIMEN (Bitfield-Mask: 0x01) */
#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */
#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */
/* Bits 2-3: Reserved */
#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */
#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */
/* Bits 6-11: Reserved */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */
#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */
/* Bits 14-15: Reserved */
#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */
#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */
#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */
#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */
/* Bit 21: Reserved */
#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */
#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */
#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */
/* Bits 25-27: Reserved */
#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */
#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */
/* Bits 30-31: Reserved */
/* APB4 Peripheral Clock enable register */
#define RCC_APB4ENR_SYSCFGEN_SHIFT (1ul) /* RCC APB4ENR: SYSCFGEN (Bit 1) */
#define RCC_APB4ENR_SYSCFGEN (0x2ul) /* RCC APB4ENR: SYSCFGEN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_LPUART1EN_SHIFT (3ul) /* RCC APB4ENR: LPUART1EN (Bit 3) */
#define RCC_APB4ENR_LPUART1EN (0x8ul) /* RCC APB4ENR: LPUART1EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_SPI6EN_SHIFT (5ul) /* RCC APB4ENR: SPI6EN (Bit 5) */
#define RCC_APB4ENR_SPI6EN (0x20ul) /* RCC APB4ENR: SPI6EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_I2C4EN_SHIFT (7ul) /* RCC APB4ENR: I2C4EN (Bit 7) */
#define RCC_APB4ENR_I2C4EN (0x80ul) /* RCC APB4ENR: I2C4EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_LPTIM2EN_SHIFT (9ul) /* RCC APB4ENR: LPTIM2EN (Bit 9) */
#define RCC_APB4ENR_LPTIM2EN (0x200ul) /* RCC APB4ENR: LPTIM2EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_LPTIM3EN_SHIFT (10ul) /* RCC APB4ENR: LPTIM3EN (Bit 10) */
#define RCC_APB4ENR_LPTIM3EN (0x400ul) /* RCC APB4ENR: LPTIM3EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_LPTIM4EN_SHIFT (11ul) /* RCC APB4ENR: LPTIM4EN (Bit 11) */
#define RCC_APB4ENR_LPTIM4EN (0x800ul) /* RCC APB4ENR: LPTIM4EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_LPTIM5EN_SHIFT (12ul) /* RCC APB4ENR: LPTIM5EN (Bit 12) */
#define RCC_APB4ENR_LPTIM5EN (0x1000ul) /* RCC APB4ENR: LPTIM5EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_COMP12EN_SHIFT (14ul) /* RCC APB4ENR: COMP12EN (Bit 14) */
#define RCC_APB4ENR_COMP12EN (0x4000ul) /* RCC APB4ENR: COMP12EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_VREFEN_SHIFT (15ul) /* RCC APB4ENR: VREFEN (Bit 15) */
#define RCC_APB4ENR_VREFEN (0x8000ul) /* RCC APB4ENR: VREFEN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_RTCAPBEN_SHIFT (16ul) /* RCC APB4ENR: RTCAPBEN (Bit 16) */
#define RCC_APB4ENR_RTCAPBEN (0x10000ul) /* RCC APB4ENR: RTCAPBEN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_SAI4EN_SHIFT (21ul) /* RCC APB4ENR: SAI4EN (Bit 21) */
#define RCC_APB4ENR_SAI4EN (0x200000ul) /* RCC APB4ENR: SAI4EN (Bitfield-Mask: 0x01) */
#define RCC_APB4ENR_SYSCFGEN (0x2ul) /* RCC APB4ENR: SYSCFGEN */
#define RCC_APB4ENR_LPUART1EN (0x8ul) /* RCC APB4ENR: LPUART1EN */
#define RCC_APB4ENR_SPI6EN (0x20ul) /* RCC APB4ENR: SPI6EN */
#define RCC_APB4ENR_I2C4EN (0x80ul) /* RCC APB4ENR: I2C4EN */
#define RCC_APB4ENR_LPTIM2EN (0x200ul) /* RCC APB4ENR: LPTIM2EN */
#define RCC_APB4ENR_LPTIM3EN (0x400ul) /* RCC APB4ENR: LPTIM3EN */
#define RCC_APB4ENR_LPTIM4EN (0x800ul) /* RCC APB4ENR: LPTIM4EN */
#define RCC_APB4ENR_LPTIM5EN (0x1000ul) /* RCC APB4ENR: LPTIM5EN */
#define RCC_APB4ENR_COMP12EN (0x4000ul) /* RCC APB4ENR: COMP12EN */
#define RCC_APB4ENR_VREFEN (0x8000ul) /* RCC APB4ENR: VREFEN */
#define RCC_APB4ENR_RTCAPBEN (0x10000ul) /* RCC APB4ENR: RTCAPBEN */
#define RCC_APB4ENR_SAI4EN (0x200000ul) /* RCC APB4ENR: SAI4EN */
/* AHB3 low power mode peripheral clock enable register */
#define RCC_AHB3LPENR_MDMALPEN_SHIFT (0ul) /* RCC AHB3LPENR: MDMALPEN (Bit 0) */
#define RCC_AHB3LPENR_MDMALPEN (0x1ul) /* RCC AHB3LPENR: MDMALPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_DMA2DLPEN_SHIFT (4ul) /* RCC AHB3LPENR: DMA2DLPEN (Bit 4) */
#define RCC_AHB3LPENR_DMA2DLPEN (0x10ul) /* RCC AHB3LPENR: DMA2DLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_JPGDECLPEN_SHIFT (5ul) /* RCC AHB3LPENR: JPGDECLPEN (Bit 5) */
#define RCC_AHB3LPENR_JPGDECLPEN (0x20ul) /* RCC AHB3LPENR: JPGDECLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_FLITFLPEN_SHIFT (8ul) /* RCC AHB3LPENR: FLITFLPEN (Bit 8) */
#define RCC_AHB3LPENR_FLITFLPEN (0x100ul) /* RCC AHB3LPENR: FLITFLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_FMCLPEN_SHIFT (12ul) /* RCC AHB3LPENR: FMCLPEN (Bit 12) */
#define RCC_AHB3LPENR_FMCLPEN (0x1000ul) /* RCC AHB3LPENR: FMCLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_QSPILPEN_SHIFT (14ul) /* RCC AHB3LPENR: QSPILPEN (Bit 14) */
#define RCC_AHB3LPENR_QSPILPEN (0x4000ul) /* RCC AHB3LPENR: QSPILPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_SDMMC1LPEN_SHIFT (16ul) /* RCC AHB3LPENR: SDMMC1LPEN (Bit 16) */
#define RCC_AHB3LPENR_SDMMC1LPEN (0x10000ul) /* RCC AHB3LPENR: SDMMC1LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_D1DTCM1LPEN_SHIFT (28ul) /* RCC AHB3LPENR: D1DTCM1LPEN (Bit 28) */
#define RCC_AHB3LPENR_D1DTCM1LPEN (0x10000000ul) /* RCC AHB3LPENR: D1DTCM1LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_DTCM2LPEN_SHIFT (29ul) /* RCC AHB3LPENR: DTCM2LPEN (Bit 29) */
#define RCC_AHB3LPENR_DTCM2LPEN (0x20000000ul) /* RCC AHB3LPENR: DTCM2LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_ITCMLPEN_SHIFT (30ul) /* RCC AHB3LPENR: ITCMLPEN (Bit 30) */
#define RCC_AHB3LPENR_ITCMLPEN (0x40000000ul) /* RCC AHB3LPENR: ITCMLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_AXISRAMLPEN_SHIFT (31ul) /* RCC AHB3LPENR: AXISRAMLPEN (Bit 31) */
#define RCC_AHB3LPENR_AXISRAMLPEN (0x80000000ul) /* RCC AHB3LPENR: AXISRAMLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB3LPENR_MDMALPEN (0x1ul) /* RCC AHB3LPENR: MDMALPEN */
#define RCC_AHB3LPENR_DMA2DLPEN (0x10ul) /* RCC AHB3LPENR: DMA2DLPEN */
#define RCC_AHB3LPENR_JPGDECLPEN (0x20ul) /* RCC AHB3LPENR: JPGDECLPEN */
#define RCC_AHB3LPENR_FLITFLPEN (0x100ul) /* RCC AHB3LPENR: FLITFLPEN */
#define RCC_AHB3LPENR_FMCLPEN (0x1000ul) /* RCC AHB3LPENR: FMCLPEN */
#define RCC_AHB3LPENR_QSPILPEN (0x4000ul) /* RCC AHB3LPENR: QSPILPEN */
#define RCC_AHB3LPENR_SDMMC1LPEN (0x10000ul) /* RCC AHB3LPENR: SDMMC1LPEN */
#define RCC_AHB3LPENR_D1DTCM1LPEN (0x10000000ul) /* RCC AHB3LPENR: D1DTCM1LPEN */
#define RCC_AHB3LPENR_DTCM2LPEN (0x20000000ul) /* RCC AHB3LPENR: DTCM2LPEN */
#define RCC_AHB3LPENR_ITCMLPEN (0x40000000ul) /* RCC AHB3LPENR: ITCMLPEN */
#define RCC_AHB3LPENR_AXISRAMLPEN (0x80000000ul) /* RCC AHB3LPENR: AXISRAMLPEN */
/* AHB1 low power mode peripheral clock enable register */
#define RCC_AHB1LPENR_DMA1LPEN_SHIFT (0ul) /* RCC AHB1LPENR: DMA1LPEN (Bit 0) */
#define RCC_AHB1LPENR_DMA1LPEN (0x1ul) /* RCC AHB1LPENR: DMA1LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_DMA2LPEN_SHIFT (1ul) /* RCC AHB1LPENR: DMA2LPEN (Bit 1) */
#define RCC_AHB1LPENR_DMA2LPEN (0x2ul) /* RCC AHB1LPENR: DMA2LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_ADC12LPEN_SHIFT (5ul) /* RCC AHB1LPENR: ADC12LPEN (Bit 5) */
#define RCC_AHB1LPENR_ADC12LPEN (0x20ul) /* RCC AHB1LPENR: ADC12LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_ETH1MACLPEN_SHIFT (15ul) /* RCC AHB1LPENR: ETH1MACLPEN (Bit 15) */
#define RCC_AHB1LPENR_ETH1MACLPEN (0x8000ul) /* RCC AHB1LPENR: ETH1MACLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_ETH1TXLPEN_SHIFT (16ul) /* RCC AHB1LPENR: ETH1TXLPEN (Bit 16) */
#define RCC_AHB1LPENR_ETH1TXLPEN (0x10000ul) /* RCC AHB1LPENR: ETH1TXLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_ETH1RXLPEN_SHIFT (17ul) /* RCC AHB1LPENR: ETH1RXLPEN (Bit 17) */
#define RCC_AHB1LPENR_ETH1RXLPEN (0x20000ul) /* RCC AHB1LPENR: ETH1RXLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_USB1OTGLPEN_SHIFT (25ul) /* RCC AHB1LPENR: USB1OTGLPEN (Bit 25) */
#define RCC_AHB1LPENR_USB1OTGLPEN (0x2000000ul) /* RCC AHB1LPENR: USB1OTGLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_USB1ULPILPEN_SHIFT (26ul) /* RCC AHB1LPENR: USB1ULPILPEN (Bit 26) */
#define RCC_AHB1LPENR_USB1ULPILPEN (0x4000000ul) /* RCC AHB1LPENR: USB1ULPILPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_USB2OTGLPEN_SHIFT (27ul) /* RCC AHB1LPENR: USB2OTGLPEN (Bit 27) */
#define RCC_AHB1LPENR_USB2OTGLPEN (0x8000000ul) /* RCC AHB1LPENR: USB2OTGLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_USB2ULPILPEN_SHIFT (28ul) /* RCC AHB1LPENR: USB2ULPILPEN (Bit 28) */
#define RCC_AHB1LPENR_USB2ULPILPEN (0x10000000ul) /* RCC AHB1LPENR: USB2ULPILPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB1LPENR_DMA1LPEN (0x1ul) /* RCC AHB1LPENR: DMA1LPEN */
#define RCC_AHB1LPENR_DMA2LPEN (0x2ul) /* RCC AHB1LPENR: DMA2LPEN */
#define RCC_AHB1LPENR_ADC12LPEN (0x20ul) /* RCC AHB1LPENR: ADC12LPEN */
#define RCC_AHB1LPENR_ETH1MACLPEN (0x8000ul) /* RCC AHB1LPENR: ETH1MACLPEN */
#define RCC_AHB1LPENR_ETH1TXLPEN (0x10000ul) /* RCC AHB1LPENR: ETH1TXLPEN */
#define RCC_AHB1LPENR_ETH1RXLPEN (0x20000ul) /* RCC AHB1LPENR: ETH1RXLPEN */
#define RCC_AHB1LPENR_USB1OTGLPEN (0x2000000ul) /* RCC AHB1LPENR: USB1OTGLPEN */
#define RCC_AHB1LPENR_USB1ULPILPEN (0x4000000ul) /* RCC AHB1LPENR: USB1ULPILPEN */
#define RCC_AHB1LPENR_USB2OTGLPEN (0x8000000ul) /* RCC AHB1LPENR: USB2OTGLPEN */
#define RCC_AHB1LPENR_USB2ULPILPEN (0x10000000ul) /* RCC AHB1LPENR: USB2ULPILPEN */
/* AHB2 low power mode peripheral clock enable register */
#define RCC_AHB2LPENR_CAMITFLPEN_SHIFT (0ul) /* RCC AHB2LPENR: CAMITFLPEN (Bit 0) */
#define RCC_AHB2LPENR_CAMITFLPEN (0x1ul) /* RCC AHB2LPENR: CAMITFLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_CRYPTLPEN_SHIFT (4ul) /* RCC AHB2LPENR: CRYPTLPEN (Bit 4) */
#define RCC_AHB2LPENR_CRYPTLPEN (0x10ul) /* RCC AHB2LPENR: CRYPTLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_HASHLPEN_SHIFT (5ul) /* RCC AHB2LPENR: HASHLPEN (Bit 5) */
#define RCC_AHB2LPENR_HASHLPEN (0x20ul) /* RCC AHB2LPENR: HASHLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_SDMMC2LPEN_SHIFT (9ul) /* RCC AHB2LPENR: SDMMC2LPEN (Bit 9) */
#define RCC_AHB2LPENR_SDMMC2LPEN (0x200ul) /* RCC AHB2LPENR: SDMMC2LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_RNGLPEN_SHIFT (6ul) /* RCC AHB2LPENR: RNGLPEN (Bit 6) */
#define RCC_AHB2LPENR_RNGLPEN (0x40ul) /* RCC AHB2LPENR: RNGLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_SRAM1LPEN_SHIFT (29ul) /* RCC AHB2LPENR: SRAM1LPEN (Bit 29) */
#define RCC_AHB2LPENR_SRAM1LPEN (0x20000000ul) /* RCC AHB2LPENR: SRAM1LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_SRAM2LPEN_SHIFT (30ul) /* RCC AHB2LPENR: SRAM2LPEN (Bit 30) */
#define RCC_AHB2LPENR_SRAM2LPEN (0x40000000ul) /* RCC AHB2LPENR: SRAM2LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_SRAM3LPEN_SHIFT (31ul) /* RCC AHB2LPENR: SRAM3LPEN (Bit 31) */
#define RCC_AHB2LPENR_SRAM3LPEN (0x80000000ul) /* RCC AHB2LPENR: SRAM3LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB2LPENR_CAMITFLPEN (0x1ul) /* RCC AHB2LPENR: CAMITFLPEN */
#define RCC_AHB2LPENR_CRYPTLPEN (0x10ul) /* RCC AHB2LPENR: CRYPTLPEN */
#define RCC_AHB2LPENR_HASHLPEN (0x20ul) /* RCC AHB2LPENR: HASHLPEN */
#define RCC_AHB2LPENR_SDMMC2LPEN (0x200ul) /* RCC AHB2LPENR: SDMMC2LPEN */
#define RCC_AHB2LPENR_RNGLPEN (0x40ul) /* RCC AHB2LPENR: RNGLPEN */
#define RCC_AHB2LPENR_SRAM1LPEN (0x20000000ul) /* RCC AHB2LPENR: SRAM1LPEN */
#define RCC_AHB2LPENR_SRAM2LPEN (0x40000000ul) /* RCC AHB2LPENR: SRAM2LPEN */
#define RCC_AHB2LPENR_SRAM3LPEN (0x80000000ul) /* RCC AHB2LPENR: SRAM3LPEN */
/* AHB4 low power mode peripheral clock enable register*/
#define RCC_AHB4LPENR_GPIOALPEN_SHIFT (0ul) /* RCC AHB4LPENR: GPIOALPEN (Bit 0) */
#define RCC_AHB4LPENR_GPIOALPEN (0x1ul) /* RCC AHB4LPENR: GPIOALPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOBLPEN_SHIFT (1ul) /* RCC AHB4LPENR: GPIOBLPEN (Bit 1) */
#define RCC_AHB4LPENR_GPIOBLPEN (0x2ul) /* RCC AHB4LPENR: GPIOBLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOCLPEN_SHIFT (2ul) /* RCC AHB4LPENR: GPIOCLPEN (Bit 2) */
#define RCC_AHB4LPENR_GPIOCLPEN (0x4ul) /* RCC AHB4LPENR: GPIOCLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIODLPEN_SHIFT (3ul) /* RCC AHB4LPENR: GPIODLPEN (Bit 3) */
#define RCC_AHB4LPENR_GPIODLPEN (0x8ul) /* RCC AHB4LPENR: GPIODLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOELPEN_SHIFT (4ul) /* RCC AHB4LPENR: GPIOELPEN (Bit 4) */
#define RCC_AHB4LPENR_GPIOELPEN (0x10ul) /* RCC AHB4LPENR: GPIOELPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOFLPEN_SHIFT (5ul) /* RCC AHB4LPENR: GPIOFLPEN (Bit 5) */
#define RCC_AHB4LPENR_GPIOFLPEN (0x20ul) /* RCC AHB4LPENR: GPIOFLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOGLPEN_SHIFT (6ul) /* RCC AHB4LPENR: GPIOGLPEN (Bit 6) */
#define RCC_AHB4LPENR_GPIOGLPEN (0x40ul) /* RCC AHB4LPENR: GPIOGLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOHLPEN_SHIFT (7ul) /* RCC AHB4LPENR: GPIOHLPEN (Bit 7) */
#define RCC_AHB4LPENR_GPIOHLPEN (0x80ul) /* RCC AHB4LPENR: GPIOHLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOILPEN_SHIFT (8ul) /* RCC AHB4LPENR: GPIOILPEN (Bit 8) */
#define RCC_AHB4LPENR_GPIOILPEN (0x100ul) /* RCC AHB4LPENR: GPIOILPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOJLPEN_SHIFT (9ul) /* RCC AHB4LPENR: GPIOJLPEN (Bit 9) */
#define RCC_AHB4LPENR_GPIOJLPEN (0x200ul) /* RCC AHB4LPENR: GPIOJLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOKLPEN_SHIFT (10ul) /* RCC AHB4LPENR: GPIOKLPEN (Bit 10) */
#define RCC_AHB4LPENR_GPIOKLPEN (0x400ul) /* RCC AHB4LPENR: GPIOKLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_CRCLPEN_SHIFT (19ul) /* RCC AHB4LPENR: CRCLPEN (Bit 19) */
#define RCC_AHB4LPENR_CRCLPEN (0x80000ul) /* RCC AHB4LPENR: CRCLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_BDMALPEN_SHIFT (21ul) /* RCC AHB4LPENR: BDMALPEN (Bit 21) */
#define RCC_AHB4LPENR_BDMALPEN (0x200000ul) /* RCC AHB4LPENR: BDMALPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_ADC3LPEN_SHIFT (24ul) /* RCC AHB4LPENR: ADC3LPEN (Bit 24) */
#define RCC_AHB4LPENR_ADC3LPEN (0x1000000ul) /* RCC AHB4LPENR: ADC3LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_BKPRAMLPEN_SHIFT (28ul) /* RCC AHB4LPENR: BKPRAMLPEN (Bit 28) */
#define RCC_AHB4LPENR_BKPRAMLPEN (0x10000000ul) /* RCC AHB4LPENR: BKPRAMLPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_SRAM4LPEN_SHIFT (29ul) /* RCC AHB4LPENR: SRAM4LPEN (Bit 29) */
#define RCC_AHB4LPENR_SRAM4LPEN (0x20000000ul) /* RCC AHB4LPENR: SRAM4LPEN (Bitfield-Mask: 0x01) */
#define RCC_AHB4LPENR_GPIOALPEN (0x1ul) /* RCC AHB4LPENR: GPIOALPEN */
#define RCC_AHB4LPENR_GPIOBLPEN (0x2ul) /* RCC AHB4LPENR: GPIOBLPEN */
#define RCC_AHB4LPENR_GPIOCLPEN (0x4ul) /* RCC AHB4LPENR: GPIOCLPEN */
#define RCC_AHB4LPENR_GPIODLPEN (0x8ul) /* RCC AHB4LPENR: GPIODLPEN */
#define RCC_AHB4LPENR_GPIOELPEN (0x10ul) /* RCC AHB4LPENR: GPIOELPEN */
#define RCC_AHB4LPENR_GPIOFLPEN (0x20ul) /* RCC AHB4LPENR: GPIOFLPEN */
#define RCC_AHB4LPENR_GPIOGLPEN (0x40ul) /* RCC AHB4LPENR: GPIOGLPEN */
#define RCC_AHB4LPENR_GPIOHLPEN (0x80ul) /* RCC AHB4LPENR: GPIOHLPEN */
#define RCC_AHB4LPENR_GPIOILPEN (0x100ul) /* RCC AHB4LPENR: GPIOILPEN */
#define RCC_AHB4LPENR_GPIOJLPEN (0x200ul) /* RCC AHB4LPENR: GPIOJLPEN */
#define RCC_AHB4LPENR_GPIOKLPEN (0x400ul) /* RCC AHB4LPENR: GPIOKLPEN */
#define RCC_AHB4LPENR_CRCLPEN (0x80000ul) /* RCC AHB4LPENR: CRCLPEN */
#define RCC_AHB4LPENR_BDMALPEN (0x200000ul) /* RCC AHB4LPENR: BDMALPEN */
#define RCC_AHB4LPENR_ADC3LPEN (0x1000000ul) /* RCC AHB4LPENR: ADC3LPEN */
#define RCC_AHB4LPENR_BKPRAMLPEN (0x10000000ul) /* RCC AHB4LPENR: BKPRAMLPEN */
#define RCC_AHB4LPENR_SRAM4LPEN (0x20000000ul) /* RCC AHB4LPENR: SRAM4LPEN */
/* APB3 low power mode peripheral clock enable register */
#define RCC_APB3LPENR_LTDCLPEN_SHIFT (3ul) /* RCC APB3LPENR: LTDCLPEN (Bit 3) */
#define RCC_APB3LPENR_LTDCLPEN (0x8ul) /* RCC APB3LPENR: LTDCLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB3LPENR_WWDG1LPEN_SHIFT (6ul) /* RCC APB3LPENR: WWDG1LPEN (Bit 6) */
#define RCC_APB3LPENR_WWDG1LPEN (0x40ul) /* RCC APB3LPENR: WWDG1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB3LPENR_LTDCLPEN (0x8ul) /* RCC APB3LPENR: LTDCLPEN */
#define RCC_APB3LPENR_WWDG1LPEN (0x40ul) /* RCC APB3LPENR: WWDG1LPEN */
/* APB1 L low power mode peripheral clock enable register */
#define RCC_APB1LLPENR_TIM2LPEN_SHIFT (0ul) /* RCC APB1LLPENR: TIM2LPEN (Bit 0) */
#define RCC_APB1LLPENR_TIM2LPEN (0x1ul) /* RCC APB1LLPENR: TIM2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM3LPEN_SHIFT (1ul) /* RCC APB1LLPENR: TIM3LPEN (Bit 1) */
#define RCC_APB1LLPENR_TIM3LPEN (0x2ul) /* RCC APB1LLPENR: TIM3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM4LPEN_SHIFT (2ul) /* RCC APB1LLPENR: TIM4LPEN (Bit 2) */
#define RCC_APB1LLPENR_TIM4LPEN (0x4ul) /* RCC APB1LLPENR: TIM4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM5LPEN_SHIFT (3ul) /* RCC APB1LLPENR: TIM5LPEN (Bit 3) */
#define RCC_APB1LLPENR_TIM5LPEN (0x8ul) /* RCC APB1LLPENR: TIM5LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM6LPEN_SHIFT (4ul) /* RCC APB1LLPENR: TIM6LPEN (Bit 4) */
#define RCC_APB1LLPENR_TIM6LPEN (0x10ul) /* RCC APB1LLPENR: TIM6LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM7LPEN_SHIFT (5ul) /* RCC APB1LLPENR: TIM7LPEN (Bit 5) */
#define RCC_APB1LLPENR_TIM7LPEN (0x20ul) /* RCC APB1LLPENR: TIM7LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM12LPEN_SHIFT (6ul) /* RCC APB1LLPENR: TIM12LPEN (Bit 6) */
#define RCC_APB1LLPENR_TIM12LPEN (0x40ul) /* RCC APB1LLPENR: TIM12LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM13LPEN_SHIFT (7ul) /* RCC APB1LLPENR: TIM13LPEN (Bit 7) */
#define RCC_APB1LLPENR_TIM13LPEN (0x80ul) /* RCC APB1LLPENR: TIM13LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM14LPEN_SHIFT (8ul) /* RCC APB1LLPENR: TIM14LPEN (Bit 8) */
#define RCC_APB1LLPENR_TIM14LPEN (0x100ul) /* RCC APB1LLPENR: TIM14LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_LPTIM1LPEN_SHIFT (9ul) /* RCC APB1LLPENR: LPTIM1LPEN (Bit 9) */
#define RCC_APB1LLPENR_LPTIM1LPEN (0x200ul) /* RCC APB1LLPENR: LPTIM1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_SPI2LPEN_SHIFT (14ul) /* RCC APB1LLPENR: SPI2LPEN (Bit 14) */
#define RCC_APB1LLPENR_SPI2LPEN (0x4000ul) /* RCC APB1LLPENR: SPI2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_SPI3LPEN_SHIFT (15ul) /* RCC APB1LLPENR: SPI3LPEN (Bit 15) */
#define RCC_APB1LLPENR_SPI3LPEN (0x8000ul) /* RCC APB1LLPENR: SPI3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_SPDIFRXLPEN_SHIFT (16ul) /* RCC APB1LLPENR: SPDIFRXLPEN (Bit 16) */
#define RCC_APB1LLPENR_SPDIFRXLPEN (0x10000ul) /* RCC APB1LLPENR: SPDIFRXLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_USART2LPEN_SHIFT (17ul) /* RCC APB1LLPENR: USART2LPEN (Bit 17) */
#define RCC_APB1LLPENR_USART2LPEN (0x20000ul) /* RCC APB1LLPENR: USART2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_USART3LPEN_SHIFT (18ul) /* RCC APB1LLPENR: USART3LPEN (Bit 18) */
#define RCC_APB1LLPENR_USART3LPEN (0x40000ul) /* RCC APB1LLPENR: USART3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_UART4LPEN_SHIFT (19ul) /* RCC APB1LLPENR: UART4LPEN (Bit 19) */
#define RCC_APB1LLPENR_UART4LPEN (0x80000ul) /* RCC APB1LLPENR: UART4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_UART5LPEN_SHIFT (20ul) /* RCC APB1LLPENR: UART5LPEN (Bit 20) */
#define RCC_APB1LLPENR_UART5LPEN (0x100000ul) /* RCC APB1LLPENR: UART5LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_I2C1LPEN_SHIFT (21ul) /* RCC APB1LLPENR: I2C1LPEN (Bit 21) */
#define RCC_APB1LLPENR_I2C1LPEN (0x200000ul) /* RCC APB1LLPENR: I2C1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_I2C2LPEN_SHIFT (22ul) /* RCC APB1LLPENR: I2C2LPEN (Bit 22) */
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_I2C3LPEN_SHIFT (23ul) /* RCC APB1LLPENR: I2C3LPEN (Bit 23) */
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_HDMICECLPEN_SHIFT (27ul) /* RCC APB1LLPENR: HDMICECLPEN (Bit 27) */
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_DAC12LPEN_SHIFT (29ul) /* RCC APB1LLPENR: DAC12LPEN (Bit 29) */
#define RCC_APB1LLPENR_DAC12LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC12LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_USART7LPEN_SHIFT (30ul) /* RCC APB1LLPENR: USART7LPEN (Bit 30) */
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_USART8LPEN_SHIFT (31ul) /* RCC APB1LLPENR: USART8LPEN (Bit 31) */
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1LLPENR_TIM2LPEN (0x1ul) /* RCC APB1LLPENR: TIM2LPEN */
#define RCC_APB1LLPENR_TIM3LPEN (0x2ul) /* RCC APB1LLPENR: TIM3LPEN */
#define RCC_APB1LLPENR_TIM4LPEN (0x4ul) /* RCC APB1LLPENR: TIM4LPEN */
#define RCC_APB1LLPENR_TIM5LPEN (0x8ul) /* RCC APB1LLPENR: TIM5LPEN */
#define RCC_APB1LLPENR_TIM6LPEN (0x10ul) /* RCC APB1LLPENR: TIM6LPEN */
#define RCC_APB1LLPENR_TIM7LPEN (0x20ul) /* RCC APB1LLPENR: TIM7LPEN */
#define RCC_APB1LLPENR_TIM12LPEN (0x40ul) /* RCC APB1LLPENR: TIM12LPEN */
#define RCC_APB1LLPENR_TIM13LPEN (0x80ul) /* RCC APB1LLPENR: TIM13LPEN */
#define RCC_APB1LLPENR_TIM14LPEN (0x100ul) /* RCC APB1LLPENR: TIM14LPEN */
#define RCC_APB1LLPENR_LPTIM1LPEN (0x200ul) /* RCC APB1LLPENR: LPTIM1LPEN */
#define RCC_APB1LLPENR_SPI2LPEN (0x4000ul) /* RCC APB1LLPENR: SPI2LPEN */
#define RCC_APB1LLPENR_SPI3LPEN (0x8000ul) /* RCC APB1LLPENR: SPI3LPEN */
#define RCC_APB1LLPENR_SPDIFRXLPEN (0x10000ul) /* RCC APB1LLPENR: SPDIFRXLPEN */
#define RCC_APB1LLPENR_USART2LPEN (0x20000ul) /* RCC APB1LLPENR: USART2LPEN */
#define RCC_APB1LLPENR_USART3LPEN (0x40000ul) /* RCC APB1LLPENR: USART3LPEN */
#define RCC_APB1LLPENR_UART4LPEN (0x80000ul) /* RCC APB1LLPENR: UART4LPEN */
#define RCC_APB1LLPENR_UART5LPEN (0x100000ul) /* RCC APB1LLPENR: UART5LPEN */
#define RCC_APB1LLPENR_I2C1LPEN (0x200000ul) /* RCC APB1LLPENR: I2C1LPEN */
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN */
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN */
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN */
#define RCC_APB1LLPENR_DAC12LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC12LPEN */
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN */
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN */
/* APB1 H low power mode peripheral clock enable register */
#define RCC_APB1HLPENR_CRSLPEN_SHIFT (1ul) /* RCC APB1HLPENR: CRSLPEN (Bit 1) */
#define RCC_APB1HLPENR_CRSLPEN (0x2ul) /* RCC APB1HLPENR: CRSLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HLPENR_SWPLPEN_SHIFT (2ul) /* RCC APB1HLPENR: SWPLPEN (Bit 2) */
#define RCC_APB1HLPENR_SWPLPEN (0x4ul) /* RCC APB1HLPENR: SWPLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HLPENR_OPAMPLPEN_SHIFT (4ul) /* RCC APB1HLPENR: OPAMPLPEN (Bit 4) */
#define RCC_APB1HLPENR_OPAMPLPEN (0x10ul) /* RCC APB1HLPENR: OPAMPLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HLPENR_MDIOSLPEN_SHIFT (5ul) /* RCC APB1HLPENR: MDIOSLPEN (Bit 5) */
#define RCC_APB1HLPENR_MDIOSLPEN (0x20ul) /* RCC APB1HLPENR: MDIOSLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HLPENR_FDCANLPEN_SHIFT (8ul) /* RCC APB1HLPENR: FDCANLPEN (Bit 8) */
#define RCC_APB1HLPENR_FDCANLPEN (0x100ul) /* RCC APB1HLPENR: FDCANLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB1HLPENR_CRSLPEN (0x2ul) /* RCC APB1HLPENR: CRSLPEN */
#define RCC_APB1HLPENR_SWPLPEN (0x4ul) /* RCC APB1HLPENR: SWPLPEN */
#define RCC_APB1HLPENR_OPAMPLPEN (0x10ul) /* RCC APB1HLPENR: OPAMPLPEN */
#define RCC_APB1HLPENR_MDIOSLPEN (0x20ul) /* RCC APB1HLPENR: MDIOSLPEN */
#define RCC_APB1HLPENR_FDCANLPEN (0x100ul) /* RCC APB1HLPENR: FDCANLPEN */
/* APB2 low power mode peripheral clock enable register */
#define RCC_APB2LPENR_TIM1LPEN_SHIFT (0ul) /* RCC APB2LPENR: TIM1LPEN (Bit 0) */
#define RCC_APB2LPENR_TIM1LPEN (0x1ul) /* RCC APB2LPENR: TIM1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_TIM8LPEN_SHIFT (1ul) /* RCC APB2LPENR: TIM8LPEN (Bit 1) */
#define RCC_APB2LPENR_TIM8LPEN (0x2ul) /* RCC APB2LPENR: TIM8LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_USART1LPEN_SHIFT (4ul) /* RCC APB2LPENR: USART1LPEN (Bit 4) */
#define RCC_APB2LPENR_USART1LPEN (0x10ul) /* RCC APB2LPENR: USART1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_USART6LPEN_SHIFT (5ul) /* RCC APB2LPENR: USART6LPEN (Bit 5) */
#define RCC_APB2LPENR_USART6LPEN (0x20ul) /* RCC APB2LPENR: USART6LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SPI1LPEN_SHIFT (12ul) /* RCC APB2LPENR: SPI1LPEN (Bit 12) */
#define RCC_APB2LPENR_SPI1LPEN (0x1000ul) /* RCC APB2LPENR: SPI1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SPI4LPEN_SHIFT (13ul) /* RCC APB2LPENR: SPI4LPEN (Bit 13) */
#define RCC_APB2LPENR_SPI4LPEN (0x2000ul) /* RCC APB2LPENR: SPI4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_TIM15LPEN_SHIFT (16ul) /* RCC APB2LPENR: TIM15LPEN (Bit 16) */
#define RCC_APB2LPENR_TIM15LPEN (0x10000ul) /* RCC APB2LPENR: TIM15LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_TIM16LPEN_SHIFT (17ul) /* RCC APB2LPENR: TIM16LPEN (Bit 17) */
#define RCC_APB2LPENR_TIM16LPEN (0x20000ul) /* RCC APB2LPENR: TIM16LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_TIM17LPEN_SHIFT (18ul) /* RCC APB2LPENR: TIM17LPEN (Bit 18) */
#define RCC_APB2LPENR_TIM17LPEN (0x40000ul) /* RCC APB2LPENR: TIM17LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SPI5LPEN_SHIFT (20ul) /* RCC APB2LPENR: SPI5LPEN (Bit 20) */
#define RCC_APB2LPENR_SPI5LPEN (0x100000ul) /* RCC APB2LPENR: SPI5LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SAI1LPEN_SHIFT (22ul) /* RCC APB2LPENR: SAI1LPEN (Bit 22) */
#define RCC_APB2LPENR_SAI1LPEN (0x400000ul) /* RCC APB2LPENR: SAI1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SAI2LPEN_SHIFT (23ul) /* RCC APB2LPENR: SAI2LPEN (Bit 23) */
#define RCC_APB2LPENR_SAI2LPEN (0x800000ul) /* RCC APB2LPENR: SAI2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_SAI3LPEN_SHIFT (24ul) /* RCC APB2LPENR: SAI3LPEN (Bit 24) */
#define RCC_APB2LPENR_SAI3LPEN (0x1000000ul) /* RCC APB2LPENR: SAI3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_DFSDM1LPEN_SHIFT (28ul) /* RCC APB2LPENR: DFSDM1LPEN (Bit 28) */
#define RCC_APB2LPENR_DFSDM1LPEN (0x10000000ul) /* RCC APB2LPENR: DFSDM1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_HRTIMLPEN_SHIFT (29ul) /* RCC APB2LPENR: HRTIMLPEN (Bit 29) */
#define RCC_APB2LPENR_HRTIMLPEN (0x20000000ul) /* RCC APB2LPENR: HRTIMLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB2LPENR_TIM1LPEN (0x1ul) /* RCC APB2LPENR: TIM1LPEN */
#define RCC_APB2LPENR_TIM8LPEN (0x2ul) /* RCC APB2LPENR: TIM8LPEN */
#define RCC_APB2LPENR_USART1LPEN (0x10ul) /* RCC APB2LPENR: USART1LPEN */
#define RCC_APB2LPENR_USART6LPEN (0x20ul) /* RCC APB2LPENR: USART6LPEN */
#define RCC_APB2LPENR_SPI1LPEN (0x1000ul) /* RCC APB2LPENR: SPI1LPEN */
#define RCC_APB2LPENR_SPI4LPEN (0x2000ul) /* RCC APB2LPENR: SPI4LPEN */
#define RCC_APB2LPENR_TIM15LPEN (0x10000ul) /* RCC APB2LPENR: TIM15LPEN */
#define RCC_APB2LPENR_TIM16LPEN (0x20000ul) /* RCC APB2LPENR: TIM16LPEN */
#define RCC_APB2LPENR_TIM17LPEN (0x40000ul) /* RCC APB2LPENR: TIM17LPEN */
#define RCC_APB2LPENR_SPI5LPEN (0x100000ul) /* RCC APB2LPENR: SPI5LPEN */
#define RCC_APB2LPENR_SAI1LPEN (0x400000ul) /* RCC APB2LPENR: SAI1LPEN */
#define RCC_APB2LPENR_SAI2LPEN (0x800000ul) /* RCC APB2LPENR: SAI2LPEN */
#define RCC_APB2LPENR_SAI3LPEN (0x1000000ul) /* RCC APB2LPENR: SAI3LPEN */
#define RCC_APB2LPENR_DFSDM1LPEN (0x10000000ul) /* RCC APB2LPENR: DFSDM1LPEN */
#define RCC_APB2LPENR_HRTIMLPEN (0x20000000ul) /* RCC APB2LPENR: HRTIMLPEN */
/* APB4 low power mode peripheral clock enable register */
#define RCC_APB4LPENR_SYSCFGLPEN_SHIFT (1ul) /* RCC APB4LPENR: SYSCFGLPEN (Bit 1) */
#define RCC_APB4LPENR_SYSCFGLPEN (0x2ul) /* RCC APB4LPENR: SYSCFGLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_LPUART1LPEN_SHIFT (3ul) /* RCC APB4LPENR: LPUART1LPEN (Bit 3) */
#define RCC_APB4LPENR_LPUART1LPEN (0x8ul) /* RCC APB4LPENR: LPUART1LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_SPI6LPEN_SHIFT (5ul) /* RCC APB4LPENR: SPI6LPEN (Bit 5) */
#define RCC_APB4LPENR_SPI6LPEN (0x20ul) /* RCC APB4LPENR: SPI6LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_I2C4LPEN_SHIFT (7ul) /* RCC APB4LPENR: I2C4LPEN (Bit 7) */
#define RCC_APB4LPENR_I2C4LPEN (0x80ul) /* RCC APB4LPENR: I2C4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_LPTIM2LPEN_SHIFT (9ul) /* RCC APB4LPENR: LPTIM2LPEN (Bit 9) */
#define RCC_APB4LPENR_LPTIM2LPEN (0x200ul) /* RCC APB4LPENR: LPTIM2LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_LPTIM3LPEN_SHIFT (10ul) /* RCC APB4LPENR: LPTIM3LPEN (Bit 10) */
#define RCC_APB4LPENR_LPTIM3LPEN (0x400ul) /* RCC APB4LPENR: LPTIM3LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_LPTIM4LPEN_SHIFT (11ul) /* RCC APB4LPENR: LPTIM4LPEN (Bit 11) */
#define RCC_APB4LPENR_LPTIM4LPEN (0x800ul) /* RCC APB4LPENR: LPTIM4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_LPTIM5LPEN_SHIFT (12ul) /* RCC APB4LPENR: LPTIM5LPEN (Bit 12) */
#define RCC_APB4LPENR_LPTIM5LPEN (0x1000ul) /* RCC APB4LPENR: LPTIM5LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_COMP12LPEN_SHIFT (14ul) /* RCC APB4LPENR: COMP12LPEN (Bit 14) */
#define RCC_APB4LPENR_COMP12LPEN (0x4000ul) /* RCC APB4LPENR: COMP12LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_VREFLPEN_SHIFT (15ul) /* RCC APB4LPENR: VREFLPEN (Bit 15) */
#define RCC_APB4LPENR_VREFLPEN (0x8000ul) /* RCC APB4LPENR: VREFLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_RTCAPBLPEN_SHIFT (16ul) /* RCC APB4LPENR: RTCAPBLPEN (Bit 16) */
#define RCC_APB4LPENR_RTCAPBLPEN (0x10000ul) /* RCC APB4LPENR: RTCAPBLPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_SAI4LPEN_SHIFT (21ul) /* RCC APB4LPENR: SAI4LPEN (Bit 21) */
#define RCC_APB4LPENR_SAI4LPEN (0x200000ul) /* RCC APB4LPENR: SAI4LPEN (Bitfield-Mask: 0x01) */
#define RCC_APB4LPENR_SYSCFGLPEN (0x2ul) /* RCC APB4LPENR: SYSCFGLPEN */
#define RCC_APB4LPENR_LPUART1LPEN (0x8ul) /* RCC APB4LPENR: LPUART1LPEN */
#define RCC_APB4LPENR_SPI6LPEN (0x20ul) /* RCC APB4LPENR: SPI6LPEN */
#define RCC_APB4LPENR_I2C4LPEN (0x80ul) /* RCC APB4LPENR: I2C4LPEN */
#define RCC_APB4LPENR_LPTIM2LPEN (0x200ul) /* RCC APB4LPENR: LPTIM2LPEN */
#define RCC_APB4LPENR_LPTIM3LPEN (0x400ul) /* RCC APB4LPENR: LPTIM3LPEN */
#define RCC_APB4LPENR_LPTIM4LPEN (0x800ul) /* RCC APB4LPENR: LPTIM4LPEN */
#define RCC_APB4LPENR_LPTIM5LPEN (0x1000ul) /* RCC APB4LPENR: LPTIM5LPEN */
#define RCC_APB4LPENR_COMP12LPEN (0x4000ul) /* RCC APB4LPENR: COMP12LPEN */
#define RCC_APB4LPENR_VREFLPEN (0x8000ul) /* RCC APB4LPENR: VREFLPEN */
#define RCC_APB4LPENR_RTCAPBLPEN (0x10000ul) /* RCC APB4LPENR: RTCAPBLPEN */
#define RCC_APB4LPENR_SAI4LPEN (0x200000ul) /* RCC APB4LPENR: SAI4LPEN */
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H */

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_lowputc.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "up_internal.h"
#include "up_arch.h"
#include "chip.h"
#include "chip/stm32_pinmap.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
#include "stm32_uart.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select USART parameters for the selected console */
#ifdef HAVE_CONSOLE
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32_CONSOLE_TX GPIO_USART1_TX
# define STM32_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32_CONSOLE_TX GPIO_USART2_TX
# define STM32_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32_CONSOLE_TX GPIO_USART3_TX
# define STM32_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
# define STM32_CONSOLE_TX GPIO_UART4_TX
# define STM32_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART5_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
# define STM32_CONSOLE_TX GPIO_UART5_TX
# define STM32_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART6_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART6EN
# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
# define STM32_CONSOLE_TX GPIO_USART6_TX
# define STM32_CONSOLE_RX GPIO_USART6_RX
# ifdef CONFIG_USART6_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART7_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN
# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART7_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP
# define STM32_CONSOLE_TX GPIO_UART7_TX
# define STM32_CONSOLE_RX GPIO_UART7_RX
# ifdef CONFIG_UART7_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR
# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART8_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN
# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART8_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP
# define STM32_CONSOLE_TX GPIO_UART8_TX
# define STM32_CONSOLE_RX GPIO_UART8_RX
# ifdef CONFIG_UART8_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR
# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if STM32_CONSOLE_BITS == 7
# define USART_CR_M01_VALUE USART_CR1_M1
# elif STM32_CONSOLE_BITS == 9
# define USART_CR_M01_VALUE USART_CR1_M0
# else /* STM32_CONSOLE_BITS == 8 */
# define USART_CR_M01_VALUE 0
# endif
# if STM32_CONSOLE_PARITY == 1
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
# elif STM32_CONSOLE_PARITY == 2
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
# else
# define USART_CR1_PARITY_VALUE 0
# endif
# define USART_CR1_CLRBITS \
(USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \
USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \
USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
# define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE)
/* CR2 settings */
# if STM32_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
# else
# define USART_CR2_STOP2_VALUE 0
# endif
# define USART_CR2_CLRBITS \
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \
USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
/* CR3 settings */
# define USART_CR3_CLRBITS \
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \
USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP | \
USART_CR1_SCARCNT_MASK)
# define USART_CR3_SETBITS 0
/* Only the STM32 F3 supports oversampling by 8 */
# undef USE_OVER8
/* Calculate USART BAUD rate divider */
/* Baud rate for standard USART (SPI mode included):
*
* In case of oversampling by 16, the equation is:
* baud = fCK / UARTDIV
* UARTDIV = fCK / baud
*
* In case of oversampling by 8, the equation is:
*
* baud = 2 * fCK / UARTDIV
* UARTDIV = 2 * fCK / baud
*/
# define STM32_USARTDIV8 \
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
# define STM32_USARTDIV16 \
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
/* Use oversampling by 8 only if the divisor is small. But what is small? */
# if STM32_USARTDIV8 > 100
# define STM32_BRR_VALUE STM32_USARTDIV16
# else
# define USE_OVER8 1
# define STM32_BRR_VALUE \
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
# endif
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output availabe as soon
* as possible.
*
****************************************************************************/
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c
*/
#ifdef STM32_CONSOLE_TX
stm32_configgpio(STM32_CONSOLE_TX);
#endif
#ifdef STM32_CONSOLE_RX
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Enable and configure the selected console device */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Configure CR2 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
/* Select oversampling by 8 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#ifdef USE_OVER8
cr |= USART_CR1_OVER8;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
}

77
arch/arm/src/stm32h7/stm32_lowputc.h Normal file
View File

@ -0,0 +1,77 @@
/************************************************************************************
* arch/arm/src/stm32h7/stm32_lowputc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level initialization
* of serial console.
*
************************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H */

30
arch/arm/src/stm32h7/stm32_start.c
View File

@ -54,9 +54,9 @@
# include "nvic.h"
#endif
// TODO: #include "stm32_rcc.h"
#include "stm32_rcc.h"
// TODO: #include "stm32_userspace.h"
// TODO: #include "stm32_lowputc.h"
#include "stm32_lowputc.h"
#include "stm32_start.h"
/****************************************************************************
@ -109,6 +109,20 @@ static void go_os_start(void *pv, unsigned int nbytes)
__attribute__ ((naked, no_instrument_function, noreturn));
#endif
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -358,9 +372,10 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
// TODO: stm32_clockconfig();
stm32_clockconfig();
stm32_fpuconfig();
// TODO: stm32_lowsetup();
stm32_lowsetup();
showprogress('A');
/* Enable/disable tightly coupled memories */
@ -369,18 +384,21 @@ void __start(void)
/* Initialize onboard resources */
stm32_boardinitialize();
showprogress('B');
/* Enable I- and D-Caches */
arch_dcache_writethrough();
arch_enable_icache();
arch_enable_dcache();
showprogress('C');
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
@ -391,9 +409,13 @@ void __start(void)
#ifdef CONFIG_BUILD_PROTECTED
stm32_userspace();
#endif
showprogress('E');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
#ifdef CONFIG_STACK_COLORATION
/* Set the IDLE stack to the coloration value and jump into os_start() */

240
arch/arm/src/stm32h7/stm32_uart.h Normal file
View File

@ -0,0 +1,240 @@
/************************************************************************************
* arch/arm/src/stm32h7/stm32_uart.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_UART_H
#define __ARCH_ARM_SRC_STM32H7_STM32_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip/stm32_uart.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
#if STM32H7_NUART < 4
# undef CONFIG_STM32H7_UART8
#endif
#if STM32H7_NUART < 3
# undef CONFIG_STM32H7_UART7
#endif
#if STM32H7_NUART < 2
# undef CONFIG_STM32H7_UART5
#endif
#if STM32H7_NUART < 1
# undef CONFIG_STM32H7_UART4
#endif
#if STM32H7_NUSART < 4
# undef CONFIG_STM32H7_USART6
#endif
#if STM32H7_NUSART < 3
# undef CONFIG_STM32H7_USART3
#endif
#if STM32H7_NUSART < 2
# undef CONFIG_STM32H7_USART2
#endif
#if STM32H7_NUSART < 1
# undef CONFIG_STM32H7_USART1
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \
defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \
defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \
defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1)
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define CONSOLE_UART 8
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
/* Is RS-485 used? */
#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \
defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485) || \
defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485) || \
defined(CONFIG_UART7_RS485) || defined(CONFIG_UART8_RS485)
# define HAVE_RS485 1
#endif
#ifdef HAVE_RS485
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
#else
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_serial_get_uart
*
* Description:
* Get serial driver structure for STM32 USART
*
************************************************************************************/
FAR uart_dev_t *stm32_serial_get_uart(int uart_num);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_UART_H */

74
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
View File

@ -102,7 +102,9 @@ static inline void rcc_reset(void)
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON | RCC_CR_CSION | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON |
RCC_CR_CSION | RCC_CR_PLL1ON |
RCC_CR_PLL2ON | RCC_CR_PLL3ON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -138,7 +140,17 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
// TODO: ...
#ifdef CONFIG_STM32H7_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN;
#endif
#ifdef CONFIG_STM32H7_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN;
#endif
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
@ -190,10 +202,10 @@ static inline void rcc_enableahb3(void)
}
/****************************************************************************
* Name: rcc_enableahb3
* Name: rcc_enableahb4
*
* Description:
* Enable selected AHB1 peripherals
* Enable selected AHB4 peripherals
*
****************************************************************************/
@ -207,7 +219,54 @@ static inline void rcc_enableahb4(void)
regval = getreg32(STM32_RCC_AHB4ENR);
// TODO: ...
/* Enable GPIO, GPIOB, ... GPIOK */
#if STM32H7_NGPIO > 0
regval |= (RCC_AHB4ENR_GPIOAEN
#if STM32H7_NGPIO > 1
| RCC_AHB4ENR_GPIOBEN
#endif
#if STM32H7_NGPIO > 2
| RCC_AHB4ENR_GPIOCEN
#endif
#if STM32H7_NGPIO > 3
| RCC_AHB4ENR_GPIODEN
#endif
#if STM32H7_NGPIO > 4
| RCC_AHB4ENR_GPIOEEN
#endif
#if STM32H7_NGPIO > 5
| RCC_AHB4ENR_GPIOFEN
#endif
#if STM32H7_NGPIO > 6
| RCC_AHB4ENR_GPIOGEN
#endif
#if STM32H7_NGPIO > 7
| RCC_AHB4ENR_GPIOHEN
#endif
#if STM32H7_NGPIO > 8
| RCC_AHB4ENR_GPIOIEN
#endif
#if STM32H7_NGPIO > 9
| RCC_AHB4ENR_GPIOJEN
#endif
#if STM32H7_NGPIO > 10
| RCC_AHB4ENR_GPIOKEN
#endif
);
#endif
#ifdef CONFIG_STM32H7_CRC
/* CRC clock enable */
regval |= RCC_AHB4ENR_CRCEN;
#endif
#ifdef CONFIG_STM32H7_BKPSRAM
/* Backup SRAM clock enable */
regval |= RCC_AHB4ENR_BKPSRAMEN;
#endif
putreg32(regval, STM32_RCC_AHB4ENR); /* Enable peripherals */
}
@ -507,7 +566,7 @@ static void stm32_stdclockconfig(void)
/* Select the PLL1 as system clock source */
regval = getreg32(STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= RCC_CFGR_SW_PLL1;
putreg32(regval, STM32_RCC_CFGR);
@ -654,8 +713,11 @@ static inline void rcc_enableperipherals(void)
rcc_enableahb1();
rcc_enableahb2();
rcc_enableahb3();
rcc_enableahb4();
rcc_enableapb1();
rcc_enableapb2();
rcc_enableapb3();
rcc_enableapb4();
}
/****************************************************************************