From 8289e3eb7cfd36bc96b9a4001610a2bfe5594159 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 10:30:27 -1000 Subject: [PATCH] Updated F7 RCC to support all pll and config registers --- .../arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h | 7 +- .../arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 101 +++++++++++++++-- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 102 ++++++++++++++++-- 4 files changed, 193 insertions(+), 19 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h index 0cdc92c727..881f17dc56 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h @@ -1,8 +1,9 @@ /**************************************************************************************************** * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -616,7 +617,7 @@ #define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ #define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) # define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) -#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */ /* Dedicated clocks configuration register 2 */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h index 23c8b2db0b..a63cc1911a 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -638,7 +638,7 @@ #define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ #define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) # define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) -#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */ #define RCC_DCKCFGR1_DFSDM1SEL (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */ #define RCC_DCKCFGR1_ADFSDM1SEL (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 1db43d2551..7ae301548a 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32f74xxx75xx_rcc.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -827,18 +828,38 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32F7_LTDC - /* Configure PLLSAI */ +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) + + /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIR - | STM32_RCC_PLLSAICFGR_PLLSAIQ); + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); - regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; - putreg32(regval, STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR1); + regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVR_MASK + | RCC_DCKCFGR1_SAI1SEL_MASK + | RCC_DCKCFGR1_SAI2SEL_MASK + | RCC_DCKCFGR1_TIMPRESEL); + + regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVR + | STM32_RCC_DCKCFGR1_SAI1SRC + | STM32_RCC_DCKCFGR1_SAI2SRC + | STM32_RCC_DCKCFGR1_TIMPRESRC); + + putreg32(regval, STM32_RCC_DCKCFGR1); + /* Enable PLLSAI */ @@ -852,6 +873,68 @@ static void stm32_stdclockconfig(void) { } #endif +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) + + /* Configure PLLI2S */ + + regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SP_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + | RCC_DCKCFGR2_USART2SEL_MASK + | RCC_DCKCFGR2_UART4SEL_MASK + | RCC_DCKCFGR2_UART5SEL_MASK + | RCC_DCKCFGR2_USART6SEL_MASK + | RCC_DCKCFGR2_UART7SEL_MASK + | RCC_DCKCFGR2_UART8SEL_MASK + | RCC_DCKCFGR2_I2C1SEL_MASK + | RCC_DCKCFGR2_I2C2SEL_MASK + | RCC_DCKCFGR2_I2C3SEL_MASK + | RCC_DCKCFGR2_I2C4SEL_MASK + | RCC_DCKCFGR2_LPTIM1SEL_MASK + | RCC_DCKCFGR2_CECSEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDMMCSEL_MASK); + + regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + | STM32_RCC_DCKCFGR2_USART2SRC + | STM32_RCC_DCKCFGR2_UART4SRC + | STM32_RCC_DCKCFGR2_UART5SRC + | STM32_RCC_DCKCFGR2_USART6SRC + | STM32_RCC_DCKCFGR2_UART7SRC + | STM32_RCC_DCKCFGR2_UART8SRC + | STM32_RCC_DCKCFGR2_I2C1SRC + | STM32_RCC_DCKCFGR2_I2C2SRC + | STM32_RCC_DCKCFGR2_I2C3SRC + | STM32_RCC_DCKCFGR2_I2C4SRC + | STM32_RCC_DCKCFGR2_LPTIM1SRC + | STM32_RCC_DCKCFGR2_CECSRC + | STM32_RCC_DCKCFGR2_CK48MSRC + | STM32_RCC_DCKCFGR2_SDMMCSRC); + + putreg32(regval, STM32_RCC_DCKCFGR2); + + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 74d58b52ad..d24705d5fd 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -224,6 +224,7 @@ static inline void rcc_enableahb1(void) /* USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; + #endif /* CONFIG_STM32F7_OTGHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ @@ -823,18 +824,41 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32F7_LTDC +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) + /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIR - | STM32_RCC_PLLSAICFGR_PLLSAIQ); + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); - regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; - putreg32(regval, STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR1); + regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVR_MASK + | RCC_DCKCFGR1_SAI1SEL_MASK + | RCC_DCKCFGR1_SAI2SEL_MASK + | RCC_DCKCFGR1_TIMPRESEL + | RCC_DCKCFGR1_DFSDM1SEL + | RCC_DCKCFGR1_ADFSDM1SEL); + + regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVR + | STM32_RCC_DCKCFGR1_SAI1SRC + | STM32_RCC_DCKCFGR1_SAI2SRC + | STM32_RCC_DCKCFGR1_TIMPRESRC + | STM32_RCC_DCKCFGR1_DFSDM1SRC + | STM32_RCC_DCKCFGR1_ADFSDM1SRC); + + putreg32(regval, STM32_RCC_DCKCFGR1); /* Enable PLLSAI */ @@ -848,6 +872,72 @@ static void stm32_stdclockconfig(void) { } #endif +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) + + /* Configure PLLI2S */ + + regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SP_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + | RCC_DCKCFGR2_USART2SEL_MASK + | RCC_DCKCFGR2_UART4SEL_MASK + | RCC_DCKCFGR2_UART5SEL_MASK + | RCC_DCKCFGR2_USART6SEL_MASK + | RCC_DCKCFGR2_UART7SEL_MASK + | RCC_DCKCFGR2_UART8SEL_MASK + | RCC_DCKCFGR2_I2C1SEL_MASK + | RCC_DCKCFGR2_I2C2SEL_MASK + | RCC_DCKCFGR2_I2C3SEL_MASK + | RCC_DCKCFGR2_I2C4SEL_MASK + | RCC_DCKCFGR2_LPTIM1SEL_MASK + | RCC_DCKCFGR2_CECSEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDMMCSEL_MASK + | RCC_DCKCFGR2_SDMMC2SEL_MASK + | RCC_DCKCFGR2_DSISELL_MASK); + + regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + | STM32_RCC_DCKCFGR2_USART2SRC + | STM32_RCC_DCKCFGR2_UART4SRC + | STM32_RCC_DCKCFGR2_UART5SRC + | STM32_RCC_DCKCFGR2_USART6SRC + | STM32_RCC_DCKCFGR2_UART7SRC + | STM32_RCC_DCKCFGR2_UART8SRC + | STM32_RCC_DCKCFGR2_I2C1SRC + | STM32_RCC_DCKCFGR2_I2C2SRC + | STM32_RCC_DCKCFGR2_I2C3SRC + | STM32_RCC_DCKCFGR2_I2C4SRC + | STM32_RCC_DCKCFGR2_LPTIM1SRC + | STM32_RCC_DCKCFGR2_CECSRC + | STM32_RCC_DCKCFGR2_CK48MSRC + | STM32_RCC_DCKCFGR2_SDMMCSRC + | STM32_RCC_DCKCFGR2_SDMMC2SRC + | STM32_RCC_DCKCFGR2_DSISRC); + + putreg32(regval, STM32_RCC_DCKCFGR2); + + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) /* Low speed internal clock source LSI */