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SAM4E: Add CAN and RSWDT register definition header files

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This commit is contained in:
Gregory Nutt 2014-02-26 14:14:19 -06:00
parent 07adb58099
commit 82bd647951
30 changed files with 461 additions and 37 deletions
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2
arch/arm/src/sam34/chip/sam3u_pio.h
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@ -109,7 +109,7 @@
/* 0x00ec-0x00f8: Reserved */
/* 0x0100-0x0144: Reserved */
/* PIO register adresses ****************************************************************/
/* PIO register addresses ***************************************************************/
#define PIOA (0)
#define PIOB (1)

2
arch/arm/src/sam34/chip/sam4e_pio.h
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@ -123,7 +123,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
/* PIO register adresses ****************************************************************/
/* PIO register addresses ***************************************************************/
#define PIOA (0)
#define PIOB (1)

2
arch/arm/src/sam34/chip/sam4l_bpm.h
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@ -65,7 +65,7 @@
#define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */
#define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */
/* BPM register adresses ***************************************************************/
/* BPM register addresses **************************************************************/
#define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET)
#define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET)

2
arch/arm/src/sam34/chip/sam4l_bscif.h
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@ -85,7 +85,7 @@
#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */
#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */
/* BSCIF register adresses **************************************************************/
/* BSCIF register addresses *************************************************************/
#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET)
#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET)

8
arch/arm/src/sam34/chip/sam4l_gpio.h
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@ -194,7 +194,7 @@
#define SAM_GPIOB_BASE SAM_GPION_BASE(SAM_GPIOB)
#define SAM_GPIOC_BASE SAM_GPION_BASE(SAM_GPIOC)
/* GPIO register adresses ***************************************************************/
/* GPIO register addresses **************************************************************/
#define SAM_GPIO_GPER(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIO_GPERS(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET)
@ -289,7 +289,7 @@
#define SAM_GPIO_PARAMETER(n) (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIO_VERSION (n) (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTA register adresses *********************************************************/
/* GPIO PORTA register addresses ********************************************************/
#define SAM_GPIOA_GPER (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOA_GPERS (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET)
@ -384,7 +384,7 @@
#define SAM_GPIOA_PARAMETER (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOA_VERSION (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTB register adresses *********************************************************/
/* GPIO PORTB register addresses ********************************************************/
#define SAM_GPIOB_GPER (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOB_GPERS (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET)
@ -479,7 +479,7 @@
#define SAM_GPIOB_PARAMETER (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOB_VERSION (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTC register adresses *********************************************************/
/* GPIO PORTC register addresses ********************************************************/
#define SAM_GPIOC_GPER (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOC_GPERS (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET)

2
arch/arm/src/sam34/chip/sam4l_lcdca.h
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@ -82,7 +82,7 @@
#define SAM_LCDCA_IMR_OFFSET 0x0060 /* Interrupt Mask Register */
#define SAM_LCDCA_VERSION_OFFSET 0x0064 /* Version Register */
/* LCDCA register adresses ***********************************************************/
/* LCDCA register addresses **********************************************************/
#define SAM_LCDCA_CR (SAM_LCDCA_BASE+SAM_LCDCA_CR_OFFSET)
#define SAM_LCDCA_CFG (SAM_LCDCA_BASE+SAM_LCDCA_CFG_OFFSET)

4
arch/arm/src/sam34/chip/sam4l_pdca.h
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@ -89,7 +89,7 @@
#define SAM_PDCA_VERSION_OFFSET 0x834 /* Version Register */
/* PDCA channel adresses ****************************************************************/
/* PDCA channel addresses ***************************************************************/
/* Channel register base addresses */
#define SAM_PDCA_CHAN(n) (SAM_PDCA_BASE+SAM_PDCA_CHAN_OFFSET(n))
@ -110,7 +110,7 @@
#define SAM_PDCA_CHAN14 (SAM_PDCA_BASE+SAM_PDCA_CHAN14_OFFSET)
#define SAM_PDCA_CHAN15 (SAM_PDCA_BASE+SAM_PDCA_CHAN15_OFFSET)
/* PDCA register adresses ***************************************************************/
/* PDCA register addresses **************************************************************/
/* Channel register addresses */
#define SAM_PDCA_MAR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MAR_OFFSET)

2
arch/arm/src/sam34/chip/sam4l_picouart.h
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@ -57,7 +57,7 @@
#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
/* PICOUART register adresses ***********************************************************/
/* PICOUART register addresses **********************************************************/
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */

2
arch/arm/src/sam34/chip/sam4l_scif.h
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@ -98,7 +98,7 @@
#define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */
#define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */
/* SCIF register adresses ***************************************************************/
/* SCIF register addresses **************************************************************/
#define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET)
#define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET)

2
arch/arm/src/sam34/chip/sam4l_usart.h
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@ -79,7 +79,7 @@
#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */
/* 0x0100-0x0124: PDC Area */
/* USART register adresses **********************************************************************/
/* USART register addresses *********************************************************************/
#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET)
#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET)

2
arch/arm/src/sam34/chip/sam4l_wdt.h
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@ -61,7 +61,7 @@
#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */
#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */
/* WDT register adresses ***************************************************************/
/* WDT register addresses **************************************************************/
#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET)
#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET)

2
arch/arm/src/sam34/chip/sam4s_pio.h
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@ -121,7 +121,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
/* PIO register adresses ****************************************************************/
/* PIO register addresses ***************************************************************/
#define PIOA (0)
#define PIOB (1)

2
arch/arm/src/sam34/chip/sam_adc.h
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@ -75,7 +75,7 @@
#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
/* ADC register adresses ***************************************************************/
/* ADC register addresses **************************************************************/
#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET)

319
arch/arm/src/sam34/chip/sam_can.h Normal file
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@ -0,0 +1,319 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_can.h
* Controller Area Network (CAN) for the SAM4E
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
#define SAM_CAN_NMBOXES 8 /* 8 Mailboxes */
#define SAM_CAN_MBOX(n) (n)
#define SAM_CAN_MBOX0 0
#define SAM_CAN_MBOX1 1
#define SAM_CAN_MBOX2 2
#define SAM_CAN_MBOX3 3
#define SAM_CAN_MBOX4 4
#define SAM_CAN_MBOX5 5
#define SAM_CAN_MBOX6 6
#define SAM_CAN_MBOX7 7
/* CAN register offsets *****************************************************************/
#define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */
#define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */
#define SAM_CAN_IDR_OFFSET 0x0008 /* Interrupt Disable Register */
#define SAM_CAN_IMR_OFFSET 0x000c /* Interrupt Mask Register */
#define SAM_CAN_SR_OFFSET 0x0010 /* Status Register */
#define SAM_CAN_BR_OFFSET 0x0014 /* Baudrate Register */
#define SAM_CAN_TIM_OFFSET 0x0018 /* Timer Register */
#define SAM_CAN_TIMESTP_OFFSET 0x001c /* Timestamp Register */
#define SAM_CAN_ECR_OFFSET 0x0020 /* Error Counter Register */
#define SAM_CAN_TCR_OFFSET 0x0024 /* Transfer Command Register */
#define SAM_CAN_ACR_OFFSET 0x0028 /* Abort Command Register */
/* 0x002c-0x00e0: Reserved */
#define SAM_CAN_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_CAN_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* 0x00eC-0x01fc: Reserved */
/* Mailbox Registers */
#define SAM_CAN_MBOX_OFFSET(n) (0x0200+((n) << 5))
#define SAM_CAN_MMR_OFFSET 0x0000 /* Mailbox Mode Register */
#define SAM_CAN_MAM_OFFSET 0x0004 /* Mailbox Acceptance Mask Register */
#define SAM_CAN_MID_OFFSET 0x0008 /* Mailbox ID Register */
#define SAM_CAN_MFID_OFFSET 0x000c /* Mailbox Family ID Register */
#define SAM_CAN_MSR_OFFSET 0x0010 /* Mailbox Status Register */
#define SAM_CAN_MDL_OFFSET 0x0014 /* Mailbox Data Low Register */
#define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */
#define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */
/* CAN register addresses ***************************************************************/
#define SAM_CAN0_MR (SAM_CAN0_BASE+SAM_CAN_MR_OFFSET)
#define SAM_CAN0_IER (SAM_CAN0_BASE+SAM_CAN_IER_OFFSET)
#define SAM_CAN0_IDR (SAM_CAN0_BASE+SAM_CAN_IDR_OFFSET)
#define SAM_CAN0_IMR (SAM_CAN0_BASE+SAM_CAN_IMR_OFFSET)
#define SAM_CAN0_SR (SAM_CAN0_BASE+SAM_CAN_SR_OFFSET)
#define SAM_CAN0_BR (SAM_CAN0_BASE+SAM_CAN_BR_OFFSET)
#define SAM_CAN0_TIM (SAM_CAN0_BASE+SAM_CAN_TIM_OFFSET)
#define SAM_CAN0_TIMESTP (SAM_CAN0_BASE+SAM_CAN_TIMESTP_OFFSET)
#define SAM_CAN0_ECR (SAM_CAN0_BASE+SAM_CAN_ECR_OFFSET)
#define SAM_CAN0_TCR (SAM_CAN0_BASE+SAM_CAN_TCR_OFFSET)
#define SAM_CAN0_ACR (SAM_CAN0_BASE+SAM_CAN_ACR_OFFSET)
#define SAM_CAN0_WPMR (SAM_CAN0_BASE+SAM_CAN_WPMR_OFFSET)
#define SAM_CAN0_WPSR (SAM_CAN0_BASE+SAM_CAN_WPSR_OFFSET)
/* Mailbox Registers */
#define SAM_CAN0_MBOX_BASE(n) (SAM_CAN0_BASE+SAM_CAN_MBOX_OFFSET(n))
#define SAM_CAN0_MMR(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MMR_OFFSET)
#define SAM_CAN0_MAM(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MAM_OFFSET)
#define SAM_CAN0_MID(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MID_OFFSET)
#define SAM_CAN0_MFID(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MFID_OFFSET)
#define SAM_CAN0_MSR(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MSR_OFFSET)
#define SAM_CAN0_MDL(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MDL_OFFSET)
#define SAM_CAN0_MDH(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MDH_OFFSET)
#define SAM_CAN0_MCR(n) (SAM_CAN0_MBOX_BASE(n)+SAM_CAN_MCR_OFFSET)
#define SAM_CAN1_MR (SAM_CAN1_BASE+SAM_CAN_MR_OFFSET)
#define SAM_CAN1_IER (SAM_CAN1_BASE+SAM_CAN_IER_OFFSET)
#define SAM_CAN1_IDR (SAM_CAN1_BASE+SAM_CAN_IDR_OFFSET)
#define SAM_CAN1_IMR (SAM_CAN1_BASE+SAM_CAN_IMR_OFFSET)
#define SAM_CAN1_SR (SAM_CAN1_BASE+SAM_CAN_SR_OFFSET)
#define SAM_CAN1_BR (SAM_CAN1_BASE+SAM_CAN_BR_OFFSET)
#define SAM_CAN1_TIM (SAM_CAN1_BASE+SAM_CAN_TIM_OFFSET)
#define SAM_CAN1_TIMESTP (SAM_CAN1_BASE+SAM_CAN_TIMESTP_OFFSET)
#define SAM_CAN1_ECR (SAM_CAN1_BASE+SAM_CAN_ECR_OFFSET)
#define SAM_CAN1_TCR (SAM_CAN1_BASE+SAM_CAN_TCR_OFFSET)
#define SAM_CAN1_ACR (SAM_CAN1_BASE+SAM_CAN_ACR_OFFSET)
#define SAM_CAN1_WPMR (SAM_CAN1_BASE+SAM_CAN_WPMR_OFFSET)
#define SAM_CAN1_WPSR (SAM_CAN1_BASE+SAM_CAN_WPSR_OFFSET)
/* Mailbox Registers */
#define SAM_CAN1_MBOX_BASE(n) (SAM_CAN1_BASE+SAM_CAN_MBOX_OFFSET(n))
#define SAM_CAN1_MMR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MMR_OFFSET)
#define SAM_CAN1_MAM(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MAM_OFFSET)
#define SAM_CAN1_MID(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MID_OFFSET)
#define SAM_CAN1_MFID(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MFID_OFFSET)
#define SAM_CAN1_MSR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MSR_OFFSET)
#define SAM_CAN1_MDL(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MDL_OFFSET)
#define SAM_CAN1_MDH(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MDH_OFFSET)
#define SAM_CAN1_MCR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MCR_OFFSET)
/* CAN register bit definitions *********************************************************/
/* Mode Register */
#define CAN_MR_CANEN (1 << 0) /* Bit 0: CAN controller enable */
#define CAN_MR_LPM (1 << 1) /* Bit 1: Disable/enable low power mode */
#define CAN_MR_ABM (1 << 2) /* Bit 2: Disable/enable autobaud/listen mode */
#define CAN_MR_OVL (1 << 3) /* Bit 3: Disable/enable overload frame */
#define CAN_MR_TEOF (1 << 4) /* Bit 4: Timestamp messages at each end of frame */
#define CAN_MR_TTM (1 << 5) /* Bit 5: Disable/enable time triggered mode */
#define CAN_MR_TIMFRZ (1 << 6) /* Bit 6: Enable timer freeze */
#define CAN_MR_DRPT (1 << 7) /* Bit 7: Disable repeat */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask and Status Register */
#define CAN_INT_MB(n) (1 << (n)) /* Bit n: Mailbox n Interrupt */
#define CAN_INT_ERRA (1 << 16) /* Bit 16: Error Active Mode Interrupt */
#define CAN_INT_WARN (1 << 17) /* Bit 17: Warning Limit Interrupt */
#define CAN_INT_ERRP (1 << 18) /* Bit 18: Error Passive Mode Interrupt */
#define CAN_INT_BOFF (1 << 19) /* Bit 19: Bus Off Mode Interrupt */
#define CAN_INT_SLEEP (1 << 20) /* Bit 20: Sleep Interrupt */
#define CAN_INT_WAKEUP (1 << 21) /* Bit 21: Wake-up Interrupt */
#define CAN_INT_TOVF (1 << 22) /* Bit 22: Timer Overflow Interrupt */
#define CAN_INT_TSTP (1 << 23) /* Bit 23: TimeStamp Interrupt */
#define CAN_INT_CERR (1 << 24) /* Bit 24: CRC Error Interrupt */
#define CAN_INT_SERR (1 << 25) /* Bit 25: Stuffing Error Interrupt */
#define CAN_INT_AERR (1 << 26) /* Bit 26: Acknowledgement Error Interrupt */
#define CAN_INT_FERR (1 << 27) /* Bit 27: Form Error Interrupt */
#define CAN_INT_BERR (1 << 28) /* Bit 28: Bit Error Interrupt */
#define CAN_SR_RBSY (1 << 29) /* Bit 29: Receiver busy (SR only) */
#define CAN_SR_TBSY (1 << 30) /* Bit 30: Transmitter busy (SR only) */
#define CAN_SR_OVLSY (1 << 31) /* Bit 31: Overload busy (SR only) */
/* Baudrate Register */
#define CAN_BR_PHASE2_SHIFT (0) /* Bits 0-2: Phase 2 segment */
#define CAN_BR_PHASE2_MASK (7 << CAN_BR_PHASE2_SHIFT)
# define CAN_BR_PHASE2(n) ((uint32_t)(n) << CAN_BR_PHASE2_SHIFT)
#define CAN_BR_PHASE1_SHIFT (4) /* Bits 4-6: Phase 1 segment */
#define CAN_BR_PHASE1_MASK (7 << CAN_BR_PHASE1_SHIFT)
# define CAN_BR_PHASE1(n) ((uint32_t)(n) << CAN_BR_PHASE1_SHIFT)
#define CAN_BR_PROPAG_SHIFT (8) /* Bits 8-10: Programming time segment */
#define CAN_BR_PROPAG_MASK (7 << CAN_BR_PROPAG_SHIFT)
# define CAN_BR_PROPAG(n) ((uint32_t)(n) << CAN_BR_PROPAG_SHIFT)
#define CAN_BR_SJW_SHIFT (12) /* Bits 12-13: Re-synchronization jump width */
#define CAN_BR_SJW_MASK (3 << CAN_BR_SJW_SHIFT)
# define CAN_BR_SJW(n) ((uint32_t)(n) << CAN_BR_SJW_SHIFT)
#define CAN_BR_BRP_SHIFT (16) /* Bits 16-22: Baudrate Prescaler */
#define CAN_BR_BRP_MASK (127 << CAN_BR_BRP_SHIFT)
# define CAN_BR_BRP(n) ((uint32_t)(n) << CAN_BR_BRP_SHIFT)
#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode
/* Timer Register */
#define CAN_TIM_MASK (0x0000ffff) /* Bits 0-15: Timer */
/* Timestamp Register */
#define CAN_TIMESTP_MASK (0x0000ffff) /* Bits 0-15: Timestamp */
/* Error Counter Register */
#define CAN_ECR_REC_SHIFT (0) /* Bits 0-7: Receive Error Counter */
#define CAN_ECR_REC_MASK (0xff << CAN_ECR_REC_SHIFT)
# define CAN_ECR_REC(n) ((uint32_t)(n) << CAN_ECR_REC_SHIFT)
#define CAN_ECR_TEC_SHIFT (16) /* Bits 16-23: Transmit Error Counter */
#define CAN_ECR_TEC_MASK (0xff << CAN_ECR_TEC_SHIFT)
# define CAN_ECR_TEC(n) ((uint32_t)(n) << CAN_ECR_TEC_SHIFT)
/* Transfer Command Register */
#define CAN_TCR_MB(n) (1 << (n)) /* Bit (n): Transfer Request for Mailbox n */
#define CAN_TCR_TIMRST (1 << 31) /* Bit 31: Timer Reset */
/* Abort Command Register */
#define CAN_ACR_MB(n) (1 << (n)) /* Bit (n): Abort Request for Mailbox n */
/* Write Protect Mode Register */
#define CAN_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */
#define CAN_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
#define CAN_WPMR_WPKEY_MASK (0x00ffffff << CAN_WPMR_WPKEY_SHIFT)
# define CAN_WPMR_WPKEY (0x0043414e << CAN_WPMR_WPKEY_SHIFT)
/* Write Protect Status Register */
#define CAN_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */
#define CAN_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define CAN_WPSR_WPVSRC_MASK (0x0000ffff << CAN_WPSR_WPVSRC_SHIFT)
/* Mailbox Registers */
/* Mailbox Mode Register */
#define CAN_MMR_MTIMEMARK_SHIFT (0) /* Bits 0-15: Mailbox Timemark */
#define CAN_MMR_MTIMEMARK_MASK (0x0000ffff << CAN_MMR_MTIMEMARK_SHIFT)
# define CAN_MMR_MTIMEMARK(n) ((uint32_t)(n) << CAN_MMR_MTIMEMARK_SHIFT)
#define CAN_MMR_PRIOR_SHIFT (16) /* Bits 16-19: Mailbox Priority */
#define CAN_MMR_PRIOR_MASK (15 << CAN_MMR_PRIOR_SHIFT)
# define CAN_MMR_PRIOR(n) ((uint32_t)(n) << CAN_MMR_PRIOR_SHIFT)
#define CAN_MMR_MOT_SHIFT (24) /* Bits 24-26: Mailbox Object Type */
#define CAN_MMR_MOT_MASK (7 << CAN_MMR_MOT_SHIFT)
# define CAN_MMR_MOT_DISABLED (0 << CAN_MMR_MOT_SHIFT) /* Mailbox is disabled */
# define CAN_MMR_MOT_RX (1 << CAN_MMR_MOT_SHIFT) /* Reception Mailbox */
# define CAN_MMR_MOT_RXOVR (2 << CAN_MMR_MOT_SHIFT) /* Reception mailbox with overwrite */
# define CAN_MMR_MOT_TX (3 << CAN_MMR_MOT_SHIFT) /* Transmit mailbox */
# define CAN_MMR_MOT_CONSUMER (4 << CAN_MMR_MOT_SHIFT) /* Consumer Mailbox */
# define CAN_MMR_MOT_PRODUCER (5 << CAN_MMR_MOT_SHIFT) /* Producer Mailbox */
/* Mailbox Acceptance Mask Register */
#define CAN_MAM_MIDvB_SHIFT (0) /* Bits 0-18: Complementary bits for ID in extended frame mode */
#define CAN_MAM_MIDvB_MASK (0x0003ffff << CAN_MAM_MIDvB_SHIFT)
# define CAN_MAM_MIDvB(n) ((uint32_t)(n) << CAN_MAM_MIDvB_SHIFT)
#define CAN_MAM_MIDvA_SHIFT (18) /* Bits 18-28: ID for standard frame mode */
#define CAN_MAM_MIDvA_MASK (0x000007ff << CAN_MAM_MIDvA_SHIFT)
# define CAN_MAM_MIDvA(n) ((uint32_t)(n) << CAN_MAM_MIDvA_SHIFT)
#define CAN_MAM_MIDE (1 << 29) /* Bit 29: ID Version */
/* Mailbox ID Register */
#define CAN_MID_MIDvB_SHIFT (0) /* Bits 0-18: Complementary bits for ID in extended frame mode */
#define CAN_MID_MIDvB_MASK (0x0003ffff << CAN_MID_MIDvB_SHIFT)
# define CAN_MID_MIDvB(n) ((uint32_t)(n) << CAN_MID_MIDvB_SHIFT)
#define CAN_MID_MIDvA_SHIFT (18) /* Bits 18-28: ID for standard frame mode */
#define CAN_MID_MIDvA_MASK (0x000007ff << CAN_MID_MIDvA_SHIFT)
# define CAN_MID_MIDvA(n) ((uint32_t)(n) << CAN_MID_MIDvA_SHIFT)
#define CAN_MID_MIDE (1 << 29) /* Bit 29: ID Version */
/* Mailbox Family ID Register */
#define CAN_MFID_MASK (0x1fffffff) /* Bit 0-28: Family ID */
/* Mailbox Status Register */
#define CAN_MSR_MTIMESTAMP_SHIFT (0) /* Bits 0-15: Timer value */
#define CAN_MSR_MTIMESTAMP_MASK (0x0000ffff << CAN_MSR_MTIMESTAMP_SHIFT)
# define CAN_MSR_MTIMESTAMP(n) ((uint32_t)(n) << CAN_MSR_MTIMESTAMP_SHIFT)
#define CAN_MSR_MDLC_SHIFT (16) /* Bits 16-19: Mailbox Data Length Code */
#define CAN_MSR_MDLC_MASK (15 << CAN_MSR_MDLC_SHIFT)
# define CAN_MSR_MDLC(n) ((uint32_t)(n) << CAN_MSR_MDLC_SHIFT)
#define CAN_MSR_MRTR (1 << 20) /* Bit 20: Mailbox Remote Transmission Request */
#define CAN_MSR_MABT (1 << 22) /* Bit 22: Mailbox Message Abort */
#define CAN_MSR_MRDY (1 << 23) /* Bit 23: Mailbox Ready */
#define CAN_MSR_MMI (1 << 24) /* Bit 24: Mailbox Message Ignored */
/* Mailbox Data Low Register (32-bit value) */
/* Mailbox Data High Register (32-bit value) */
/* Mailbox Control Register */
#define CAN_MCR_MDLC_SHIFT (16) /* Bits 16-19: Mailbox Data Length Code */
#define CAN_MCR_MDLC_MASK (15 << CAN_MCR_MDLC_SHIFT)
# define CAN_MCR_MDLC(n) ((uint32_t)(n) << CAN_MCR_MDLC_SHIFT)
#define CAN_MCR_MRTR (1 << 20) /* Bit 20: Mailbox Remote Transmission Request */
#define CAN_MCR_MACR (1 << 22) /* Bit 22: Abort Request for Mailbox n */
#define CAN_MCR_MTCR (1 << 23) /* Bit 23: Mailbox Transfer Command */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H */

2
arch/arm/src/sam34/chip/sam_chipid.h
View File

@ -55,7 +55,7 @@
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
/* CHIPID register adresses *************************************************************/
/* CHIPID register addresses ************************************************************/
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)

2
arch/arm/src/sam34/chip/sam_dacc.h
View File

@ -66,7 +66,7 @@
#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
/* DACC register adresses ***************************************************************/
/* DACC register addresses **************************************************************/
#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)

2
arch/arm/src/sam34/chip/sam_dmac.h
View File

@ -91,7 +91,7 @@
# define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */
#endif
/* DMAC register adresses ***************************************************************/
/* DMAC register addresses **************************************************************/
/* Global Registers */

2
arch/arm/src/sam34/chip/sam_eefc.h
View File

@ -58,7 +58,7 @@
#define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
#define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
/* EEFC register adresses ***************************************************************/
/* EEFC register addresses **************************************************************/
#define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET)

2
arch/arm/src/sam34/chip/sam_gpbr.h
View File

@ -76,7 +76,7 @@
# define SAM_GPBR19_OFFSET 0x4c
#endif
/* GPBR register adresses ***************************************************************/
/* GPBR register addresses **************************************************************/
#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n))
#define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET)

2
arch/arm/src/sam34/chip/sam_hsmci.h
View File

@ -83,7 +83,7 @@
/* 0x0100-0x0124: Reserved for PCD registers */
#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
/* HSMCI register adresses **************************************************************/
/* HSMCI register addresses *************************************************************/
#define SAM_HSMCI_CR (SAM_MCI_BASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI_MR (SAM_MCI_BASE+SAM_HSMCI_MR_OFFSET)

2
arch/arm/src/sam34/chip/sam_matrix.h
View File

@ -126,7 +126,7 @@
#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
/* 0x0110 - 0x01fc: Reserved */
/* MATRIX register adresses *************************************************************/
/* MATRIX register addresses ************************************************************/
#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)

2
arch/arm/src/sam34/chip/sam_rstc.h
View File

@ -56,7 +56,7 @@
#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */
#define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */
/* RSTC register adresses ***************************************************************/
/* RSTC register addresses **************************************************************/
#define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET)
#define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET)

105
arch/arm/src/sam34/chip/sam_rswdt.h Normal file
View File

@ -0,0 +1,105 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rswdt.h
* Reinforced Safety Watchdog Timer (RSWDT) for the SAM4E
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* RSWDT register offsets ***************************************************************/
#define SAM_RSWDT_CR_OFFSET 0x0000 /* Control Register */
#define SAM_RSWDT_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_RSWDT_SR_OFFSET 0x0008 /* Status Register */
/* RSWDT register addresses *************************************************************/
#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_RSWDT_CR_OFFSET)
#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_RSWDT_MR_OFFSET)
#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_RSWDT_SR_OFFSET)
/* RSWDT register bit definitions *******************************************************/
/* Watchdog Timer Control Register */
#define RSWDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
#define RSWDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSWDT_CR_KEY_MASK (0xff << RSWDT_CR_KEY_SHIFT)
# define RSWDT_CR_KEY (0xc4 << RSWDT_CR_KEY_SHIFT)
/* Watchdog Timer Mode Register */
#define RSWDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
#define RSWDT_MR_WDV_MASK (0xfff << RSWDT_MR_WDV_SHIFT)
# define RSWDT_MR_WDV(n) ((uint32_t)(n) << RSWDT_MR_WDV_SHIFT)
#define RSWDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
#define RSWDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
#define RSWDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
#define RSWDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
#define RSWDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */
#define RSWDT_MR_WDD_MASK (0xfff << RSWDT_MR_WDD_SHIFT)
# define RSWDT_MR_WDD(n) ((uint32_t)(n) << RSWDT_MR_WDD_SHIFT)
#define RSWDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
#define RSWDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
/* Watchdog Timer Status Register */
#define RSWDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
#define RSWDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H */

2
arch/arm/src/sam34/chip/sam_rtc.h
View File

@ -65,7 +65,7 @@
#define SAM_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */
#define SAM_RTC_VER_OFFSET 0x2c /* Valid Entry Register */
/* RTC register adresses ****************************************************************/
/* RTC register addresses ***************************************************************/
#define SAM_RTC_CR (SAM_RTC_BASE+SAM_RTC_CR_OFFSET)
#define SAM_RTC_MR (SAM_RTC_BASE+SAM_RTC_MR_OFFSET)

2
arch/arm/src/sam34/chip/sam_smc.h
View File

@ -123,7 +123,7 @@
# error Unrecognized SAM architecture
#endif
/* SMC register adresses ****************************************************************/
/* SMC register addresses ***************************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)

2
arch/arm/src/sam34/chip/sam_ssc.h
View File

@ -77,7 +77,7 @@
/* 0x050-0x0fc: Reserved */
/* 0x100-0x124: Reserved for PDC registers */
/* SSC register adresses ****************************************************************/
/* SSC register addresses ***************************************************************/
#define SAM_SSC_CR (SAM_SSC_BASE+SAM_SSC_CR_OFFSET)
#define SAM_SSC_CMR (SAM_SSC_BASE+SAM_SSC_CMR_OFFSET)

2
arch/arm/src/sam34/chip/sam_twi.h
View File

@ -69,7 +69,7 @@
# define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */
#endif
/* TWI register adresses ****************************************************************/
/* TWI register addresses ***************************************************************/
#define SAM_TWI_CR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CR_OFFSET)
#define SAM_TWI_MMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_MMR_OFFSET)

2
arch/arm/src/sam34/chip/sam_uart.h
View File

@ -83,7 +83,7 @@
#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only, Not SAM4E) */
/* 0x0100-0x0124: PDC Area (Common) */
/* UART register adresses ***********************************************************************/
/* UART register addresses **********************************************************************/
#define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET)
#define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET)

2
arch/arm/src/sam34/chip/sam_udphs.h
View File

@ -90,7 +90,7 @@
#define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
#define SAM_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
/* UDPHS register adresses **************************************************************/
/* UDPHS register addresses *************************************************************/
#define SAM_UDPHS_CTRL (SAM_UDPHS_BASE+SAM_UDPHS_CTRL_OFFSET)
#define SAM_UDPHS_FNUM (SAM_UDPHS_BASE+SAM_UDPHS_FNUM_OFFSET)

12
arch/arm/src/sam34/chip/sam_wdt.h
View File

@ -34,8 +34,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
/****************************************************************************************
* Included Files
@ -50,19 +50,19 @@
* Pre-processor Definitions
****************************************************************************************/
/* WDT register offsets ****************************************************************/
/* WDT register offsets *****************************************************************/
#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */
#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */
#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */
/* WDT register adresses ***************************************************************/
/* WDT register addresses ***************************************************************/
#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET)
#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET)
#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET)
/* WDT register bit definitions ********************************************************/
/* WDT register bit definitions *********************************************************/
/* Watchdog Timer Control Register */
#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
@ -102,4 +102,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H */
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */