init global interrupt in timer mode
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f02d3808a3
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82c865e2b0
@ -79,6 +79,7 @@
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#ifndef CONFIG_ADC0_MASK
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#define CONFIG_ADC0_MASK 0x01
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#endif
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#ifndef CONFIG_ADC0_FREQ
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#define CONFIG_ADC0_FREQ 0
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#endif
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@ -227,61 +228,61 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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/* do pin configuration if defined */
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#ifdef PINCONF_ADC0_C0
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#ifdef PINCONF_ADC0_CH0
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if ((priv->mask & 0x01) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C0);
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lpc43_pin_config(PINCONF_ADC0_CH0);
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}
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#endif /* PINCONF_ADC0_C0 */
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#endif /* PINCONF_ADC0_CH0 */
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#ifdef PINCONF_ADC0_C1
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#ifdef PINCONF_ADC0_CH1
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if ((priv->mask & 0x02) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C1);
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lpc43_pin_config(PINCONF_ADC0_CH1);
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}
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#endif /* PINCONF_ADC0_C1 */
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#endif /* PINCONF_ADC0_CH1 */
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#ifdef PINCONF_ADC0_C2
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#ifdef PINCONF_ADC0_CH2
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if ((priv->mask & 0x04) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C2);
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lpc43_pin_config(PINCONF_ADC0_CH2);
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}
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#endif /* PINCONF_ADC0_C2 */
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#endif /* PINCONF_ADC0_CH2 */
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#ifdef PINCONF_ADC0_C3
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#ifdef PINCONF_ADC0_CH3
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if ((priv->mask & 0x08) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C3);
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lpc43_pin_config(PINCONF_ADC0_CH3);
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}
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#endif /* PINCONF_ADC0_C3 */
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#endif /* PINCONF_ADC0_CH3 */
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#ifdef PINCONF_ADC0_C4
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#ifdef PINCONF_ADC0_CH4
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if ((priv->mask & 0x10) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C4);
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lpc43_pin_config(PINCONF_ADC0_CH4);
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}
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#endif /* PINCONF_ADC0_C4 */
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#endif /* PINCONF_ADC0_CH4 */
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#ifdef PINCONF_ADC0_C5
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#ifdef PINCONF_ADC0_CH5
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if ((priv->mask & 0x20) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C5);
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lpc43_pin_config(PINCONF_ADC0_CH5);
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}
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#endif /* PINCONF_ADC0_C5 */
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#endif /* PINCONF_ADC0_CH5 */
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#ifdef PINCONF_ADC0_C6
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#ifdef PINCONF_ADC0_CH6
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if ((priv->mask & 0x40) != 0)
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{
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lpc43_pin_config(PINCONF_ADC0_C6);
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lpc43_pin_config(PINCONF_ADC0_CH6);
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}
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#endif /* PINCONF_ADC0_C6 */
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#endif /* PINCONF_ADC0_CH6 */
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#ifdef PINCONF_ADC0_C7
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#ifdef PINCONF_ADC0_CH7
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if ((priv->mask & 0x80) != 0)
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{
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lpc43_configgpio(PINCONF_ADC0_C7);
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lpc43_configgpio(PINCONF_ADC0_CH7);
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}
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#endif /* PINCONF_ADC0_C7 */
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#endif /* PINCONF_ADC0_CH7 */
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irqrestore(flags);
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}
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@ -351,10 +352,10 @@ static void adc_shutdown(FAR struct adc_dev_s *dev)
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static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
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{
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FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
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uint32_t regval = getreg32(LPC43_ADC0_CR);
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if (enable)
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{
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uint32_t regval = getreg32(LPC43_ADC0_CR);
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if (priv->freq == 0)
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{
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if ( priv->m_ch )
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@ -375,6 +376,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
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putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_PC_OFFSET); /* reset prescale counter */
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putreg32(0, LPC43_TIMER2_BASE+LPC43_TMR_TC_OFFSET); /* reset timer counter */
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putreg32(TMR_TCR_EN, LPC43_TIMER2_BASE+LPC43_TMR_TCR_OFFSET); /* enable the timer */
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putreg32(ADC_INTEN_GLOBAL, LPC43_ADC0_INTEN);
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}
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else
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{
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@ -422,12 +424,12 @@ static int adc_interrupt(int irq, void *context)
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if( priv->timer)
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{
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putreg32(TMR_EMR_EMC0_SET, LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET);
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putreg32(TMR_EMR_EMC0_SET, LPC43_TIMER2_BASE+LPC43_TMR_EMR_OFFSET); /* clear EM0 bit by resetting default value */
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}
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if (priv->freq == 0 && priv->m_ch )
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{
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regval = getreg32(LPC43_ADC0_CR);
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regval = getreg32(LPC43_ADC0_CR); /* clear burst while single conversation */
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regval &= ~ADC_CR_BURST;
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putreg32(regval, LPC43_ADC0_CR);
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}
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