Add PHY register definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2630 42af7a65-404d-4744-a932-0658087f49c3
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@ -44,7 +44,12 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* A total of seven instructions are implemented on the ENC28J60 */
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/* ENC28J60 Commands ********************************************************/
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/* A total of seven instructions are implemented on the ENC28J60. Where:
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*
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* aaaaaa is the 5-bit address of a control register, and
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* dddddddd is one or more bytes of data that may accompany the command.
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*/
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#define ENC28J60_RCR (0x00) /* Read Control Register
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* 000 | aaaaa | (Registe value returned)) */
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@ -61,20 +66,21 @@
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#define ENC28J60_SRC (0xff) /* System Reset
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* 111 | 11111 | (No data) */
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/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC commands.
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* The following identifies all ENC28J60 control registers. The Control register
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* memory is partitioned into four banks, selectable by the bank select bits,
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* BSEL1:BSEL0, in the ECON1 register.
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/* Global Control Registers *************************************************/
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/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC
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* commands. The following identifies all ENC28J60 control registers. The
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* control register memory is partitioned into four banks, selectable by the
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* bank select bits, BSEL1:BSEL0, in the ECON1 register.
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*
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* The last five locations (0x1b to 0x1f) of all banks point to a common set of
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* registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used
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* in controlling and monitoring the operation of the device. Their common
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* mapping allows easy access without switching the bank.
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* The last five locations (0x1b to 0x1f) of all banks point to a common set
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* of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers
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* usedin controlling and monitoring the operation of the device. Their
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* common mapping allows easy access without switching the bank.
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*
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* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
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* MII registers. Register names starting with E belong to the ETH group. Similarly,
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* registers names starting with MA belong to the MAC group and registers prefixed
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* with MI belong to the MII group.
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* MII registers. Register names starting with E belong to the ETH group.
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* Similarly, registers names starting with MA belong to the MAC group and
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* registers prefixed with MI belong to the MII group.
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*/
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#define EIE (0x1b) /* Ethernet Interrupt Enable Register */
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@ -83,9 +89,66 @@
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#define ECON2 (0x1e) /* Ethernet Control 2 Register */
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#define ECON1 (0x1f) /* Ethernet Control 1 Register */
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/* The remaining control registers are identified with a a 5 bit address and a
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* bank selection. We pack the bank number and the control register address
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* together to keep the design simpler.
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/* Ethernet Interrupt Enable Register Bit Definitions */
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
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#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
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/* Bit 2: Reserved */
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#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
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#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
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#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
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#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
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#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
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/* Ethernet Interrupt Request Register Bit Definitions */
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#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
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#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
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/* Bit 2: Reserved */
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#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
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#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
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#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
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#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
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/* Bit 7: Reserved */
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/* Ethernet Status Register Bit Definitions */
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#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
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#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
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#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
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/* Bit 3: Reserved */
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#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
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/* Bit 5: Reserved */
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#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
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#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
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/* Ethernet Control 1 Register Bit Definitions */
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#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
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#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
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# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
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# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
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# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
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# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
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#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
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#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
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#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
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#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
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#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
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#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
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/* Ethernet Control 2 Register */
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/* Bits 0-2: Reserved */
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#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
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/* Bit 4: Reserved */
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#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
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#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
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#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
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/* Banked Control Registers *************************************************/
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/* The remaining control registers are identified with a a 5 bit address and
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* a bank selection. We pack the bank number and the control register
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* address together to keep the design simpler.
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*/
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#define ENC28J60_ADDR_SHIFT (0) /* Bits 0-4: Register address */
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@ -206,61 +269,71 @@
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Ethernet Interrupt Enable Register Bit Definitions */
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/* PHY Registers ************************************************************/
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
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#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
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/* Bit 2: Reserved */
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#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
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#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
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#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
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#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
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#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
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#define PHCON1 (0x00)
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#define PHSTAT1 (0x01)
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#define PHHID1 (0x02)
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#define PHHID2 (0x03)
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#define PHCON2 (0x10)
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#define PHSTAT2 (0x11)
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#define PHIE (0x12)
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#define PHIR (0x13)
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#define PHLCON (0x14)
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/* Ethernet Interupt Request Register Bit Definitions */
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/* PHCON1 Register Bit Definitions */
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#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
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#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
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/* Bit 2: Reserved */
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#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
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#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
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#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
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#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
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/* Bit 7: Reserved */
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#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */
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#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */
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#define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */
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#define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */
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/* Ethernet Status Register Bit Definitions */
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/* PHSTAT1 Register Bit Definitions */
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#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
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#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
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#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
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/* Bit 3: Reserved */
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#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
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/* Bit 5: Reserved */
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#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
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#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
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#define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */
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#define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */
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#define PHSTAT1_PHDPX (1 << 11) /* Bit 11: PHY Half-Duplex Capable */
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#define PHSTAT1_PFDPX (1 << 12) /* Bit 12: PHY Full-Duplex Capable */
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/* Ethernet Control 1 Register Bit Definitions */
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/* PHCON2 Register Bit Definitions */
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#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
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#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
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# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
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# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
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# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
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# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
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#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
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#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
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#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
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#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
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#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
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#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
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#define PHCON2_HDLDIS (1 << 8) /* Bit 8: PHY Half-Duplex Loopback Disable */
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#define PHCON2_JABBER (1 << 10) /* Bit 10: Jabber Correction Disable */
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#define PHCON2_TXDIS (1 << 13) /* Bit 13: Twisted-Pair Transmitter Disable */
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#define PHCON2_FRCLINK (1 << 14) /* Bit 14: PHY Force Linkup */
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/* Ethernet Control 2 Register */
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/* Bits 0-2: Reserved */
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#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
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/* Bit 4: Reserved */
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#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
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#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
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#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
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/* PHSTAT2 Register Bit Definitions */
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#define PHSTAT2_PLRITY (1 << 5) /* Bit 5: Polarity Status */
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#define PHSTAT2_DPXSTAT (1 << 9) /* Bit 9: PHY Duplex Status */
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#define PHSTAT2_LSTAT (1 << 10) /* Bit 10: PHY Link Status */
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#define PHSTAT2_COLSTAT (1 << 11) /* Bit 11: PHY Collision Status */
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#define PHSTAT2_RXSTAT (1 << 12) /* Bit 12: PHY Receive Status */
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#define PHSTAT2_TXSTAT (1 << 13) /* Bit 13: PHY Transmit Status */
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/* PHIE Regiser Bit Definitions */
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#define PHIE_PGEIE (1 << 1)
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#define PHIE_PLNKIE (1 << 4)
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/* PHIR Regiser Bit Definitions */
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#define PHIR_PGIF (1 << 2)
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#define PHIR_PLNKIF (1 << 4)
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/* PHLCON Regiser Bit Definitions */
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#define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */
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#define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */
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#define PHLCON_LFRQ1 (1 << 3) /* Bit 3: " " " " " " " " " */
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#define PHLCON_LBCFG0 (1 << 4) /* Bit 4: LEDB Configuration */
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#define PHLCON_LBCFG1 (1 << 5) /* Bit 5: " " " " */
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#define PHLCON_LBCFG2 (1 << 6) /* Bit 6: " " " " */
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#define PHLCON_LBCFG3 (1 << 7) /* Bit 7: " " " " */
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#define PHLCON_LACFG0 (1 << 8) /* Bit 8: LEDA Configuration */
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#define PHLCON_LACFG1 (1 << 9) /* Bit 9: " " " " */
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#define PHLCON_LACFG2 (1 << 10) /* Bit 10: " " " " */
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#define PHLCON_LACFG3 (1 << 11) /* Bit 11: " " " " */
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/****************************************************************************
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* Public Types
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