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arch/risc-v: Attach exception handler in common place

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-04-08 15:09:58 +08:00 committed by Xiang Xiao
parent 36bc8d2131
commit 833211680a
18 changed files with 69 additions and 61 deletions
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2
arch/risc-v/src/bl602/Make.defs
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@ -34,7 +34,7 @@ CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_getnewintctx.c riscv_doirq.c
CMN_CSRCS += riscv_cpuindex.c
CMN_CSRCS += riscv_cpuindex.c riscv_exception.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += riscv_backtrace.c

4
arch/risc-v/src/bl602/bl602_irq.c
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@ -92,9 +92,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifndef CONFIG_SUPPRESS_INTERRUPTS

8
arch/risc-v/src/c906/c906_irq.c
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@ -93,13 +93,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_BUILD_PROTECTED
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#endif
riscv_exception_attach();
#ifndef CONFIG_SUPPRESS_INTERRUPTS

7
arch/risc-v/src/c906/c906_irq_dispatch.c
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@ -54,13 +54,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Check if fault happened */
if (vector < RISCV_IRQ_ECALLU)
{
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */
if (RISCV_IRQ_MEXT == irq)

48
arch/risc-v/src/common/riscv_exception.c
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@ -90,3 +90,51 @@ int riscv_exception(int mcause, void *regs, void *args)
return 0;
}
/****************************************************************************
* Name: riscv_exception_attach
*
* Description:
* Attach standard exception with suitable handler
*
****************************************************************************/
void riscv_exception_attach(void)
{
irq_attach(RISCV_IRQ_IAMISALIGNED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_IAFAULT, riscv_exception, NULL);
irq_attach(RISCV_IRQ_IINSTRUCTION, riscv_exception, NULL);
irq_attach(RISCV_IRQ_BPOINT, riscv_exception, NULL);
irq_attach(RISCV_IRQ_LAMISALIGNED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_LAFAULT, riscv_exception, NULL);
irq_attach(RISCV_IRQ_SAMISALIGNED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_SAFAULT, riscv_exception, NULL);
/* Attach the ecall interrupt handler */
#ifndef CONFIG_BUILD_FLAT
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#else
irq_attach(RISCV_IRQ_ECALLU, riscv_exception, NULL);
#endif
irq_attach(RISCV_IRQ_ECALLS, riscv_exception, NULL);
irq_attach(RISCV_IRQ_ECALLH, riscv_exception, NULL);
#ifndef CONFIG_ARCH_USE_S_MODE
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#else
irq_attach(RISCV_IRQ_ECALLM, riscv_exception, NULL);
#endif
irq_attach(RISCV_IRQ_INSTRUCTIONPF, riscv_exception, NULL);
irq_attach(RISCV_IRQ_LOADPF, riscv_exception, NULL);
irq_attach(RISCV_IRQ_RESERVED, riscv_exception, NULL);
irq_attach(RISCV_IRQ_STOREPF, riscv_exception, NULL);
#ifdef CONFIG_SMP
irq_attach(RISCV_IRQ_MSOFT, riscv_pause_handler, NULL);
#else
irq_attach(RISCV_IRQ_MSOFT, riscv_exception, NULL);
#endif
}

1
arch/risc-v/src/common/riscv_internal.h
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@ -229,6 +229,7 @@ void riscv_copystate(uintptr_t *dest, uintptr_t *src);
void riscv_sigdeliver(void);
int riscv_swint(int irq, void *context, void *arg);
uintptr_t riscv_get_newintctx(void);
void riscv_exception_attach(void);
#ifdef CONFIG_ARCH_FPU
void riscv_fpuconfig(void);

4
arch/risc-v/src/esp32c3/esp32c3_irq.c
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@ -112,9 +112,9 @@ void up_irqinitialize(void)
putreg32(ESP32C3_DEFAULT_INT_THRESHOLD, INTERRUPT_CPU_INT_THRESH_REG);
/* Attach the ECALL interrupt. */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifdef CONFIG_ESP32C3_GPIO_IRQ
/* Initialize GPIO interrupt support */

2
arch/risc-v/src/fe310/Make.defs
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@ -26,7 +26,7 @@ HEAD_ASRC = fe310_head.S
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_exception.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c

4
arch/risc-v/src/fe310/fe310_irq.c
View File

@ -86,9 +86,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifndef CONFIG_SUPPRESS_INTERRUPTS

11
arch/risc-v/src/k210/k210_irq.c
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@ -90,22 +90,15 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_BUILD_PROTECTED
irq_attach(RISCV_IRQ_ECALLU, riscv_swint, NULL);
#endif
riscv_exception_attach();
#ifdef CONFIG_SMP
/* Clear MSOFT for CPU0 */
putreg32(0, K210_CLINT_MSIP);
/* Setup MSOFT for CPU0 with pause handler */
irq_attach(RISCV_IRQ_MSOFT, riscv_pause_handler, NULL);
up_enable_irq(RISCV_IRQ_MSOFT);
#endif

7
arch/risc-v/src/k210/k210_irq_dispatch.c
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@ -55,13 +55,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Check if fault happened */
if (vector < RISCV_IRQ_ECALLU)
{
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */
if (RISCV_IRQ_MEXT == irq)

2
arch/risc-v/src/litex/Make.defs
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@ -26,7 +26,7 @@ HEAD_ASRC = litex_head.S
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c

4
arch/risc-v/src/litex/litex_irq.c
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@ -72,9 +72,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifndef CONFIG_SUPPRESS_INTERRUPTS

11
arch/risc-v/src/mpfs/mpfs_irq_dispatch.c
View File

@ -52,17 +52,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
int irq = (vector & 0x3f);
uintptr_t *epc = regs;
/* Check if fault happened */
if (vector < RISCV_IRQ_ECALLU ||
vector == RISCV_IRQ_INSTRUCTIONPF ||
vector == RISCV_IRQ_LOADPF ||
vector == RISCV_IRQ_STOREPF ||
vector == RISCV_IRQ_RESERVED)
{
riscv_exception(irq, regs, NULL);
}
if ((vector & RISCV_IRQ_BIT) != 0)
{
irq += MPFS_IRQ_ASYNC;

4
arch/risc-v/src/qemu-rv/qemu_rv_irq.c
View File

@ -84,9 +84,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifdef CONFIG_SMP
/* Clear MSOFT for CPU0 */

5
arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
View File

@ -58,11 +58,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
if (vector < RISCV_IRQ_ECALLM)
{
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */
if (RISCV_IRQ_MEXT == irq)

2
arch/risc-v/src/rv32m1/Make.defs
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@ -26,7 +26,7 @@ HEAD_ASRC = rv32m1_head.S
CMN_ASRCS = riscv_vectors.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c

4
arch/risc-v/src/rv32m1/rv32m1_irq.c
View File

@ -119,9 +119,9 @@ void up_irqinitialize(void)
CURRENT_REGS = NULL;
/* Attach the ecall interrupt handler */
/* Attach the common interrupt handler */
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
riscv_exception_attach();
#ifndef CONFIG_SUPPRESS_INTERRUPTS