From 835b129c94c4dcc206c3b383ada4bc3c266ec055 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 13 Apr 2021 14:55:41 +0200 Subject: [PATCH] stm32g4xx: add DBGMCU definitions --- arch/arm/src/stm32/Kconfig | 5 +++ arch/arm/src/stm32/hardware/stm32_dbgmcu.h | 45 ++++++++++++++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f3274bd6a2..708f35f736 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1928,6 +1928,7 @@ config STM32_STM32G4XXX bool default n select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_DBGMCU_V3 config STM32_STM32G4_CAT2 bool @@ -2571,6 +2572,10 @@ config STM32_HAVE_IP_DBGMCU_V2 bool default n +config STM32_HAVE_IP_DBGMCU_V3 + bool + default n + config STM32_HAVE_IP_I2C_V1 bool default n diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h index 9868388d55..8784fcc7a5 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h @@ -41,6 +41,11 @@ # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +# define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ +# define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ +# define STM32_DBGMCU_APB2_FZ 0xe004200e /* Debug MCU APB2 freeze register */ +#endif /* Register Bitfield Definitions ********************************************/ @@ -80,11 +85,12 @@ # define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ # define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ # define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ -#endif +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */ + +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 /* Debug MCU APB1 freeze register */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ @@ -139,7 +145,40 @@ # define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ #endif -#endif +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */ + +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 + +/* Debug MCU APB1 freeze 1 register */ + +# define DBGMCU_APB1FZ1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +# define DBGMCU_APB1FZ1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +# define DBGMCU_APB1FZ1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +# define DBGMCU_APB1FZ1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +# define DBGMCU_APB1FZ1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +# define DBGMCU_APB1FZ1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_I2C3STOP (1 << 30) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ +# define DBGMCU_APB1FZ1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 counter stopped when Core is halted */ + +/* Debug MCU APB1 freeze 2 register */ + +# define DBGMCU_APB1FZ2_I2C4STOP (1 << 1) /* Bit 30: SMBUS timeout mode stopped when Core is halted */ + +/* Debug MCU APB2 freeze register */ + +# define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */ +# define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 14: TIM8 stopped when core is halted */ +# define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */ +# define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */ +# define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */ +# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ +# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ + +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */ /**************************************************************************** * Public Types