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stm32g4xx: add DBGMCU definitions

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This commit is contained in:
raiden00pl 2021-04-13 14:55:41 +02:00 committed by Xiang Xiao
parent 0719976722
commit 835b129c94
2 changed files with 47 additions and 3 deletions
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5
arch/arm/src/stm32/Kconfig
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@ -1928,6 +1928,7 @@ config STM32_STM32G4XXX
bool bool
default n default n
select STM32_HAVE_DMAMUX select STM32_HAVE_DMAMUX
select STM32_HAVE_IP_DBGMCU_V3
config STM32_STM32G4_CAT2 config STM32_STM32G4_CAT2
bool bool
@ -2571,6 +2572,10 @@ config STM32_HAVE_IP_DBGMCU_V2
bool bool
default n default n
config STM32_HAVE_IP_DBGMCU_V3
bool
default n
config STM32_HAVE_IP_I2C_V1 config STM32_HAVE_IP_I2C_V1
bool bool
default n default n

45
arch/arm/src/stm32/hardware/stm32_dbgmcu.h
View File

@ -41,6 +41,11 @@
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
#endif #endif
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3
# define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */
# define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */
# define STM32_DBGMCU_APB2_FZ 0xe004200e /* Debug MCU APB2 freeze register */
#endif
/* Register Bitfield Definitions ********************************************/ /* Register Bitfield Definitions ********************************************/
@ -80,11 +85,12 @@
# define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ # define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */
# define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ # define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */
# define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ # define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */
#endif #endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
/* Debug MCU APB1 freeze register */ /* Debug MCU APB1 freeze register */
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
@ -139,7 +145,40 @@
# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */
# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */
#endif #endif
#endif #endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3
/* Debug MCU APB1 freeze 1 register */
# define DBGMCU_APB1FZ1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1FZ1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
# define DBGMCU_APB1FZ1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
# define DBGMCU_APB1FZ1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
# define DBGMCU_APB1FZ1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
# define DBGMCU_APB1FZ1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
# define DBGMCU_APB1FZ1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
# define DBGMCU_APB1FZ1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
# define DBGMCU_APB1FZ1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1FZ1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1FZ1_I2C3STOP (1 << 30) /* Bit 30: SMBUS timeout mode stopped when Core is halted */
# define DBGMCU_APB1FZ1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 counter stopped when Core is halted */
/* Debug MCU APB1 freeze 2 register */
# define DBGMCU_APB1FZ2_I2C4STOP (1 << 1) /* Bit 30: SMBUS timeout mode stopped when Core is halted */
/* Debug MCU APB2 freeze register */
# define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
# define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 14: TIM8 stopped when core is halted */
# define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
# define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
# define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */
# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types