arch/risc-v: Correct comments for current implementations
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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@ -492,7 +492,7 @@ struct xcptcontext
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/* These additional register save locations are used to implement the
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* signal delivery trampoline.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* REVISIT: Because there is only a reference of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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@ -64,8 +64,8 @@
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# define PRIxREG "016" PRIxPTR
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#endif
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/* In the RISC_V model, the state is copied from the stack to the TCB, but
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* only a referenced is passed to get the state from the TCB.
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/* In the RISC-V model, the state is saved in stack,
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* only a reference stored in TCB.
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*/
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#ifdef CONFIG_ARCH_FPU
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@ -214,8 +214,8 @@ int riscv_swint(int irq, void *context, void *arg)
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* A1 = restoreregs
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*
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* In this case, we simply need to set CURRENT_REGS to restore register
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* area referenced in the saved R1. context == CURRENT_REGS is the
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* normal exception return. By setting CURRENT_REGS = context[R1], we
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* area referenced in the saved A1. context == CURRENT_REGS is the
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* normal exception return. By setting CURRENT_REGS = context[A1], we
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* force the return to the saved context referenced in $a1.
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*/
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@ -364,9 +364,9 @@ int riscv_swint(int irq, void *context, void *arg)
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*
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* At this point, the following values are saved in context:
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*
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* R0 = SYS_pthread_start
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* R1 = entrypt
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* R2 = arg
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* A0 = SYS_pthread_start
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* A1 = entrypt
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* A2 = arg
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*/
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#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD)
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@ -396,11 +396,11 @@ int riscv_swint(int irq, void *context, void *arg)
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*
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* At this point, the following values are saved in context:
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*
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* R0 = SYS_signal_handler
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* R1 = sighand
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* R2 = signo
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* R3 = info
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* R4 = ucontext
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* A0 = SYS_signal_handler
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* A1 = sighand
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* A2 = signo
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* A3 = info
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* A4 = ucontext
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*/
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#ifndef CONFIG_BUILD_FLAT
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